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| Rev 1403 | Rev 1404 | ||
|---|---|---|---|
| Line 150... | Line 150... | ||
| 150 | 150 | ||
| 151 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
151 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
| 152 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
152 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
| 153 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
153 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
| - | 154 | if (rdev->gart.table.vram.robj) { |
|
| - | 155 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
|
| 154 | if (rdev->gart.table.vram.robj) { |
156 | if (likely(r == 0)) { |
| 155 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
157 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
| - | 158 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
|
| - | 159 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
|
| 156 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
160 | } |
| 157 | } |
161 | } |
| Line 158... | Line 162... | ||
| 158 | } |
162 | } |
| 159 | 163 | ||
| Line 506... | Line 510... | ||
| 506 | { |
510 | { |
| 507 | uint32_t tmp; |
511 | uint32_t tmp; |
| Line 508... | Line 512... | ||
| 508 | 512 | ||
| 509 | /* DDR for all card after R300 & IGP */ |
513 | /* DDR for all card after R300 & IGP */ |
| - | 514 | rdev->mc.vram_is_ddr = true; |
|
| 510 | rdev->mc.vram_is_ddr = true; |
515 | |
| 511 | tmp = RREG32(RADEON_MEM_CNTL); |
516 | tmp = RREG32(RADEON_MEM_CNTL); |
| - | 517 | tmp &= R300_MEM_NUM_CHANNELS_MASK; |
|
| 512 | if (tmp & R300_MEM_NUM_CHANNELS_MASK) { |
518 | switch (tmp) { |
| 513 | rdev->mc.vram_width = 128; |
519 | case 0: rdev->mc.vram_width = 64; break; |
| 514 | } else { |
520 | case 1: rdev->mc.vram_width = 128; break; |
| - | 521 | case 2: rdev->mc.vram_width = 256; break; |
|
| 515 | rdev->mc.vram_width = 64; |
522 | default: rdev->mc.vram_width = 128; break; |
| Line 516... | Line 523... | ||
| 516 | } |
523 | } |
| 517 | 524 | ||
| Line 1353... | Line 1360... | ||
| 1353 | // return r; |
1360 | // return r; |
| 1354 | // r = radeon_irq_kms_init(rdev); |
1361 | // r = radeon_irq_kms_init(rdev); |
| 1355 | // if (r) |
1362 | // if (r) |
| 1356 | // return r; |
1363 | // return r; |
| 1357 | /* Memory manager */ |
1364 | /* Memory manager */ |
| 1358 | r = radeon_object_init(rdev); |
1365 | r = radeon_bo_init(rdev); |
| 1359 | if (r) |
1366 | if (r) |
| 1360 | return r; |
1367 | return r; |
| 1361 | if (rdev->flags & RADEON_IS_PCIE) { |
1368 | if (rdev->flags & RADEON_IS_PCIE) { |
| 1362 | r = rv370_pcie_gart_init(rdev); |
1369 | r = rv370_pcie_gart_init(rdev); |
| 1363 | if (r) |
1370 | if (r) |
| Line 1380... | Line 1387... | ||
| 1380 | // r100_ib_fini(rdev); |
1387 | // r100_ib_fini(rdev); |
| 1381 | if (rdev->flags & RADEON_IS_PCIE) |
1388 | if (rdev->flags & RADEON_IS_PCIE) |
| 1382 | rv370_pcie_gart_fini(rdev); |
1389 | rv370_pcie_gart_fini(rdev); |
| 1383 | if (rdev->flags & RADEON_IS_PCI) |
1390 | if (rdev->flags & RADEON_IS_PCI) |
| 1384 | r100_pci_gart_fini(rdev); |
1391 | r100_pci_gart_fini(rdev); |
| 1385 | // radeon_irq_kms_fini(rdev); |
1392 | // radeon_agp_fini(rdev); |
| 1386 | rdev->accel_working = false; |
1393 | rdev->accel_working = false; |
| 1387 | } |
1394 | } |
| 1388 | return 0; |
1395 | return 0; |
| 1389 | } |
1396 | } |