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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | //#include |
28 | #include |
29 | #include "drmP.h" |
29 | #include "drmP.h" |
30 | #include "drm.h" |
30 | #include "drm.h" |
31 | #include "radeon_reg.h" |
31 | #include "radeon_reg.h" |
32 | #include "radeon.h" |
32 | #include "radeon.h" |
- | 33 | #include "radeon_drm.h" |
|
- | 34 | ||
- | 35 | #include "r300d.h" |
|
- | 36 | ||
- | 37 | #include "r300_reg_safe.h" |
|
33 | 38 | ||
34 | /* r300,r350,rv350,rv370,rv380 depends on : */ |
39 | /* r300,r350,rv350,rv370,rv380 depends on : */ |
35 | void r100_hdp_reset(struct radeon_device *rdev); |
40 | void r100_hdp_reset(struct radeon_device *rdev); |
36 | int r100_cp_reset(struct radeon_device *rdev); |
41 | int r100_cp_reset(struct radeon_device *rdev); |
37 | int r100_rb2d_reset(struct radeon_device *rdev); |
42 | int r100_rb2d_reset(struct radeon_device *rdev); |
38 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
43 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
39 | int r100_pci_gart_enable(struct radeon_device *rdev); |
44 | int r100_pci_gart_enable(struct radeon_device *rdev); |
40 | void r100_pci_gart_disable(struct radeon_device *rdev); |
- | |
41 | void r100_mc_setup(struct radeon_device *rdev); |
45 | void r100_mc_setup(struct radeon_device *rdev); |
42 | void r100_mc_disable_clients(struct radeon_device *rdev); |
46 | void r100_mc_disable_clients(struct radeon_device *rdev); |
43 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
47 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
44 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
48 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
45 | struct radeon_cs_packet *pkt, |
49 | struct radeon_cs_packet *pkt, |
46 | unsigned idx); |
50 | unsigned idx); |
47 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
51 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); |
48 | struct radeon_cs_reloc **cs_reloc); |
- | |
49 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
52 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
50 | struct radeon_cs_packet *pkt, |
53 | struct radeon_cs_packet *pkt, |
51 | const unsigned *auth, unsigned n, |
54 | const unsigned *auth, unsigned n, |
52 | radeon_packet0_check_t check); |
55 | radeon_packet0_check_t check); |
53 | void r100_cs_dump_packet(struct radeon_cs_parser *p, |
- | |
54 | struct radeon_cs_packet *pkt); |
- | |
55 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
56 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
56 | struct radeon_cs_packet *pkt, |
57 | struct radeon_cs_packet *pkt, |
57 | struct radeon_object *robj); |
58 | struct radeon_object *robj); |
58 | 59 | ||
59 | /* This files gather functions specifics to: |
60 | /* This files gather functions specifics to: |
60 | * r300,r350,rv350,rv370,rv380 |
61 | * r300,r350,rv350,rv370,rv380 |
61 | * |
62 | * |
62 | * Some of these functions might be used by newer ASICs. |
63 | * Some of these functions might be used by newer ASICs. |
63 | */ |
64 | */ |
64 | void r300_gpu_init(struct radeon_device *rdev); |
65 | void r300_gpu_init(struct radeon_device *rdev); |
65 | int r300_mc_wait_for_idle(struct radeon_device *rdev); |
66 | int r300_mc_wait_for_idle(struct radeon_device *rdev); |
66 | int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
67 | int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
67 | 68 | ||
68 | 69 | ||
69 | /* |
70 | /* |
70 | * rv370,rv380 PCIE GART |
71 | * rv370,rv380 PCIE GART |
71 | */ |
72 | */ |
72 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
73 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
73 | { |
74 | { |
74 | uint32_t tmp; |
75 | uint32_t tmp; |
75 | int i; |
76 | int i; |
76 | 77 | ||
77 | /* Workaround HW bug do flush 2 times */ |
78 | /* Workaround HW bug do flush 2 times */ |
78 | for (i = 0; i < 2; i++) { |
79 | for (i = 0; i < 2; i++) { |
79 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
80 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
80 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); |
81 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); |
81 | (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
82 | (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
82 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
83 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
- | 84 | } |
|
83 | mb(); |
85 | mb(); |
- | 86 | } |
|
- | 87 | ||
- | 88 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
|
- | 89 | { |
|
- | 90 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
|
- | 91 | ||
- | 92 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
|
- | 93 | return -EINVAL; |
|
84 | } |
94 | } |
- | 95 | addr = (lower_32_bits(addr) >> 8) | |
|
- | 96 | ((upper_32_bits(addr) & 0xff) << 24) | |
|
- | 97 | 0xc; |
|
- | 98 | /* on x86 we want this to be CPU endian, on powerpc |
|
- | 99 | * on powerpc without HW swappers, it'll get swapped on way |
|
- | 100 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
|
- | 101 | writel(addr, ((void __iomem *)ptr) + (i * 4)); |
|
- | 102 | return 0; |
|
85 | } |
103 | } |
86 | 104 | ||
87 | int rv370_pcie_gart_enable(struct radeon_device *rdev) |
105 | int rv370_pcie_gart_init(struct radeon_device *rdev) |
88 | { |
- | |
89 | uint32_t table_addr; |
- | |
90 | uint32_t tmp; |
106 | { |
- | 107 | int r; |
|
- | 108 | ||
- | 109 | if (rdev->gart.table.vram.robj) { |
|
- | 110 | WARN(1, "RV370 PCIE GART already initialized.\n"); |
|
91 | int r; |
111 | return 0; |
92 | 112 | } |
|
93 | /* Initialize common gart structure */ |
113 | /* Initialize common gart structure */ |
94 | r = radeon_gart_init(rdev); |
114 | r = radeon_gart_init(rdev); |
95 | if (r) { |
- | |
96 | return r; |
115 | if (r) |
97 | } |
116 | return r; |
98 | r = rv370_debugfs_pcie_gart_info_init(rdev); |
117 | r = rv370_debugfs_pcie_gart_info_init(rdev); |
99 | if (r) { |
- | |
100 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
118 | if (r) |
- | 119 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
|
- | 120 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
|
101 | } |
121 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
- | 122 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
|
- | 123 | return radeon_gart_table_vram_alloc(rdev); |
|
- | 124 | } |
|
- | 125 | ||
- | 126 | int rv370_pcie_gart_enable(struct radeon_device *rdev) |
|
- | 127 | { |
|
102 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
128 | uint32_t table_addr; |
- | 129 | uint32_t tmp; |
|
- | 130 | int r; |
|
- | 131 | ||
103 | r = radeon_gart_table_vram_alloc(rdev); |
132 | if (rdev->gart.table.vram.robj == NULL) { |
104 | if (r) { |
133 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
- | 134 | return -EINVAL; |
|
- | 135 | } |
|
- | 136 | r = radeon_gart_table_vram_pin(rdev); |
|
105 | return r; |
137 | if (r) |
106 | } |
138 | return r; |
107 | /* discard memory request outside of configured range */ |
139 | /* discard memory request outside of configured range */ |
108 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
140 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
109 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
141 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
110 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); |
142 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); |
111 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096; |
143 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096; |
112 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
144 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
113 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
145 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
114 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
146 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
115 | table_addr = rdev->gart.table_addr; |
147 | table_addr = rdev->gart.table_addr; |
116 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |
148 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |
117 | /* FIXME: setup default page */ |
149 | /* FIXME: setup default page */ |
118 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location); |
150 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location); |
119 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
151 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
120 | /* Clear error */ |
152 | /* Clear error */ |
121 | WREG32_PCIE(0x18, 0); |
153 | WREG32_PCIE(0x18, 0); |
122 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
154 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
123 | tmp |= RADEON_PCIE_TX_GART_EN; |
155 | tmp |= RADEON_PCIE_TX_GART_EN; |
124 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
156 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
125 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
157 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
126 | rv370_pcie_gart_tlb_flush(rdev); |
158 | rv370_pcie_gart_tlb_flush(rdev); |
127 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", |
159 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", |
128 | rdev->mc.gtt_size >> 20, table_addr); |
160 | (unsigned)(rdev->mc.gtt_size >> 20), table_addr); |
129 | rdev->gart.ready = true; |
161 | rdev->gart.ready = true; |
130 | return 0; |
162 | return 0; |
131 | } |
163 | } |
132 | 164 | ||
133 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
165 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
134 | { |
166 | { |
135 | uint32_t tmp; |
167 | uint32_t tmp; |
136 | 168 | ||
137 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
169 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
138 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
170 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
139 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
171 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
140 | if (rdev->gart.table.vram.robj) { |
172 | if (rdev->gart.table.vram.robj) { |
141 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
173 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
142 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
174 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
143 | } |
175 | } |
144 | } |
176 | } |
145 | - | ||
146 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
- | |
147 | { |
- | |
148 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
- | |
149 | - | ||
150 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
- | |
151 | return -EINVAL; |
- | |
152 | } |
- | |
153 | addr = (((u32)addr) >> 8) | ((upper_32_bits(addr) & 0xff) << 4) | 0xC; |
- | |
154 | writel(cpu_to_le32(addr), ((void __iomem *)ptr) + (i * 4)); |
- | |
155 | return 0; |
- | |
156 | } |
- | |
157 | 177 | ||
158 | int r300_gart_enable(struct radeon_device *rdev) |
178 | void rv370_pcie_gart_fini(struct radeon_device *rdev) |
159 | { |
- | |
160 | #if __OS_HAS_AGP |
- | |
161 | if (rdev->flags & RADEON_IS_AGP) { |
- | |
162 | if (rdev->family > CHIP_RV350) { |
179 | { |
163 | rv370_pcie_gart_disable(rdev); |
- | |
164 | } else { |
180 | rv370_pcie_gart_disable(rdev); |
165 | r100_pci_gart_disable(rdev); |
- | |
166 | } |
- | |
167 | return 0; |
- | |
168 | } |
- | |
169 | #endif |
- | |
170 | if (rdev->flags & RADEON_IS_PCIE) { |
- | |
171 | rdev->asic->gart_disable = &rv370_pcie_gart_disable; |
- | |
172 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
- | |
173 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
181 | radeon_gart_table_vram_free(rdev); |
174 | return rv370_pcie_gart_enable(rdev); |
- | |
175 | } |
- | |
176 | return r100_pci_gart_enable(rdev); |
182 | radeon_gart_fini(rdev); |
177 | } |
- | |
178 | 183 | } |
|
179 | 184 | ||
180 | /* |
185 | /* |
181 | * MC |
186 | * MC |
182 | */ |
187 | */ |
183 | int r300_mc_init(struct radeon_device *rdev) |
188 | int r300_mc_init(struct radeon_device *rdev) |
184 | { |
189 | { |
185 | int r; |
190 | int r; |
186 | 191 | ||
187 | if (r100_debugfs_rbbm_init(rdev)) { |
192 | if (r100_debugfs_rbbm_init(rdev)) { |
188 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
193 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
189 | } |
194 | } |
190 | 195 | ||
191 | r300_gpu_init(rdev); |
196 | r300_gpu_init(rdev); |
192 | r100_pci_gart_disable(rdev); |
197 | r100_pci_gart_disable(rdev); |
193 | if (rdev->flags & RADEON_IS_PCIE) { |
198 | if (rdev->flags & RADEON_IS_PCIE) { |
194 | rv370_pcie_gart_disable(rdev); |
199 | rv370_pcie_gart_disable(rdev); |
195 | } |
200 | } |
196 | 201 | ||
197 | /* Setup GPU memory space */ |
202 | /* Setup GPU memory space */ |
198 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
203 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
199 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
204 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
200 | if (rdev->flags & RADEON_IS_AGP) { |
- | |
201 | r = radeon_agp_init(rdev); |
- | |
202 | if (r) { |
- | |
203 | printk(KERN_WARNING "[drm] Disabling AGP\n"); |
- | |
204 | rdev->flags &= ~RADEON_IS_AGP; |
- | |
205 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
- | |
206 | } else { |
- | |
207 | rdev->mc.gtt_location = rdev->mc.agp_base; |
- | |
208 | } |
- | |
209 | } |
- | |
210 | r = radeon_mc_setup(rdev); |
205 | r = radeon_mc_setup(rdev); |
211 | if (r) { |
206 | if (r) { |
212 | return r; |
207 | return r; |
213 | } |
208 | } |
214 | 209 | ||
215 | /* Program GPU memory space */ |
210 | /* Program GPU memory space */ |
216 | r100_mc_disable_clients(rdev); |
211 | r100_mc_disable_clients(rdev); |
217 | if (r300_mc_wait_for_idle(rdev)) { |
212 | if (r300_mc_wait_for_idle(rdev)) { |
218 | printk(KERN_WARNING "Failed to wait MC idle while " |
213 | printk(KERN_WARNING "Failed to wait MC idle while " |
219 | "programming pipes. Bad things might happen.\n"); |
214 | "programming pipes. Bad things might happen.\n"); |
220 | } |
215 | } |
221 | r100_mc_setup(rdev); |
216 | r100_mc_setup(rdev); |
222 | return 0; |
217 | return 0; |
223 | } |
218 | } |
224 | 219 | ||
225 | void r300_mc_fini(struct radeon_device *rdev) |
220 | void r300_mc_fini(struct radeon_device *rdev) |
226 | { |
221 | { |
227 | if (rdev->flags & RADEON_IS_PCIE) { |
- | |
228 | rv370_pcie_gart_disable(rdev); |
- | |
229 | radeon_gart_table_vram_free(rdev); |
- | |
230 | } else { |
- | |
231 | r100_pci_gart_disable(rdev); |
- | |
232 | radeon_gart_table_ram_free(rdev); |
- | |
233 | } |
- | |
234 | radeon_gart_fini(rdev); |
- | |
235 | } |
222 | } |
236 | 223 | ||
237 | 224 | ||
238 | /* |
225 | /* |
239 | * Fence emission |
226 | * Fence emission |
240 | */ |
227 | */ |
241 | void r300_fence_ring_emit(struct radeon_device *rdev, |
228 | void r300_fence_ring_emit(struct radeon_device *rdev, |
242 | struct radeon_fence *fence) |
229 | struct radeon_fence *fence) |
243 | { |
230 | { |
244 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
231 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
245 | * for enough space (today caller are ib schedule and buffer move) */ |
232 | * for enough space (today caller are ib schedule and buffer move) */ |
246 | /* Write SC register so SC & US assert idle */ |
233 | /* Write SC register so SC & US assert idle */ |
247 | radeon_ring_write(rdev, PACKET0(0x43E0, 0)); |
234 | radeon_ring_write(rdev, PACKET0(0x43E0, 0)); |
248 | radeon_ring_write(rdev, 0); |
235 | radeon_ring_write(rdev, 0); |
249 | radeon_ring_write(rdev, PACKET0(0x43E4, 0)); |
236 | radeon_ring_write(rdev, PACKET0(0x43E4, 0)); |
250 | radeon_ring_write(rdev, 0); |
237 | radeon_ring_write(rdev, 0); |
251 | /* Flush 3D cache */ |
238 | /* Flush 3D cache */ |
252 | radeon_ring_write(rdev, PACKET0(0x4E4C, 0)); |
239 | radeon_ring_write(rdev, PACKET0(0x4E4C, 0)); |
253 | radeon_ring_write(rdev, (2 << 0)); |
240 | radeon_ring_write(rdev, (2 << 0)); |
254 | radeon_ring_write(rdev, PACKET0(0x4F18, 0)); |
241 | radeon_ring_write(rdev, PACKET0(0x4F18, 0)); |
255 | radeon_ring_write(rdev, (1 << 0)); |
242 | radeon_ring_write(rdev, (1 << 0)); |
256 | /* Wait until IDLE & CLEAN */ |
243 | /* Wait until IDLE & CLEAN */ |
257 | radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
244 | radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
258 | radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); |
245 | radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); |
259 | /* Emit fence sequence & fire IRQ */ |
246 | /* Emit fence sequence & fire IRQ */ |
260 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
247 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
261 | radeon_ring_write(rdev, fence->seq); |
248 | radeon_ring_write(rdev, fence->seq); |
262 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
249 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
263 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
250 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
264 | } |
251 | } |
265 | 252 | ||
266 | 253 | ||
267 | #if 0 |
254 | #if 0 |
268 | 255 | ||
269 | /* |
256 | /* |
270 | * Global GPU functions |
257 | * Global GPU functions |
271 | */ |
258 | */ |
272 | int r300_copy_dma(struct radeon_device *rdev, |
259 | int r300_copy_dma(struct radeon_device *rdev, |
273 | uint64_t src_offset, |
260 | uint64_t src_offset, |
274 | uint64_t dst_offset, |
261 | uint64_t dst_offset, |
275 | unsigned num_pages, |
262 | unsigned num_pages, |
276 | struct radeon_fence *fence) |
263 | struct radeon_fence *fence) |
277 | { |
264 | { |
278 | uint32_t size; |
265 | uint32_t size; |
279 | uint32_t cur_size; |
266 | uint32_t cur_size; |
280 | int i, num_loops; |
267 | int i, num_loops; |
281 | int r = 0; |
268 | int r = 0; |
282 | 269 | ||
283 | /* radeon pitch is /64 */ |
270 | /* radeon pitch is /64 */ |
284 | size = num_pages << PAGE_SHIFT; |
271 | size = num_pages << PAGE_SHIFT; |
285 | num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
272 | num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
286 | r = radeon_ring_lock(rdev, num_loops * 4 + 64); |
273 | r = radeon_ring_lock(rdev, num_loops * 4 + 64); |
287 | if (r) { |
274 | if (r) { |
288 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
275 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
289 | return r; |
276 | return r; |
290 | } |
277 | } |
291 | /* Must wait for 2D idle & clean before DMA or hangs might happen */ |
278 | /* Must wait for 2D idle & clean before DMA or hangs might happen */ |
292 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 )); |
279 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 )); |
293 | radeon_ring_write(rdev, (1 << 16)); |
280 | radeon_ring_write(rdev, (1 << 16)); |
294 | for (i = 0; i < num_loops; i++) { |
281 | for (i = 0; i < num_loops; i++) { |
295 | cur_size = size; |
282 | cur_size = size; |
296 | if (cur_size > 0x1FFFFF) { |
283 | if (cur_size > 0x1FFFFF) { |
297 | cur_size = 0x1FFFFF; |
284 | cur_size = 0x1FFFFF; |
298 | } |
285 | } |
299 | size -= cur_size; |
286 | size -= cur_size; |
300 | radeon_ring_write(rdev, PACKET0(0x720, 2)); |
287 | radeon_ring_write(rdev, PACKET0(0x720, 2)); |
301 | radeon_ring_write(rdev, src_offset); |
288 | radeon_ring_write(rdev, src_offset); |
302 | radeon_ring_write(rdev, dst_offset); |
289 | radeon_ring_write(rdev, dst_offset); |
303 | radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); |
290 | radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); |
304 | src_offset += cur_size; |
291 | src_offset += cur_size; |
305 | dst_offset += cur_size; |
292 | dst_offset += cur_size; |
306 | } |
293 | } |
307 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
294 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
308 | radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); |
295 | radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); |
309 | if (fence) { |
296 | if (fence) { |
310 | r = radeon_fence_emit(rdev, fence); |
297 | r = radeon_fence_emit(rdev, fence); |
311 | } |
298 | } |
312 | radeon_ring_unlock_commit(rdev); |
299 | radeon_ring_unlock_commit(rdev); |
313 | return r; |
300 | return r; |
314 | } |
301 | } |
315 | 302 | ||
316 | #endif |
303 | #endif |
317 | 304 | ||
318 | void r300_ring_start(struct radeon_device *rdev) |
305 | void r300_ring_start(struct radeon_device *rdev) |
319 | { |
306 | { |
320 | unsigned gb_tile_config; |
307 | unsigned gb_tile_config; |
321 | int r; |
308 | int r; |
322 | 309 | ||
323 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
310 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
324 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
311 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
325 | switch(rdev->num_gb_pipes) { |
312 | switch(rdev->num_gb_pipes) { |
326 | case 2: |
313 | case 2: |
327 | gb_tile_config |= R300_PIPE_COUNT_R300; |
314 | gb_tile_config |= R300_PIPE_COUNT_R300; |
328 | break; |
315 | break; |
329 | case 3: |
316 | case 3: |
330 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
317 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
331 | break; |
318 | break; |
332 | case 4: |
319 | case 4: |
333 | gb_tile_config |= R300_PIPE_COUNT_R420; |
320 | gb_tile_config |= R300_PIPE_COUNT_R420; |
334 | break; |
321 | break; |
335 | case 1: |
322 | case 1: |
336 | default: |
323 | default: |
337 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
324 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
338 | break; |
325 | break; |
339 | } |
326 | } |
340 | 327 | ||
341 | r = radeon_ring_lock(rdev, 64); |
328 | r = radeon_ring_lock(rdev, 64); |
342 | if (r) { |
329 | if (r) { |
343 | return; |
330 | return; |
344 | } |
331 | } |
345 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
332 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
346 | radeon_ring_write(rdev, |
333 | radeon_ring_write(rdev, |
347 | RADEON_ISYNC_ANY2D_IDLE3D | |
334 | RADEON_ISYNC_ANY2D_IDLE3D | |
348 | RADEON_ISYNC_ANY3D_IDLE2D | |
335 | RADEON_ISYNC_ANY3D_IDLE2D | |
349 | RADEON_ISYNC_WAIT_IDLEGUI | |
336 | RADEON_ISYNC_WAIT_IDLEGUI | |
350 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
337 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
351 | radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); |
338 | radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); |
352 | radeon_ring_write(rdev, gb_tile_config); |
339 | radeon_ring_write(rdev, gb_tile_config); |
353 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
340 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
354 | radeon_ring_write(rdev, |
341 | radeon_ring_write(rdev, |
355 | RADEON_WAIT_2D_IDLECLEAN | |
342 | RADEON_WAIT_2D_IDLECLEAN | |
356 | RADEON_WAIT_3D_IDLECLEAN); |
343 | RADEON_WAIT_3D_IDLECLEAN); |
357 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
344 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
358 | radeon_ring_write(rdev, 1 << 31); |
345 | radeon_ring_write(rdev, 1 << 31); |
359 | radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); |
346 | radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); |
360 | radeon_ring_write(rdev, 0); |
347 | radeon_ring_write(rdev, 0); |
361 | radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); |
348 | radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); |
362 | radeon_ring_write(rdev, 0); |
349 | radeon_ring_write(rdev, 0); |
363 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
350 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
364 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
351 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
365 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
352 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
366 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
353 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
367 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
354 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
368 | radeon_ring_write(rdev, |
355 | radeon_ring_write(rdev, |
369 | RADEON_WAIT_2D_IDLECLEAN | |
356 | RADEON_WAIT_2D_IDLECLEAN | |
370 | RADEON_WAIT_3D_IDLECLEAN); |
357 | RADEON_WAIT_3D_IDLECLEAN); |
371 | radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); |
358 | radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); |
372 | radeon_ring_write(rdev, 0); |
359 | radeon_ring_write(rdev, 0); |
373 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
360 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
374 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
361 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
375 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
362 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
376 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
363 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
377 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); |
364 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); |
378 | radeon_ring_write(rdev, |
365 | radeon_ring_write(rdev, |
379 | ((6 << R300_MS_X0_SHIFT) | |
366 | ((6 << R300_MS_X0_SHIFT) | |
380 | (6 << R300_MS_Y0_SHIFT) | |
367 | (6 << R300_MS_Y0_SHIFT) | |
381 | (6 << R300_MS_X1_SHIFT) | |
368 | (6 << R300_MS_X1_SHIFT) | |
382 | (6 << R300_MS_Y1_SHIFT) | |
369 | (6 << R300_MS_Y1_SHIFT) | |
383 | (6 << R300_MS_X2_SHIFT) | |
370 | (6 << R300_MS_X2_SHIFT) | |
384 | (6 << R300_MS_Y2_SHIFT) | |
371 | (6 << R300_MS_Y2_SHIFT) | |
385 | (6 << R300_MSBD0_Y_SHIFT) | |
372 | (6 << R300_MSBD0_Y_SHIFT) | |
386 | (6 << R300_MSBD0_X_SHIFT))); |
373 | (6 << R300_MSBD0_X_SHIFT))); |
387 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); |
374 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); |
388 | radeon_ring_write(rdev, |
375 | radeon_ring_write(rdev, |
389 | ((6 << R300_MS_X3_SHIFT) | |
376 | ((6 << R300_MS_X3_SHIFT) | |
390 | (6 << R300_MS_Y3_SHIFT) | |
377 | (6 << R300_MS_Y3_SHIFT) | |
391 | (6 << R300_MS_X4_SHIFT) | |
378 | (6 << R300_MS_X4_SHIFT) | |
392 | (6 << R300_MS_Y4_SHIFT) | |
379 | (6 << R300_MS_Y4_SHIFT) | |
393 | (6 << R300_MS_X5_SHIFT) | |
380 | (6 << R300_MS_X5_SHIFT) | |
394 | (6 << R300_MS_Y5_SHIFT) | |
381 | (6 << R300_MS_Y5_SHIFT) | |
395 | (6 << R300_MSBD1_SHIFT))); |
382 | (6 << R300_MSBD1_SHIFT))); |
396 | radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); |
383 | radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); |
397 | radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
384 | radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
398 | radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); |
385 | radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); |
399 | radeon_ring_write(rdev, |
386 | radeon_ring_write(rdev, |
400 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
387 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
401 | radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); |
388 | radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); |
402 | radeon_ring_write(rdev, |
389 | radeon_ring_write(rdev, |
403 | R300_GEOMETRY_ROUND_NEAREST | |
390 | R300_GEOMETRY_ROUND_NEAREST | |
404 | R300_COLOR_ROUND_NEAREST); |
391 | R300_COLOR_ROUND_NEAREST); |
405 | radeon_ring_unlock_commit(rdev); |
392 | radeon_ring_unlock_commit(rdev); |
406 | } |
393 | } |
407 | 394 | ||
408 | void r300_errata(struct radeon_device *rdev) |
395 | void r300_errata(struct radeon_device *rdev) |
409 | { |
396 | { |
410 | rdev->pll_errata = 0; |
397 | rdev->pll_errata = 0; |
411 | 398 | ||
412 | if (rdev->family == CHIP_R300 && |
399 | if (rdev->family == CHIP_R300 && |
413 | (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { |
400 | (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { |
414 | rdev->pll_errata |= CHIP_ERRATA_R300_CG; |
401 | rdev->pll_errata |= CHIP_ERRATA_R300_CG; |
415 | } |
402 | } |
416 | } |
403 | } |
417 | 404 | ||
418 | int r300_mc_wait_for_idle(struct radeon_device *rdev) |
405 | int r300_mc_wait_for_idle(struct radeon_device *rdev) |
419 | { |
406 | { |
420 | unsigned i; |
407 | unsigned i; |
421 | uint32_t tmp; |
408 | uint32_t tmp; |
422 | 409 | ||
423 | for (i = 0; i < rdev->usec_timeout; i++) { |
410 | for (i = 0; i < rdev->usec_timeout; i++) { |
424 | /* read MC_STATUS */ |
411 | /* read MC_STATUS */ |
425 | tmp = RREG32(0x0150); |
412 | tmp = RREG32(0x0150); |
426 | if (tmp & (1 << 4)) { |
413 | if (tmp & (1 << 4)) { |
427 | return 0; |
414 | return 0; |
428 | } |
415 | } |
429 | DRM_UDELAY(1); |
416 | DRM_UDELAY(1); |
430 | } |
417 | } |
431 | return -1; |
418 | return -1; |
432 | } |
419 | } |
433 | 420 | ||
434 | void r300_gpu_init(struct radeon_device *rdev) |
421 | void r300_gpu_init(struct radeon_device *rdev) |
435 | { |
422 | { |
436 | uint32_t gb_tile_config, tmp; |
423 | uint32_t gb_tile_config, tmp; |
437 | 424 | ||
438 | r100_hdp_reset(rdev); |
425 | r100_hdp_reset(rdev); |
439 | /* FIXME: rv380 one pipes ? */ |
426 | /* FIXME: rv380 one pipes ? */ |
440 | if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { |
427 | if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { |
441 | /* r300,r350 */ |
428 | /* r300,r350 */ |
442 | rdev->num_gb_pipes = 2; |
429 | rdev->num_gb_pipes = 2; |
443 | } else { |
430 | } else { |
444 | /* rv350,rv370,rv380 */ |
431 | /* rv350,rv370,rv380 */ |
445 | rdev->num_gb_pipes = 1; |
432 | rdev->num_gb_pipes = 1; |
446 | } |
433 | } |
- | 434 | rdev->num_z_pipes = 1; |
|
447 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
435 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
448 | switch (rdev->num_gb_pipes) { |
436 | switch (rdev->num_gb_pipes) { |
449 | case 2: |
437 | case 2: |
450 | gb_tile_config |= R300_PIPE_COUNT_R300; |
438 | gb_tile_config |= R300_PIPE_COUNT_R300; |
451 | break; |
439 | break; |
452 | case 3: |
440 | case 3: |
453 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
441 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
454 | break; |
442 | break; |
455 | case 4: |
443 | case 4: |
456 | gb_tile_config |= R300_PIPE_COUNT_R420; |
444 | gb_tile_config |= R300_PIPE_COUNT_R420; |
457 | break; |
445 | break; |
458 | default: |
446 | default: |
459 | case 1: |
447 | case 1: |
460 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
448 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
461 | break; |
449 | break; |
462 | } |
450 | } |
463 | WREG32(R300_GB_TILE_CONFIG, gb_tile_config); |
451 | WREG32(R300_GB_TILE_CONFIG, gb_tile_config); |
464 | 452 | ||
465 | if (r100_gui_wait_for_idle(rdev)) { |
453 | if (r100_gui_wait_for_idle(rdev)) { |
466 | printk(KERN_WARNING "Failed to wait GUI idle while " |
454 | printk(KERN_WARNING "Failed to wait GUI idle while " |
467 | "programming pipes. Bad things might happen.\n"); |
455 | "programming pipes. Bad things might happen.\n"); |
468 | } |
456 | } |
469 | 457 | ||
470 | tmp = RREG32(0x170C); |
458 | tmp = RREG32(0x170C); |
471 | WREG32(0x170C, tmp | (1 << 31)); |
459 | WREG32(0x170C, tmp | (1 << 31)); |
472 | 460 | ||
473 | WREG32(R300_RB2D_DSTCACHE_MODE, |
461 | WREG32(R300_RB2D_DSTCACHE_MODE, |
474 | R300_DC_AUTOFLUSH_ENABLE | |
462 | R300_DC_AUTOFLUSH_ENABLE | |
475 | R300_DC_DC_DISABLE_IGNORE_PE); |
463 | R300_DC_DC_DISABLE_IGNORE_PE); |
476 | 464 | ||
477 | if (r100_gui_wait_for_idle(rdev)) { |
465 | if (r100_gui_wait_for_idle(rdev)) { |
478 | printk(KERN_WARNING "Failed to wait GUI idle while " |
466 | printk(KERN_WARNING "Failed to wait GUI idle while " |
479 | "programming pipes. Bad things might happen.\n"); |
467 | "programming pipes. Bad things might happen.\n"); |
480 | } |
468 | } |
481 | if (r300_mc_wait_for_idle(rdev)) { |
469 | if (r300_mc_wait_for_idle(rdev)) { |
482 | printk(KERN_WARNING "Failed to wait MC idle while " |
470 | printk(KERN_WARNING "Failed to wait MC idle while " |
483 | "programming pipes. Bad things might happen.\n"); |
471 | "programming pipes. Bad things might happen.\n"); |
484 | } |
472 | } |
485 | DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes); |
473 | DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", |
- | 474 | rdev->num_gb_pipes, rdev->num_z_pipes); |
|
486 | } |
475 | } |
487 | 476 | ||
488 | int r300_ga_reset(struct radeon_device *rdev) |
477 | int r300_ga_reset(struct radeon_device *rdev) |
489 | { |
478 | { |
490 | uint32_t tmp; |
479 | uint32_t tmp; |
491 | bool reinit_cp; |
480 | bool reinit_cp; |
492 | int i; |
481 | int i; |
493 | 482 | ||
494 | reinit_cp = rdev->cp.ready; |
483 | reinit_cp = rdev->cp.ready; |
495 | rdev->cp.ready = false; |
484 | rdev->cp.ready = false; |
496 | for (i = 0; i < rdev->usec_timeout; i++) { |
485 | for (i = 0; i < rdev->usec_timeout; i++) { |
497 | WREG32(RADEON_CP_CSQ_MODE, 0); |
486 | WREG32(RADEON_CP_CSQ_MODE, 0); |
498 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
487 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
499 | WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); |
488 | WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); |
500 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
489 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
501 | udelay(200); |
490 | udelay(200); |
502 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
491 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
503 | /* Wait to prevent race in RBBM_STATUS */ |
492 | /* Wait to prevent race in RBBM_STATUS */ |
504 | mdelay(1); |
493 | mdelay(1); |
505 | tmp = RREG32(RADEON_RBBM_STATUS); |
494 | tmp = RREG32(RADEON_RBBM_STATUS); |
506 | if (tmp & ((1 << 20) | (1 << 26))) { |
495 | if (tmp & ((1 << 20) | (1 << 26))) { |
507 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp); |
496 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp); |
508 | /* GA still busy soft reset it */ |
497 | /* GA still busy soft reset it */ |
509 | WREG32(0x429C, 0x200); |
498 | WREG32(0x429C, 0x200); |
510 | WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
499 | WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
511 | WREG32(0x43E0, 0); |
500 | WREG32(0x43E0, 0); |
512 | WREG32(0x43E4, 0); |
501 | WREG32(0x43E4, 0); |
513 | WREG32(0x24AC, 0); |
502 | WREG32(0x24AC, 0); |
514 | } |
503 | } |
515 | /* Wait to prevent race in RBBM_STATUS */ |
504 | /* Wait to prevent race in RBBM_STATUS */ |
516 | mdelay(1); |
505 | mdelay(1); |
517 | tmp = RREG32(RADEON_RBBM_STATUS); |
506 | tmp = RREG32(RADEON_RBBM_STATUS); |
518 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
507 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
519 | break; |
508 | break; |
520 | } |
509 | } |
521 | } |
510 | } |
522 | for (i = 0; i < rdev->usec_timeout; i++) { |
511 | for (i = 0; i < rdev->usec_timeout; i++) { |
523 | tmp = RREG32(RADEON_RBBM_STATUS); |
512 | tmp = RREG32(RADEON_RBBM_STATUS); |
524 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
513 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
525 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
514 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
526 | tmp); |
515 | tmp); |
527 | if (reinit_cp) { |
516 | if (reinit_cp) { |
528 | return r100_cp_init(rdev, rdev->cp.ring_size); |
517 | return r100_cp_init(rdev, rdev->cp.ring_size); |
529 | } |
518 | } |
530 | return 0; |
519 | return 0; |
531 | } |
520 | } |
532 | DRM_UDELAY(1); |
521 | DRM_UDELAY(1); |
533 | } |
522 | } |
534 | tmp = RREG32(RADEON_RBBM_STATUS); |
523 | tmp = RREG32(RADEON_RBBM_STATUS); |
535 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
524 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
536 | return -1; |
525 | return -1; |
537 | } |
526 | } |
538 | 527 | ||
539 | int r300_gpu_reset(struct radeon_device *rdev) |
528 | int r300_gpu_reset(struct radeon_device *rdev) |
540 | { |
529 | { |
541 | uint32_t status; |
530 | uint32_t status; |
542 | 531 | ||
543 | /* reset order likely matter */ |
532 | /* reset order likely matter */ |
544 | status = RREG32(RADEON_RBBM_STATUS); |
533 | status = RREG32(RADEON_RBBM_STATUS); |
545 | /* reset HDP */ |
534 | /* reset HDP */ |
546 | r100_hdp_reset(rdev); |
535 | r100_hdp_reset(rdev); |
547 | /* reset rb2d */ |
536 | /* reset rb2d */ |
548 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
537 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
549 | r100_rb2d_reset(rdev); |
538 | r100_rb2d_reset(rdev); |
550 | } |
539 | } |
551 | /* reset GA */ |
540 | /* reset GA */ |
552 | if (status & ((1 << 20) | (1 << 26))) { |
541 | if (status & ((1 << 20) | (1 << 26))) { |
553 | r300_ga_reset(rdev); |
542 | r300_ga_reset(rdev); |
554 | } |
543 | } |
555 | /* reset CP */ |
544 | /* reset CP */ |
556 | status = RREG32(RADEON_RBBM_STATUS); |
545 | status = RREG32(RADEON_RBBM_STATUS); |
557 | if (status & (1 << 16)) { |
546 | if (status & (1 << 16)) { |
558 | r100_cp_reset(rdev); |
547 | r100_cp_reset(rdev); |
559 | } |
548 | } |
560 | /* Check if GPU is idle */ |
549 | /* Check if GPU is idle */ |
561 | status = RREG32(RADEON_RBBM_STATUS); |
550 | status = RREG32(RADEON_RBBM_STATUS); |
562 | if (status & (1 << 31)) { |
551 | if (status & (1 << 31)) { |
563 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
552 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
564 | return -1; |
553 | return -1; |
565 | } |
554 | } |
566 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
555 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
567 | return 0; |
556 | return 0; |
568 | } |
557 | } |
569 | 558 | ||
570 | 559 | ||
571 | /* |
560 | /* |
572 | * r300,r350,rv350,rv380 VRAM info |
561 | * r300,r350,rv350,rv380 VRAM info |
573 | */ |
562 | */ |
574 | void r300_vram_info(struct radeon_device *rdev) |
563 | void r300_vram_info(struct radeon_device *rdev) |
575 | { |
564 | { |
576 | uint32_t tmp; |
565 | uint32_t tmp; |
577 | 566 | ||
578 | /* DDR for all card after R300 & IGP */ |
567 | /* DDR for all card after R300 & IGP */ |
579 | rdev->mc.vram_is_ddr = true; |
568 | rdev->mc.vram_is_ddr = true; |
580 | tmp = RREG32(RADEON_MEM_CNTL); |
569 | tmp = RREG32(RADEON_MEM_CNTL); |
581 | if (tmp & R300_MEM_NUM_CHANNELS_MASK) { |
570 | if (tmp & R300_MEM_NUM_CHANNELS_MASK) { |
582 | rdev->mc.vram_width = 128; |
571 | rdev->mc.vram_width = 128; |
583 | } else { |
572 | } else { |
584 | rdev->mc.vram_width = 64; |
573 | rdev->mc.vram_width = 64; |
585 | } |
574 | } |
586 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
- | |
587 | - | ||
588 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
575 | |
589 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
576 | r100_vram_init_sizes(rdev); |
590 | } |
577 | } |
591 | 578 | ||
592 | 579 | ||
593 | /* |
580 | /* |
594 | * Indirect registers accessor |
- | |
595 | */ |
- | |
596 | uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
- | |
597 | { |
- | |
598 | uint32_t r; |
- | |
599 | - | ||
600 | WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff)); |
- | |
601 | (void)RREG32(RADEON_PCIE_INDEX); |
- | |
602 | r = RREG32(RADEON_PCIE_DATA); |
- | |
603 | return r; |
- | |
604 | } |
- | |
605 | - | ||
606 | void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
- | |
607 | { |
- | |
608 | WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff)); |
- | |
609 | (void)RREG32(RADEON_PCIE_INDEX); |
- | |
610 | WREG32(RADEON_PCIE_DATA, (v)); |
- | |
611 | (void)RREG32(RADEON_PCIE_DATA); |
- | |
612 | } |
- | |
613 | - | ||
614 | /* |
- | |
615 | * PCIE Lanes |
581 | * PCIE Lanes |
616 | */ |
582 | */ |
617 | 583 | ||
618 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
584 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
619 | { |
585 | { |
620 | uint32_t link_width_cntl, mask; |
586 | uint32_t link_width_cntl, mask; |
621 | 587 | ||
622 | if (rdev->flags & RADEON_IS_IGP) |
588 | if (rdev->flags & RADEON_IS_IGP) |
623 | return; |
589 | return; |
624 | 590 | ||
625 | if (!(rdev->flags & RADEON_IS_PCIE)) |
591 | if (!(rdev->flags & RADEON_IS_PCIE)) |
626 | return; |
592 | return; |
627 | 593 | ||
628 | /* FIXME wait for idle */ |
594 | /* FIXME wait for idle */ |
629 | 595 | ||
630 | switch (lanes) { |
596 | switch (lanes) { |
631 | case 0: |
597 | case 0: |
632 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; |
598 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; |
633 | break; |
599 | break; |
634 | case 1: |
600 | case 1: |
635 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; |
601 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; |
636 | break; |
602 | break; |
637 | case 2: |
603 | case 2: |
638 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; |
604 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; |
639 | break; |
605 | break; |
640 | case 4: |
606 | case 4: |
641 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; |
607 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; |
642 | break; |
608 | break; |
643 | case 8: |
609 | case 8: |
644 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; |
610 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; |
645 | break; |
611 | break; |
646 | case 12: |
612 | case 12: |
647 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
613 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
648 | break; |
614 | break; |
649 | case 16: |
615 | case 16: |
650 | default: |
616 | default: |
651 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
617 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
652 | break; |
618 | break; |
653 | } |
619 | } |
654 | 620 | ||
655 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
621 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
656 | 622 | ||
657 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == |
623 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == |
658 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) |
624 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) |
659 | return; |
625 | return; |
660 | 626 | ||
661 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | |
627 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | |
662 | RADEON_PCIE_LC_RECONFIG_NOW | |
628 | RADEON_PCIE_LC_RECONFIG_NOW | |
663 | RADEON_PCIE_LC_RECONFIG_LATER | |
629 | RADEON_PCIE_LC_RECONFIG_LATER | |
664 | RADEON_PCIE_LC_SHORT_RECONFIG_EN); |
630 | RADEON_PCIE_LC_SHORT_RECONFIG_EN); |
665 | link_width_cntl |= mask; |
631 | link_width_cntl |= mask; |
666 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
632 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
667 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | |
633 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | |
668 | RADEON_PCIE_LC_RECONFIG_NOW)); |
634 | RADEON_PCIE_LC_RECONFIG_NOW)); |
669 | 635 | ||
670 | /* wait for lane set to complete */ |
636 | /* wait for lane set to complete */ |
671 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
637 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
672 | while (link_width_cntl == 0xffffffff) |
638 | while (link_width_cntl == 0xffffffff) |
673 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
639 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
674 | 640 | ||
675 | } |
641 | } |
676 | 642 | ||
677 | 643 | ||
678 | /* |
644 | /* |
679 | * Debugfs info |
645 | * Debugfs info |
680 | */ |
646 | */ |
681 | #if defined(CONFIG_DEBUG_FS) |
647 | #if defined(CONFIG_DEBUG_FS) |
682 | static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) |
648 | static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) |
683 | { |
649 | { |
684 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
650 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
685 | struct drm_device *dev = node->minor->dev; |
651 | struct drm_device *dev = node->minor->dev; |
686 | struct radeon_device *rdev = dev->dev_private; |
652 | struct radeon_device *rdev = dev->dev_private; |
687 | uint32_t tmp; |
653 | uint32_t tmp; |
688 | 654 | ||
689 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
655 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
690 | seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); |
656 | seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); |
691 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); |
657 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); |
692 | seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); |
658 | seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); |
693 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); |
659 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); |
694 | seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); |
660 | seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); |
695 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); |
661 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); |
696 | seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); |
662 | seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); |
697 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); |
663 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); |
698 | seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); |
664 | seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); |
699 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); |
665 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); |
700 | seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); |
666 | seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); |
701 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); |
667 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); |
702 | seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); |
668 | seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); |
703 | return 0; |
669 | return 0; |
704 | } |
670 | } |
705 | 671 | ||
706 | static struct drm_info_list rv370_pcie_gart_info_list[] = { |
672 | static struct drm_info_list rv370_pcie_gart_info_list[] = { |
707 | {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, |
673 | {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, |
708 | }; |
674 | }; |
709 | #endif |
675 | #endif |
710 | 676 | ||
711 | int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
677 | int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
712 | { |
678 | { |
713 | #if defined(CONFIG_DEBUG_FS) |
679 | #if defined(CONFIG_DEBUG_FS) |
714 | return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); |
680 | return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); |
715 | #else |
681 | #else |
716 | return 0; |
682 | return 0; |
717 | #endif |
683 | #endif |
718 | } |
684 | } |
719 | 685 | ||
720 | 686 | ||
721 | #if 0 |
687 | #if 0 |
722 | /* |
688 | /* |
723 | * CS functions |
689 | * CS functions |
724 | */ |
690 | */ |
725 | struct r300_cs_track_cb { |
- | |
726 | struct radeon_object *robj; |
- | |
727 | unsigned pitch; |
- | |
728 | unsigned cpp; |
- | |
729 | unsigned offset; |
- | |
730 | }; |
- | |
731 | - | ||
732 | struct r300_cs_track_array { |
- | |
733 | struct radeon_object *robj; |
- | |
734 | unsigned esize; |
- | |
735 | }; |
- | |
736 | - | ||
737 | struct r300_cs_track_texture { |
- | |
738 | struct radeon_object *robj; |
- | |
739 | unsigned pitch; |
- | |
740 | unsigned width; |
- | |
741 | unsigned height; |
- | |
742 | unsigned num_levels; |
- | |
743 | unsigned cpp; |
- | |
744 | unsigned tex_coord_type; |
- | |
745 | unsigned txdepth; |
- | |
746 | unsigned width_11; |
- | |
747 | unsigned height_11; |
- | |
748 | bool use_pitch; |
- | |
749 | bool enabled; |
- | |
750 | bool roundup_w; |
- | |
751 | bool roundup_h; |
- | |
752 | }; |
- | |
753 | - | ||
754 | struct r300_cs_track { |
- | |
755 | unsigned num_cb; |
- | |
756 | unsigned maxy; |
- | |
757 | unsigned vtx_size; |
- | |
758 | unsigned vap_vf_cntl; |
- | |
759 | unsigned immd_dwords; |
- | |
760 | unsigned num_arrays; |
- | |
761 | unsigned max_indx; |
- | |
762 | struct r300_cs_track_array arrays[11]; |
- | |
763 | struct r300_cs_track_cb cb[4]; |
- | |
764 | struct r300_cs_track_cb zb; |
- | |
765 | struct r300_cs_track_texture textures[16]; |
- | |
766 | bool z_enabled; |
- | |
767 | }; |
- | |
768 | - | ||
769 | static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t) |
- | |
770 | { |
- | |
771 | DRM_ERROR("pitch %d\n", t->pitch); |
- | |
772 | DRM_ERROR("width %d\n", t->width); |
- | |
773 | DRM_ERROR("height %d\n", t->height); |
- | |
774 | DRM_ERROR("num levels %d\n", t->num_levels); |
- | |
775 | DRM_ERROR("depth %d\n", t->txdepth); |
- | |
776 | DRM_ERROR("bpp %d\n", t->cpp); |
- | |
777 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); |
- | |
778 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); |
- | |
779 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); |
- | |
780 | } |
- | |
781 | - | ||
782 | static inline int r300_cs_track_texture_check(struct radeon_device *rdev, |
- | |
783 | struct r300_cs_track *track) |
- | |
784 | { |
- | |
785 | struct radeon_object *robj; |
- | |
786 | unsigned long size; |
- | |
787 | unsigned u, i, w, h; |
- | |
788 | - | ||
789 | for (u = 0; u < 16; u++) { |
- | |
790 | if (!track->textures[u].enabled) |
- | |
791 | continue; |
- | |
792 | robj = track->textures[u].robj; |
- | |
793 | if (robj == NULL) { |
- | |
794 | DRM_ERROR("No texture bound to unit %u\n", u); |
- | |
795 | return -EINVAL; |
- | |
796 | } |
- | |
797 | size = 0; |
- | |
798 | for (i = 0; i <= track->textures[u].num_levels; i++) { |
- | |
799 | if (track->textures[u].use_pitch) { |
- | |
800 | w = track->textures[u].pitch / (1 << i); |
- | |
801 | } else { |
- | |
802 | w = track->textures[u].width / (1 << i); |
- | |
803 | if (rdev->family >= CHIP_RV515) |
- | |
804 | w |= track->textures[u].width_11; |
- | |
805 | if (track->textures[u].roundup_w) |
- | |
806 | w = roundup_pow_of_two(w); |
- | |
807 | } |
- | |
808 | h = track->textures[u].height / (1 << i); |
- | |
809 | if (rdev->family >= CHIP_RV515) |
- | |
810 | h |= track->textures[u].height_11; |
- | |
811 | if (track->textures[u].roundup_h) |
- | |
812 | h = roundup_pow_of_two(h); |
- | |
813 | size += w * h; |
- | |
814 | } |
- | |
815 | size *= track->textures[u].cpp; |
- | |
816 | switch (track->textures[u].tex_coord_type) { |
- | |
817 | case 0: |
- | |
818 | break; |
- | |
819 | case 1: |
- | |
820 | size *= (1 << track->textures[u].txdepth); |
- | |
821 | break; |
- | |
822 | case 2: |
- | |
823 | size *= 6; |
- | |
824 | break; |
- | |
825 | default: |
- | |
826 | DRM_ERROR("Invalid texture coordinate type %u for unit " |
- | |
827 | "%u\n", track->textures[u].tex_coord_type, u); |
- | |
828 | return -EINVAL; |
- | |
829 | } |
- | |
830 | if (size > radeon_object_size(robj)) { |
- | |
831 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " |
- | |
832 | "%lu\n", u, size, radeon_object_size(robj)); |
- | |
833 | r300_cs_track_texture_print(&track->textures[u]); |
- | |
834 | return -EINVAL; |
- | |
835 | } |
- | |
836 | } |
- | |
837 | return 0; |
- | |
838 | } |
- | |
839 | - | ||
840 | int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track) |
- | |
841 | { |
- | |
842 | unsigned i; |
- | |
843 | unsigned long size; |
- | |
844 | unsigned prim_walk; |
- | |
845 | unsigned nverts; |
- | |
846 | - | ||
847 | for (i = 0; i < track->num_cb; i++) { |
- | |
848 | if (track->cb[i].robj == NULL) { |
- | |
849 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); |
- | |
850 | return -EINVAL; |
- | |
851 | } |
- | |
852 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; |
- | |
853 | size += track->cb[i].offset; |
- | |
854 | if (size > radeon_object_size(track->cb[i].robj)) { |
- | |
855 | DRM_ERROR("[drm] Buffer too small for color buffer %d " |
- | |
856 | "(need %lu have %lu) !\n", i, size, |
- | |
857 | radeon_object_size(track->cb[i].robj)); |
- | |
858 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", |
- | |
859 | i, track->cb[i].pitch, track->cb[i].cpp, |
- | |
860 | track->cb[i].offset, track->maxy); |
- | |
861 | return -EINVAL; |
- | |
862 | } |
- | |
863 | } |
- | |
864 | if (track->z_enabled) { |
- | |
865 | if (track->zb.robj == NULL) { |
- | |
866 | DRM_ERROR("[drm] No buffer for z buffer !\n"); |
- | |
867 | return -EINVAL; |
- | |
868 | } |
- | |
869 | size = track->zb.pitch * track->zb.cpp * track->maxy; |
- | |
870 | size += track->zb.offset; |
- | |
871 | if (size > radeon_object_size(track->zb.robj)) { |
- | |
872 | DRM_ERROR("[drm] Buffer too small for z buffer " |
- | |
873 | "(need %lu have %lu) !\n", size, |
- | |
874 | radeon_object_size(track->zb.robj)); |
- | |
875 | return -EINVAL; |
- | |
876 | } |
- | |
877 | } |
- | |
878 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; |
- | |
879 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; |
- | |
880 | switch (prim_walk) { |
- | |
881 | case 1: |
- | |
882 | for (i = 0; i < track->num_arrays; i++) { |
- | |
883 | size = track->arrays[i].esize * track->max_indx * 4; |
- | |
884 | if (track->arrays[i].robj == NULL) { |
- | |
885 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
- | |
886 | "bound\n", prim_walk, i); |
- | |
887 | return -EINVAL; |
- | |
888 | } |
- | |
889 | if (size > radeon_object_size(track->arrays[i].robj)) { |
- | |
890 | DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " |
- | |
891 | "have %lu dwords\n", prim_walk, i, |
- | |
892 | size >> 2, |
- | |
893 | radeon_object_size(track->arrays[i].robj) >> 2); |
- | |
894 | DRM_ERROR("Max indices %u\n", track->max_indx); |
- | |
895 | return -EINVAL; |
- | |
896 | } |
- | |
897 | } |
- | |
898 | break; |
- | |
899 | case 2: |
- | |
900 | for (i = 0; i < track->num_arrays; i++) { |
- | |
901 | size = track->arrays[i].esize * (nverts - 1) * 4; |
- | |
902 | if (track->arrays[i].robj == NULL) { |
- | |
903 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
- | |
904 | "bound\n", prim_walk, i); |
- | |
905 | return -EINVAL; |
- | |
906 | } |
- | |
907 | if (size > radeon_object_size(track->arrays[i].robj)) { |
- | |
908 | DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " |
- | |
909 | "have %lu dwords\n", prim_walk, i, size >> 2, |
- | |
910 | radeon_object_size(track->arrays[i].robj) >> 2); |
- | |
911 | return -EINVAL; |
- | |
912 | } |
- | |
913 | } |
- | |
914 | break; |
- | |
915 | case 3: |
- | |
916 | size = track->vtx_size * nverts; |
- | |
917 | if (size != track->immd_dwords) { |
- | |
918 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", |
- | |
919 | track->immd_dwords, size); |
- | |
920 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", |
- | |
921 | nverts, track->vtx_size); |
- | |
922 | return -EINVAL; |
- | |
923 | } |
- | |
924 | break; |
- | |
925 | default: |
- | |
926 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", |
- | |
927 | prim_walk); |
- | |
928 | return -EINVAL; |
- | |
929 | } |
- | |
930 | return r300_cs_track_texture_check(rdev, track); |
- | |
931 | } |
- | |
932 | - | ||
933 | static inline void r300_cs_track_clear(struct r300_cs_track *track) |
- | |
934 | { |
- | |
935 | unsigned i; |
- | |
936 | - | ||
937 | track->num_cb = 4; |
- | |
938 | track->maxy = 4096; |
- | |
939 | for (i = 0; i < track->num_cb; i++) { |
- | |
940 | track->cb[i].robj = NULL; |
- | |
941 | track->cb[i].pitch = 8192; |
- | |
942 | track->cb[i].cpp = 16; |
- | |
943 | track->cb[i].offset = 0; |
- | |
944 | } |
- | |
945 | track->z_enabled = true; |
- | |
946 | track->zb.robj = NULL; |
- | |
947 | track->zb.pitch = 8192; |
- | |
948 | track->zb.cpp = 4; |
- | |
949 | track->zb.offset = 0; |
- | |
950 | track->vtx_size = 0x7F; |
- | |
951 | track->immd_dwords = 0xFFFFFFFFUL; |
- | |
952 | track->num_arrays = 11; |
- | |
953 | track->max_indx = 0x00FFFFFFUL; |
- | |
954 | for (i = 0; i < track->num_arrays; i++) { |
- | |
955 | track->arrays[i].robj = NULL; |
- | |
956 | track->arrays[i].esize = 0x7F; |
- | |
957 | } |
- | |
958 | for (i = 0; i < 16; i++) { |
- | |
959 | track->textures[i].pitch = 16536; |
- | |
960 | track->textures[i].width = 16536; |
- | |
961 | track->textures[i].height = 16536; |
- | |
962 | track->textures[i].width_11 = 1 << 11; |
- | |
963 | track->textures[i].height_11 = 1 << 11; |
- | |
964 | track->textures[i].num_levels = 12; |
- | |
965 | track->textures[i].txdepth = 16; |
- | |
966 | track->textures[i].cpp = 64; |
- | |
967 | track->textures[i].tex_coord_type = 1; |
- | |
968 | track->textures[i].robj = NULL; |
- | |
969 | /* CS IB emission code makes sure texture unit are disabled */ |
- | |
970 | track->textures[i].enabled = false; |
- | |
971 | track->textures[i].roundup_w = true; |
- | |
972 | track->textures[i].roundup_h = true; |
- | |
973 | } |
- | |
974 | } |
- | |
975 | - | ||
976 | #endif |
- | |
977 | - | ||
978 | static const unsigned r300_reg_safe_bm[159] = { |
- | |
979 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
980 | 0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF, |
- | |
981 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
982 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
983 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
984 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
985 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
986 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
987 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
988 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
989 | 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, |
- | |
990 | 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, |
- | |
991 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
992 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
993 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, |
- | |
994 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
995 | 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, |
- | |
996 | 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
997 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
998 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
999 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1000 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1001 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1002 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1003 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1004 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1005 | 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1006 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1007 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1008 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1009 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1010 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
- | |
1011 | 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF, |
- | |
1012 | 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF, |
- | |
1013 | 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, |
- | |
1014 | 0x00000000, 0x0000C100, 0x00000000, 0x00000000, |
- | |
1015 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
- | |
1016 | 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF, |
- | |
1017 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
- | |
1018 | 0x0003FC01, 0xFFFFFFF8, 0xFE800B19, |
- | |
1019 | }; |
- | |
1020 | - | ||
1021 | #if 0 |
- | |
1022 | - | ||
1023 | static int r300_packet0_check(struct radeon_cs_parser *p, |
691 | static int r300_packet0_check(struct radeon_cs_parser *p, |
1024 | struct radeon_cs_packet *pkt, |
692 | struct radeon_cs_packet *pkt, |
1025 | unsigned idx, unsigned reg) |
693 | unsigned idx, unsigned reg) |
1026 | { |
694 | { |
1027 | struct radeon_cs_chunk *ib_chunk; |
695 | struct radeon_cs_chunk *ib_chunk; |
1028 | struct radeon_cs_reloc *reloc; |
696 | struct radeon_cs_reloc *reloc; |
1029 | struct r300_cs_track *track; |
697 | struct r100_cs_track *track; |
1030 | volatile uint32_t *ib; |
698 | volatile uint32_t *ib; |
1031 | uint32_t tmp; |
699 | uint32_t tmp, tile_flags = 0; |
1032 | unsigned i; |
700 | unsigned i; |
1033 | int r; |
701 | int r; |
1034 | 702 | ||
1035 | ib = p->ib->ptr; |
703 | ib = p->ib->ptr; |
1036 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
704 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
1037 | track = (struct r300_cs_track*)p->track; |
705 | track = (struct r100_cs_track *)p->track; |
1038 | switch(reg) { |
706 | switch(reg) { |
1039 | case RADEON_DST_PITCH_OFFSET: |
707 | case AVIVO_D1MODE_VLINE_START_END: |
1040 | case RADEON_SRC_PITCH_OFFSET: |
708 | case RADEON_CRTC_GUI_TRIG_VLINE: |
1041 | r = r100_cs_packet_next_reloc(p, &reloc); |
709 | r = r100_cs_packet_parse_vline(p); |
1042 | if (r) { |
710 | if (r) { |
1043 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
711 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1044 | idx, reg); |
712 | idx, reg); |
1045 | r100_cs_dump_packet(p, pkt); |
713 | r100_cs_dump_packet(p, pkt); |
1046 | return r; |
714 | return r; |
1047 | } |
715 | } |
- | 716 | break; |
|
1048 | tmp = ib_chunk->kdata[idx] & 0x003fffff; |
717 | case RADEON_DST_PITCH_OFFSET: |
1049 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); |
718 | case RADEON_SRC_PITCH_OFFSET: |
1050 | ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp; |
719 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
- | 720 | if (r) |
|
- | 721 | return r; |
|
1051 | break; |
722 | break; |
1052 | case R300_RB3D_COLOROFFSET0: |
723 | case R300_RB3D_COLOROFFSET0: |
1053 | case R300_RB3D_COLOROFFSET1: |
724 | case R300_RB3D_COLOROFFSET1: |
1054 | case R300_RB3D_COLOROFFSET2: |
725 | case R300_RB3D_COLOROFFSET2: |
1055 | case R300_RB3D_COLOROFFSET3: |
726 | case R300_RB3D_COLOROFFSET3: |
1056 | i = (reg - R300_RB3D_COLOROFFSET0) >> 2; |
727 | i = (reg - R300_RB3D_COLOROFFSET0) >> 2; |
1057 | r = r100_cs_packet_next_reloc(p, &reloc); |
728 | r = r100_cs_packet_next_reloc(p, &reloc); |
1058 | if (r) { |
729 | if (r) { |
1059 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
730 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1060 | idx, reg); |
731 | idx, reg); |
1061 | r100_cs_dump_packet(p, pkt); |
732 | r100_cs_dump_packet(p, pkt); |
1062 | return r; |
733 | return r; |
1063 | } |
734 | } |
1064 | track->cb[i].robj = reloc->robj; |
735 | track->cb[i].robj = reloc->robj; |
1065 | track->cb[i].offset = ib_chunk->kdata[idx]; |
736 | track->cb[i].offset = ib_chunk->kdata[idx]; |
1066 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
737 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
1067 | break; |
738 | break; |
1068 | case R300_ZB_DEPTHOFFSET: |
739 | case R300_ZB_DEPTHOFFSET: |
1069 | r = r100_cs_packet_next_reloc(p, &reloc); |
740 | r = r100_cs_packet_next_reloc(p, &reloc); |
1070 | if (r) { |
741 | if (r) { |
1071 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
742 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1072 | idx, reg); |
743 | idx, reg); |
1073 | r100_cs_dump_packet(p, pkt); |
744 | r100_cs_dump_packet(p, pkt); |
1074 | return r; |
745 | return r; |
1075 | } |
746 | } |
1076 | track->zb.robj = reloc->robj; |
747 | track->zb.robj = reloc->robj; |
1077 | track->zb.offset = ib_chunk->kdata[idx]; |
748 | track->zb.offset = ib_chunk->kdata[idx]; |
1078 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
749 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
1079 | break; |
750 | break; |
1080 | case R300_TX_OFFSET_0: |
751 | case R300_TX_OFFSET_0: |
1081 | case R300_TX_OFFSET_0+4: |
752 | case R300_TX_OFFSET_0+4: |
1082 | case R300_TX_OFFSET_0+8: |
753 | case R300_TX_OFFSET_0+8: |
1083 | case R300_TX_OFFSET_0+12: |
754 | case R300_TX_OFFSET_0+12: |
1084 | case R300_TX_OFFSET_0+16: |
755 | case R300_TX_OFFSET_0+16: |
1085 | case R300_TX_OFFSET_0+20: |
756 | case R300_TX_OFFSET_0+20: |
1086 | case R300_TX_OFFSET_0+24: |
757 | case R300_TX_OFFSET_0+24: |
1087 | case R300_TX_OFFSET_0+28: |
758 | case R300_TX_OFFSET_0+28: |
1088 | case R300_TX_OFFSET_0+32: |
759 | case R300_TX_OFFSET_0+32: |
1089 | case R300_TX_OFFSET_0+36: |
760 | case R300_TX_OFFSET_0+36: |
1090 | case R300_TX_OFFSET_0+40: |
761 | case R300_TX_OFFSET_0+40: |
1091 | case R300_TX_OFFSET_0+44: |
762 | case R300_TX_OFFSET_0+44: |
1092 | case R300_TX_OFFSET_0+48: |
763 | case R300_TX_OFFSET_0+48: |
1093 | case R300_TX_OFFSET_0+52: |
764 | case R300_TX_OFFSET_0+52: |
1094 | case R300_TX_OFFSET_0+56: |
765 | case R300_TX_OFFSET_0+56: |
1095 | case R300_TX_OFFSET_0+60: |
766 | case R300_TX_OFFSET_0+60: |
1096 | i = (reg - R300_TX_OFFSET_0) >> 2; |
767 | i = (reg - R300_TX_OFFSET_0) >> 2; |
1097 | r = r100_cs_packet_next_reloc(p, &reloc); |
768 | r = r100_cs_packet_next_reloc(p, &reloc); |
1098 | if (r) { |
769 | if (r) { |
1099 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
770 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1100 | idx, reg); |
771 | idx, reg); |
1101 | r100_cs_dump_packet(p, pkt); |
772 | r100_cs_dump_packet(p, pkt); |
1102 | return r; |
773 | return r; |
1103 | } |
774 | } |
1104 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
775 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
1105 | track->textures[i].robj = reloc->robj; |
776 | track->textures[i].robj = reloc->robj; |
1106 | break; |
777 | break; |
1107 | /* Tracked registers */ |
778 | /* Tracked registers */ |
1108 | case 0x2084: |
779 | case 0x2084: |
1109 | /* VAP_VF_CNTL */ |
780 | /* VAP_VF_CNTL */ |
1110 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
781 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
1111 | break; |
782 | break; |
1112 | case 0x20B4: |
783 | case 0x20B4: |
1113 | /* VAP_VTX_SIZE */ |
784 | /* VAP_VTX_SIZE */ |
1114 | track->vtx_size = ib_chunk->kdata[idx] & 0x7F; |
785 | track->vtx_size = ib_chunk->kdata[idx] & 0x7F; |
1115 | break; |
786 | break; |
1116 | case 0x2134: |
787 | case 0x2134: |
1117 | /* VAP_VF_MAX_VTX_INDX */ |
788 | /* VAP_VF_MAX_VTX_INDX */ |
1118 | track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; |
789 | track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; |
1119 | break; |
790 | break; |
1120 | case 0x43E4: |
791 | case 0x43E4: |
1121 | /* SC_SCISSOR1 */ |
792 | /* SC_SCISSOR1 */ |
1122 | track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1; |
793 | track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1; |
1123 | if (p->rdev->family < CHIP_RV515) { |
794 | if (p->rdev->family < CHIP_RV515) { |
1124 | track->maxy -= 1440; |
795 | track->maxy -= 1440; |
1125 | } |
796 | } |
1126 | break; |
797 | break; |
1127 | case 0x4E00: |
798 | case 0x4E00: |
1128 | /* RB3D_CCTL */ |
799 | /* RB3D_CCTL */ |
1129 | track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1; |
800 | track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1; |
1130 | break; |
801 | break; |
1131 | case 0x4E38: |
802 | case 0x4E38: |
1132 | case 0x4E3C: |
803 | case 0x4E3C: |
1133 | case 0x4E40: |
804 | case 0x4E40: |
1134 | case 0x4E44: |
805 | case 0x4E44: |
1135 | /* RB3D_COLORPITCH0 */ |
806 | /* RB3D_COLORPITCH0 */ |
1136 | /* RB3D_COLORPITCH1 */ |
807 | /* RB3D_COLORPITCH1 */ |
1137 | /* RB3D_COLORPITCH2 */ |
808 | /* RB3D_COLORPITCH2 */ |
1138 | /* RB3D_COLORPITCH3 */ |
809 | /* RB3D_COLORPITCH3 */ |
- | 810 | r = r100_cs_packet_next_reloc(p, &reloc); |
|
- | 811 | if (r) { |
|
- | 812 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
|
- | 813 | idx, reg); |
|
- | 814 | r100_cs_dump_packet(p, pkt); |
|
- | 815 | return r; |
|
- | 816 | } |
|
- | 817 | ||
- | 818 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
|
- | 819 | tile_flags |= R300_COLOR_TILE_ENABLE; |
|
- | 820 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
|
- | 821 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
|
- | 822 | ||
- | 823 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); |
|
- | 824 | tmp |= tile_flags; |
|
- | 825 | ib[idx] = tmp; |
|
- | 826 | ||
1139 | i = (reg - 0x4E38) >> 2; |
827 | i = (reg - 0x4E38) >> 2; |
1140 | track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE; |
828 | track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE; |
1141 | switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) { |
829 | switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) { |
1142 | case 9: |
830 | case 9: |
1143 | case 11: |
831 | case 11: |
1144 | case 12: |
832 | case 12: |
1145 | track->cb[i].cpp = 1; |
833 | track->cb[i].cpp = 1; |
1146 | break; |
834 | break; |
1147 | case 3: |
835 | case 3: |
1148 | case 4: |
836 | case 4: |
1149 | case 13: |
837 | case 13: |
1150 | case 15: |
838 | case 15: |
1151 | track->cb[i].cpp = 2; |
839 | track->cb[i].cpp = 2; |
1152 | break; |
840 | break; |
1153 | case 6: |
841 | case 6: |
1154 | track->cb[i].cpp = 4; |
842 | track->cb[i].cpp = 4; |
1155 | break; |
843 | break; |
1156 | case 10: |
844 | case 10: |
1157 | track->cb[i].cpp = 8; |
845 | track->cb[i].cpp = 8; |
1158 | break; |
846 | break; |
1159 | case 7: |
847 | case 7: |
1160 | track->cb[i].cpp = 16; |
848 | track->cb[i].cpp = 16; |
1161 | break; |
849 | break; |
1162 | default: |
850 | default: |
1163 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
851 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
1164 | ((ib_chunk->kdata[idx] >> 21) & 0xF)); |
852 | ((ib_chunk->kdata[idx] >> 21) & 0xF)); |
1165 | return -EINVAL; |
853 | return -EINVAL; |
1166 | } |
854 | } |
1167 | break; |
855 | break; |
1168 | case 0x4F00: |
856 | case 0x4F00: |
1169 | /* ZB_CNTL */ |
857 | /* ZB_CNTL */ |
1170 | if (ib_chunk->kdata[idx] & 2) { |
858 | if (ib_chunk->kdata[idx] & 2) { |
1171 | track->z_enabled = true; |
859 | track->z_enabled = true; |
1172 | } else { |
860 | } else { |
1173 | track->z_enabled = false; |
861 | track->z_enabled = false; |
1174 | } |
862 | } |
1175 | break; |
863 | break; |
1176 | case 0x4F10: |
864 | case 0x4F10: |
1177 | /* ZB_FORMAT */ |
865 | /* ZB_FORMAT */ |
1178 | switch ((ib_chunk->kdata[idx] & 0xF)) { |
866 | switch ((ib_chunk->kdata[idx] & 0xF)) { |
1179 | case 0: |
867 | case 0: |
1180 | case 1: |
868 | case 1: |
1181 | track->zb.cpp = 2; |
869 | track->zb.cpp = 2; |
1182 | break; |
870 | break; |
1183 | case 2: |
871 | case 2: |
1184 | track->zb.cpp = 4; |
872 | track->zb.cpp = 4; |
1185 | break; |
873 | break; |
1186 | default: |
874 | default: |
1187 | DRM_ERROR("Invalid z buffer format (%d) !\n", |
875 | DRM_ERROR("Invalid z buffer format (%d) !\n", |
1188 | (ib_chunk->kdata[idx] & 0xF)); |
876 | (ib_chunk->kdata[idx] & 0xF)); |
1189 | return -EINVAL; |
877 | return -EINVAL; |
1190 | } |
878 | } |
1191 | break; |
879 | break; |
1192 | case 0x4F24: |
880 | case 0x4F24: |
1193 | /* ZB_DEPTHPITCH */ |
881 | /* ZB_DEPTHPITCH */ |
- | 882 | r = r100_cs_packet_next_reloc(p, &reloc); |
|
- | 883 | if (r) { |
|
- | 884 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
|
- | 885 | idx, reg); |
|
- | 886 | r100_cs_dump_packet(p, pkt); |
|
- | 887 | return r; |
|
- | 888 | } |
|
- | 889 | ||
- | 890 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
|
- | 891 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; |
|
- | 892 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
|
- | 893 | tile_flags |= R300_DEPTHMICROTILE_TILED;; |
|
- | 894 | ||
- | 895 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); |
|
- | 896 | tmp |= tile_flags; |
|
- | 897 | ib[idx] = tmp; |
|
- | 898 | ||
1194 | track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC; |
899 | track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC; |
1195 | break; |
900 | break; |
1196 | case 0x4104: |
901 | case 0x4104: |
1197 | for (i = 0; i < 16; i++) { |
902 | for (i = 0; i < 16; i++) { |
1198 | bool enabled; |
903 | bool enabled; |
1199 | 904 | ||
1200 | enabled = !!(ib_chunk->kdata[idx] & (1 << i)); |
905 | enabled = !!(ib_chunk->kdata[idx] & (1 << i)); |
1201 | track->textures[i].enabled = enabled; |
906 | track->textures[i].enabled = enabled; |
1202 | } |
907 | } |
1203 | break; |
908 | break; |
1204 | case 0x44C0: |
909 | case 0x44C0: |
1205 | case 0x44C4: |
910 | case 0x44C4: |
1206 | case 0x44C8: |
911 | case 0x44C8: |
1207 | case 0x44CC: |
912 | case 0x44CC: |
1208 | case 0x44D0: |
913 | case 0x44D0: |
1209 | case 0x44D4: |
914 | case 0x44D4: |
1210 | case 0x44D8: |
915 | case 0x44D8: |
1211 | case 0x44DC: |
916 | case 0x44DC: |
1212 | case 0x44E0: |
917 | case 0x44E0: |
1213 | case 0x44E4: |
918 | case 0x44E4: |
1214 | case 0x44E8: |
919 | case 0x44E8: |
1215 | case 0x44EC: |
920 | case 0x44EC: |
1216 | case 0x44F0: |
921 | case 0x44F0: |
1217 | case 0x44F4: |
922 | case 0x44F4: |
1218 | case 0x44F8: |
923 | case 0x44F8: |
1219 | case 0x44FC: |
924 | case 0x44FC: |
1220 | /* TX_FORMAT1_[0-15] */ |
925 | /* TX_FORMAT1_[0-15] */ |
1221 | i = (reg - 0x44C0) >> 2; |
926 | i = (reg - 0x44C0) >> 2; |
1222 | tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; |
927 | tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; |
1223 | track->textures[i].tex_coord_type = tmp; |
928 | track->textures[i].tex_coord_type = tmp; |
1224 | switch ((ib_chunk->kdata[idx] & 0x1F)) { |
929 | switch ((ib_chunk->kdata[idx] & 0x1F)) { |
1225 | case 0: |
- | |
1226 | case 2: |
- | |
1227 | case 5: |
- | |
1228 | case 18: |
930 | case R300_TX_FORMAT_X8: |
1229 | case 20: |
931 | case R300_TX_FORMAT_Y4X4: |
1230 | case 21: |
932 | case R300_TX_FORMAT_Z3Y3X2: |
1231 | track->textures[i].cpp = 1; |
933 | track->textures[i].cpp = 1; |
1232 | break; |
934 | break; |
1233 | case 1: |
935 | case R300_TX_FORMAT_X16: |
1234 | case 3: |
936 | case R300_TX_FORMAT_Y8X8: |
1235 | case 6: |
937 | case R300_TX_FORMAT_Z5Y6X5: |
1236 | case 7: |
938 | case R300_TX_FORMAT_Z6Y5X5: |
1237 | case 10: |
939 | case R300_TX_FORMAT_W4Z4Y4X4: |
1238 | case 11: |
940 | case R300_TX_FORMAT_W1Z5Y5X5: |
1239 | case 19: |
941 | case R300_TX_FORMAT_DXT1: |
- | 942 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
|
1240 | case 22: |
943 | case R300_TX_FORMAT_B8G8_B8G8: |
1241 | case 24: |
944 | case R300_TX_FORMAT_G8R8_G8B8: |
1242 | track->textures[i].cpp = 2; |
945 | track->textures[i].cpp = 2; |
1243 | break; |
946 | break; |
1244 | case 4: |
947 | case R300_TX_FORMAT_Y16X16: |
- | 948 | case R300_TX_FORMAT_Z11Y11X10: |
|
1245 | case 8: |
949 | case R300_TX_FORMAT_Z10Y11X11: |
1246 | case 9: |
950 | case R300_TX_FORMAT_W8Z8Y8X8: |
1247 | case 12: |
951 | case R300_TX_FORMAT_W2Z10Y10X10: |
1248 | case 13: |
952 | case 0x17: |
1249 | case 23: |
953 | case R300_TX_FORMAT_FL_I32: |
1250 | case 25: |
954 | case 0x1e: |
1251 | case 27: |
955 | case R300_TX_FORMAT_DXT3: |
1252 | case 30: |
956 | case R300_TX_FORMAT_DXT5: |
1253 | track->textures[i].cpp = 4; |
957 | track->textures[i].cpp = 4; |
1254 | break; |
958 | break; |
1255 | case 14: |
959 | case R300_TX_FORMAT_W16Z16Y16X16: |
1256 | case 26: |
960 | case R300_TX_FORMAT_FL_R16G16B16A16: |
1257 | case 28: |
961 | case R300_TX_FORMAT_FL_I32A32: |
1258 | track->textures[i].cpp = 8; |
962 | track->textures[i].cpp = 8; |
1259 | break; |
963 | break; |
1260 | case 29: |
964 | case R300_TX_FORMAT_FL_R32G32B32A32: |
1261 | track->textures[i].cpp = 16; |
965 | track->textures[i].cpp = 16; |
1262 | break; |
966 | break; |
1263 | default: |
967 | default: |
1264 | DRM_ERROR("Invalid texture format %u\n", |
968 | DRM_ERROR("Invalid texture format %u\n", |
1265 | (ib_chunk->kdata[idx] & 0x1F)); |
969 | (ib_chunk->kdata[idx] & 0x1F)); |
1266 | return -EINVAL; |
970 | return -EINVAL; |
1267 | break; |
971 | break; |
1268 | } |
972 | } |
1269 | break; |
973 | break; |
1270 | case 0x4400: |
974 | case 0x4400: |
1271 | case 0x4404: |
975 | case 0x4404: |
1272 | case 0x4408: |
976 | case 0x4408: |
1273 | case 0x440C: |
977 | case 0x440C: |
1274 | case 0x4410: |
978 | case 0x4410: |
1275 | case 0x4414: |
979 | case 0x4414: |
1276 | case 0x4418: |
980 | case 0x4418: |
1277 | case 0x441C: |
981 | case 0x441C: |
1278 | case 0x4420: |
982 | case 0x4420: |
1279 | case 0x4424: |
983 | case 0x4424: |
1280 | case 0x4428: |
984 | case 0x4428: |
1281 | case 0x442C: |
985 | case 0x442C: |
1282 | case 0x4430: |
986 | case 0x4430: |
1283 | case 0x4434: |
987 | case 0x4434: |
1284 | case 0x4438: |
988 | case 0x4438: |
1285 | case 0x443C: |
989 | case 0x443C: |
1286 | /* TX_FILTER0_[0-15] */ |
990 | /* TX_FILTER0_[0-15] */ |
1287 | i = (reg - 0x4400) >> 2; |
991 | i = (reg - 0x4400) >> 2; |
1288 | tmp = ib_chunk->kdata[idx] & 0x7;; |
992 | tmp = ib_chunk->kdata[idx] & 0x7; |
1289 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
993 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
1290 | track->textures[i].roundup_w = false; |
994 | track->textures[i].roundup_w = false; |
1291 | } |
995 | } |
1292 | tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;; |
996 | tmp = (ib_chunk->kdata[idx] >> 3) & 0x7; |
1293 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
997 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
1294 | track->textures[i].roundup_h = false; |
998 | track->textures[i].roundup_h = false; |
1295 | } |
999 | } |
1296 | break; |
1000 | break; |
1297 | case 0x4500: |
1001 | case 0x4500: |
1298 | case 0x4504: |
1002 | case 0x4504: |
1299 | case 0x4508: |
1003 | case 0x4508: |
1300 | case 0x450C: |
1004 | case 0x450C: |
1301 | case 0x4510: |
1005 | case 0x4510: |
1302 | case 0x4514: |
1006 | case 0x4514: |
1303 | case 0x4518: |
1007 | case 0x4518: |
1304 | case 0x451C: |
1008 | case 0x451C: |
1305 | case 0x4520: |
1009 | case 0x4520: |
1306 | case 0x4524: |
1010 | case 0x4524: |
1307 | case 0x4528: |
1011 | case 0x4528: |
1308 | case 0x452C: |
1012 | case 0x452C: |
1309 | case 0x4530: |
1013 | case 0x4530: |
1310 | case 0x4534: |
1014 | case 0x4534: |
1311 | case 0x4538: |
1015 | case 0x4538: |
1312 | case 0x453C: |
1016 | case 0x453C: |
1313 | /* TX_FORMAT2_[0-15] */ |
1017 | /* TX_FORMAT2_[0-15] */ |
1314 | i = (reg - 0x4500) >> 2; |
1018 | i = (reg - 0x4500) >> 2; |
1315 | tmp = ib_chunk->kdata[idx] & 0x3FFF; |
1019 | tmp = ib_chunk->kdata[idx] & 0x3FFF; |
1316 | track->textures[i].pitch = tmp + 1; |
1020 | track->textures[i].pitch = tmp + 1; |
1317 | if (p->rdev->family >= CHIP_RV515) { |
1021 | if (p->rdev->family >= CHIP_RV515) { |
1318 | tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11; |
1022 | tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11; |
1319 | track->textures[i].width_11 = tmp; |
1023 | track->textures[i].width_11 = tmp; |
1320 | tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11; |
1024 | tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11; |
1321 | track->textures[i].height_11 = tmp; |
1025 | track->textures[i].height_11 = tmp; |
1322 | } |
1026 | } |
1323 | break; |
1027 | break; |
1324 | case 0x4480: |
1028 | case 0x4480: |
1325 | case 0x4484: |
1029 | case 0x4484: |
1326 | case 0x4488: |
1030 | case 0x4488: |
1327 | case 0x448C: |
1031 | case 0x448C: |
1328 | case 0x4490: |
1032 | case 0x4490: |
1329 | case 0x4494: |
1033 | case 0x4494: |
1330 | case 0x4498: |
1034 | case 0x4498: |
1331 | case 0x449C: |
1035 | case 0x449C: |
1332 | case 0x44A0: |
1036 | case 0x44A0: |
1333 | case 0x44A4: |
1037 | case 0x44A4: |
1334 | case 0x44A8: |
1038 | case 0x44A8: |
1335 | case 0x44AC: |
1039 | case 0x44AC: |
1336 | case 0x44B0: |
1040 | case 0x44B0: |
1337 | case 0x44B4: |
1041 | case 0x44B4: |
1338 | case 0x44B8: |
1042 | case 0x44B8: |
1339 | case 0x44BC: |
1043 | case 0x44BC: |
1340 | /* TX_FORMAT0_[0-15] */ |
1044 | /* TX_FORMAT0_[0-15] */ |
1341 | i = (reg - 0x4480) >> 2; |
1045 | i = (reg - 0x4480) >> 2; |
1342 | tmp = ib_chunk->kdata[idx] & 0x7FF; |
1046 | tmp = ib_chunk->kdata[idx] & 0x7FF; |
1343 | track->textures[i].width = tmp + 1; |
1047 | track->textures[i].width = tmp + 1; |
1344 | tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF; |
1048 | tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF; |
1345 | track->textures[i].height = tmp + 1; |
1049 | track->textures[i].height = tmp + 1; |
1346 | tmp = (ib_chunk->kdata[idx] >> 26) & 0xF; |
1050 | tmp = (ib_chunk->kdata[idx] >> 26) & 0xF; |
1347 | track->textures[i].num_levels = tmp; |
1051 | track->textures[i].num_levels = tmp; |
1348 | tmp = ib_chunk->kdata[idx] & (1 << 31); |
1052 | tmp = ib_chunk->kdata[idx] & (1 << 31); |
1349 | track->textures[i].use_pitch = !!tmp; |
1053 | track->textures[i].use_pitch = !!tmp; |
1350 | tmp = (ib_chunk->kdata[idx] >> 22) & 0xF; |
1054 | tmp = (ib_chunk->kdata[idx] >> 22) & 0xF; |
1351 | track->textures[i].txdepth = tmp; |
1055 | track->textures[i].txdepth = tmp; |
1352 | break; |
1056 | break; |
- | 1057 | case R300_ZB_ZPASS_ADDR: |
|
- | 1058 | r = r100_cs_packet_next_reloc(p, &reloc); |
|
- | 1059 | if (r) { |
|
- | 1060 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
|
- | 1061 | idx, reg); |
|
- | 1062 | r100_cs_dump_packet(p, pkt); |
|
- | 1063 | return r; |
|
- | 1064 | } |
|
- | 1065 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
|
- | 1066 | break; |
|
- | 1067 | case 0x4be8: |
|
- | 1068 | /* valid register only on RV530 */ |
|
- | 1069 | if (p->rdev->family == CHIP_RV530) |
|
- | 1070 | break; |
|
- | 1071 | /* fallthrough do not move */ |
|
1353 | default: |
1072 | default: |
1354 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
1073 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
1355 | reg, idx); |
1074 | reg, idx); |
1356 | return -EINVAL; |
1075 | return -EINVAL; |
1357 | } |
1076 | } |
1358 | return 0; |
1077 | return 0; |
1359 | } |
1078 | } |
1360 | 1079 | ||
1361 | static int r300_packet3_check(struct radeon_cs_parser *p, |
1080 | static int r300_packet3_check(struct radeon_cs_parser *p, |
1362 | struct radeon_cs_packet *pkt) |
1081 | struct radeon_cs_packet *pkt) |
1363 | { |
1082 | { |
1364 | struct radeon_cs_chunk *ib_chunk; |
1083 | struct radeon_cs_chunk *ib_chunk; |
- | 1084 | ||
1365 | struct radeon_cs_reloc *reloc; |
1085 | struct radeon_cs_reloc *reloc; |
1366 | struct r300_cs_track *track; |
1086 | struct r100_cs_track *track; |
1367 | volatile uint32_t *ib; |
1087 | volatile uint32_t *ib; |
1368 | unsigned idx; |
1088 | unsigned idx; |
1369 | unsigned i, c; |
1089 | unsigned i, c; |
1370 | int r; |
1090 | int r; |
1371 | 1091 | ||
1372 | ib = p->ib->ptr; |
1092 | ib = p->ib->ptr; |
1373 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
1093 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
1374 | idx = pkt->idx + 1; |
1094 | idx = pkt->idx + 1; |
1375 | track = (struct r300_cs_track*)p->track; |
1095 | track = (struct r100_cs_track *)p->track; |
1376 | switch(pkt->opcode) { |
1096 | switch(pkt->opcode) { |
1377 | case PACKET3_3D_LOAD_VBPNTR: |
1097 | case PACKET3_3D_LOAD_VBPNTR: |
1378 | c = ib_chunk->kdata[idx++] & 0x1F; |
1098 | c = ib_chunk->kdata[idx++] & 0x1F; |
1379 | track->num_arrays = c; |
1099 | track->num_arrays = c; |
1380 | for (i = 0; i < (c - 1); i+=2, idx+=3) { |
1100 | for (i = 0; i < (c - 1); i+=2, idx+=3) { |
1381 | r = r100_cs_packet_next_reloc(p, &reloc); |
1101 | r = r100_cs_packet_next_reloc(p, &reloc); |
1382 | if (r) { |
1102 | if (r) { |
1383 | DRM_ERROR("No reloc for packet3 %d\n", |
1103 | DRM_ERROR("No reloc for packet3 %d\n", |
1384 | pkt->opcode); |
1104 | pkt->opcode); |
1385 | r100_cs_dump_packet(p, pkt); |
1105 | r100_cs_dump_packet(p, pkt); |
1386 | return r; |
1106 | return r; |
1387 | } |
1107 | } |
1388 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
1108 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
1389 | track->arrays[i + 0].robj = reloc->robj; |
1109 | track->arrays[i + 0].robj = reloc->robj; |
1390 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
1110 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
1391 | track->arrays[i + 0].esize &= 0x7F; |
1111 | track->arrays[i + 0].esize &= 0x7F; |
1392 | r = r100_cs_packet_next_reloc(p, &reloc); |
1112 | r = r100_cs_packet_next_reloc(p, &reloc); |
1393 | if (r) { |
1113 | if (r) { |
1394 | DRM_ERROR("No reloc for packet3 %d\n", |
1114 | DRM_ERROR("No reloc for packet3 %d\n", |
1395 | pkt->opcode); |
1115 | pkt->opcode); |
1396 | r100_cs_dump_packet(p, pkt); |
1116 | r100_cs_dump_packet(p, pkt); |
1397 | return r; |
1117 | return r; |
1398 | } |
1118 | } |
1399 | ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); |
1119 | ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); |
1400 | track->arrays[i + 1].robj = reloc->robj; |
1120 | track->arrays[i + 1].robj = reloc->robj; |
1401 | track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; |
1121 | track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; |
1402 | track->arrays[i + 1].esize &= 0x7F; |
1122 | track->arrays[i + 1].esize &= 0x7F; |
1403 | } |
1123 | } |
1404 | if (c & 1) { |
1124 | if (c & 1) { |
1405 | r = r100_cs_packet_next_reloc(p, &reloc); |
1125 | r = r100_cs_packet_next_reloc(p, &reloc); |
1406 | if (r) { |
1126 | if (r) { |
1407 | DRM_ERROR("No reloc for packet3 %d\n", |
1127 | DRM_ERROR("No reloc for packet3 %d\n", |
1408 | pkt->opcode); |
1128 | pkt->opcode); |
1409 | r100_cs_dump_packet(p, pkt); |
1129 | r100_cs_dump_packet(p, pkt); |
1410 | return r; |
1130 | return r; |
1411 | } |
1131 | } |
1412 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
1132 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
1413 | track->arrays[i + 0].robj = reloc->robj; |
1133 | track->arrays[i + 0].robj = reloc->robj; |
1414 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
1134 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
1415 | track->arrays[i + 0].esize &= 0x7F; |
1135 | track->arrays[i + 0].esize &= 0x7F; |
1416 | } |
1136 | } |
1417 | break; |
1137 | break; |
1418 | case PACKET3_INDX_BUFFER: |
1138 | case PACKET3_INDX_BUFFER: |
1419 | r = r100_cs_packet_next_reloc(p, &reloc); |
1139 | r = r100_cs_packet_next_reloc(p, &reloc); |
1420 | if (r) { |
1140 | if (r) { |
1421 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
1141 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
1422 | r100_cs_dump_packet(p, pkt); |
1142 | r100_cs_dump_packet(p, pkt); |
1423 | return r; |
1143 | return r; |
1424 | } |
1144 | } |
1425 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
1145 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
1426 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1146 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1427 | if (r) { |
1147 | if (r) { |
1428 | return r; |
1148 | return r; |
1429 | } |
1149 | } |
1430 | break; |
1150 | break; |
1431 | /* Draw packet */ |
1151 | /* Draw packet */ |
1432 | case PACKET3_3D_DRAW_IMMD: |
1152 | case PACKET3_3D_DRAW_IMMD: |
1433 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1153 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1434 | * PRIM_WALK must be equal to 3 vertex data in embedded |
1154 | * PRIM_WALK must be equal to 3 vertex data in embedded |
1435 | * in cmd stream */ |
1155 | * in cmd stream */ |
1436 | if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { |
1156 | if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { |
1437 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1157 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1438 | return -EINVAL; |
1158 | return -EINVAL; |
1439 | } |
1159 | } |
1440 | track->vap_vf_cntl = ib_chunk->kdata[idx+1]; |
1160 | track->vap_vf_cntl = ib_chunk->kdata[idx+1]; |
1441 | track->immd_dwords = pkt->count - 1; |
1161 | track->immd_dwords = pkt->count - 1; |
1442 | r = r300_cs_track_check(p->rdev, track); |
1162 | r = r100_cs_track_check(p->rdev, track); |
1443 | if (r) { |
1163 | if (r) { |
1444 | return r; |
1164 | return r; |
1445 | } |
1165 | } |
1446 | break; |
1166 | break; |
1447 | case PACKET3_3D_DRAW_IMMD_2: |
1167 | case PACKET3_3D_DRAW_IMMD_2: |
1448 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1168 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1449 | * PRIM_WALK must be equal to 3 vertex data in embedded |
1169 | * PRIM_WALK must be equal to 3 vertex data in embedded |
1450 | * in cmd stream */ |
1170 | * in cmd stream */ |
1451 | if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { |
1171 | if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { |
1452 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1172 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1453 | return -EINVAL; |
1173 | return -EINVAL; |
1454 | } |
1174 | } |
1455 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
1175 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
1456 | track->immd_dwords = pkt->count; |
1176 | track->immd_dwords = pkt->count; |
1457 | r = r300_cs_track_check(p->rdev, track); |
1177 | r = r100_cs_track_check(p->rdev, track); |
1458 | if (r) { |
1178 | if (r) { |
1459 | return r; |
1179 | return r; |
1460 | } |
1180 | } |
1461 | break; |
1181 | break; |
1462 | case PACKET3_3D_DRAW_VBUF: |
1182 | case PACKET3_3D_DRAW_VBUF: |
1463 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
1183 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
1464 | r = r300_cs_track_check(p->rdev, track); |
1184 | r = r100_cs_track_check(p->rdev, track); |
1465 | if (r) { |
1185 | if (r) { |
1466 | return r; |
1186 | return r; |
1467 | } |
1187 | } |
1468 | break; |
1188 | break; |
1469 | case PACKET3_3D_DRAW_VBUF_2: |
1189 | case PACKET3_3D_DRAW_VBUF_2: |
1470 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
1190 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
1471 | r = r300_cs_track_check(p->rdev, track); |
1191 | r = r100_cs_track_check(p->rdev, track); |
1472 | if (r) { |
1192 | if (r) { |
1473 | return r; |
1193 | return r; |
1474 | } |
1194 | } |
1475 | break; |
1195 | break; |
1476 | case PACKET3_3D_DRAW_INDX: |
1196 | case PACKET3_3D_DRAW_INDX: |
1477 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
1197 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
1478 | r = r300_cs_track_check(p->rdev, track); |
1198 | r = r100_cs_track_check(p->rdev, track); |
1479 | if (r) { |
1199 | if (r) { |
1480 | return r; |
1200 | return r; |
1481 | } |
1201 | } |
1482 | break; |
1202 | break; |
1483 | case PACKET3_3D_DRAW_INDX_2: |
1203 | case PACKET3_3D_DRAW_INDX_2: |
1484 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
1204 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
1485 | r = r300_cs_track_check(p->rdev, track); |
1205 | r = r100_cs_track_check(p->rdev, track); |
1486 | if (r) { |
1206 | if (r) { |
1487 | return r; |
1207 | return r; |
1488 | } |
1208 | } |
1489 | break; |
1209 | break; |
1490 | case PACKET3_NOP: |
1210 | case PACKET3_NOP: |
1491 | break; |
1211 | break; |
1492 | default: |
1212 | default: |
1493 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
1213 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
1494 | return -EINVAL; |
1214 | return -EINVAL; |
1495 | } |
1215 | } |
1496 | return 0; |
1216 | return 0; |
1497 | } |
1217 | } |
1498 | 1218 | ||
1499 | int r300_cs_parse(struct radeon_cs_parser *p) |
1219 | int r300_cs_parse(struct radeon_cs_parser *p) |
1500 | { |
1220 | { |
1501 | struct radeon_cs_packet pkt; |
1221 | struct radeon_cs_packet pkt; |
1502 | struct r300_cs_track track; |
1222 | struct r100_cs_track *track; |
1503 | int r; |
1223 | int r; |
- | 1224 | ||
1504 | 1225 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
|
1505 | r300_cs_track_clear(&track); |
1226 | r100_cs_track_clear(p->rdev, track); |
1506 | p->track = &track; |
1227 | p->track = track; |
1507 | do { |
1228 | do { |
1508 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
1229 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
1509 | if (r) { |
1230 | if (r) { |
1510 | return r; |
1231 | return r; |
1511 | } |
1232 | } |
1512 | p->idx += pkt.count + 2; |
1233 | p->idx += pkt.count + 2; |
1513 | switch (pkt.type) { |
1234 | switch (pkt.type) { |
1514 | case PACKET_TYPE0: |
1235 | case PACKET_TYPE0: |
1515 | r = r100_cs_parse_packet0(p, &pkt, |
1236 | r = r100_cs_parse_packet0(p, &pkt, |
1516 | p->rdev->config.r300.reg_safe_bm, |
1237 | p->rdev->config.r300.reg_safe_bm, |
1517 | p->rdev->config.r300.reg_safe_bm_size, |
1238 | p->rdev->config.r300.reg_safe_bm_size, |
1518 | &r300_packet0_check); |
1239 | &r300_packet0_check); |
1519 | break; |
1240 | break; |
1520 | case PACKET_TYPE2: |
1241 | case PACKET_TYPE2: |
1521 | break; |
1242 | break; |
1522 | case PACKET_TYPE3: |
1243 | case PACKET_TYPE3: |
1523 | r = r300_packet3_check(p, &pkt); |
1244 | r = r300_packet3_check(p, &pkt); |
1524 | break; |
1245 | break; |
1525 | default: |
1246 | default: |
1526 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); |
1247 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); |
1527 | return -EINVAL; |
1248 | return -EINVAL; |
1528 | } |
1249 | } |
1529 | if (r) { |
1250 | if (r) { |
1530 | return r; |
1251 | return r; |
1531 | } |
1252 | } |
1532 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
1253 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
1533 | return 0; |
1254 | return 0; |
1534 | } |
1255 | } |
1535 | - | ||
1536 | #endif |
1256 | #endif |
- | 1257 | ||
1537 | 1258 | ||
1538 | int r300_init(struct radeon_device *rdev) |
1259 | void r300_set_reg_safe(struct radeon_device *rdev) |
1539 | { |
1260 | { |
1540 | rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; |
1261 | rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; |
1541 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); |
1262 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); |
- | 1263 | } |
|
- | 1264 | ||
- | 1265 | int r300_init(struct radeon_device *rdev) |
|
- | 1266 | { |
|
- | 1267 | r300_set_reg_safe(rdev); |
|
1542 | return 0; |
1268 | return 0; |
1543 | }>>><>><>><>><>>>><>><>>>>>>>><>><>><>><>=>>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>><>><>><>><>>> |
1269 | } |
- | 1270 | ||
- | 1271 | void r300_mc_program(struct radeon_device *rdev) |
|
- | 1272 | { |
|
- | 1273 | struct r100_mc_save save; |
|
- | 1274 | int r; |
|
- | 1275 | ||
- | 1276 | r = r100_debugfs_mc_info_init(rdev); |
|
- | 1277 | if (r) { |
|
- | 1278 | dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
|
- | 1279 | } |
|
- | 1280 | ||
- | 1281 | /* Stops all mc clients */ |
|
- | 1282 | r100_mc_stop(rdev, &save); |
|
- | 1283 | if (rdev->flags & RADEON_IS_AGP) { |
|
- | 1284 | WREG32(R_00014C_MC_AGP_LOCATION, |
|
- | 1285 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
|
- | 1286 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
|
- | 1287 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
|
- | 1288 | WREG32(R_00015C_AGP_BASE_2, |
|
- | 1289 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
|
- | 1290 | } else { |
|
- | 1291 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
|
- | 1292 | WREG32(R_000170_AGP_BASE, 0); |
|
- | 1293 | WREG32(R_00015C_AGP_BASE_2, 0); |
|
- | 1294 | } |
|
- | 1295 | /* Wait for mc idle */ |
|
- | 1296 | if (r300_mc_wait_for_idle(rdev)) |
|
- | 1297 | DRM_INFO("Failed to wait MC idle before programming MC.\n"); |
|
- | 1298 | /* Program MC, should be a 32bits limited address space */ |
|
- | 1299 | WREG32(R_000148_MC_FB_LOCATION, |
|
- | 1300 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
|
- | 1301 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
|
- | 1302 | r100_mc_resume(rdev, &save); |
|
- | 1303 | }>>><>><>><>><>>><>><>>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>><>><>><>><>>> |