WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r200.c



#include "radeon_asic.h"

 
#include "r100d.h"

 
 
#include "r200_reg_safe.h"

 
#include "r100_track.h"
 

		vtx_size++;
	if (vtx_fmt_0 & R200_VTX_N1)
		vtx_size += 3;
	return vtx_size;
}
 

 
int r200_copy_dma(struct radeon_device *rdev,
		  uint64_t src_offset,
		  uint64_t dst_offset,

	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
	radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);
	if (fence) {
		r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
	}
	radeon_ring_unlock_commit(rdev, ring, false);
	return r;
}
 

 
static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
{
	int vtx_size, i, tex_size;

			return r;
		}
		track->zb.robj = reloc->robj;
		track->zb.offset = idx_value;
		track->zb_dirty = true;
		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
		break;
	case RADEON_RB3D_COLOROFFSET:
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",

			return r;
		}
		track->cb[0].robj = reloc->robj;
		track->cb[0].offset = idx_value;
		track->cb_dirty = true;
		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
		break;
	case R200_PP_TXOFFSET_0:
	case R200_PP_TXOFFSET_1:
	case R200_PP_TXOFFSET_2:
	case R200_PP_TXOFFSET_3:

				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
			if (reloc->tiling_flags & RADEON_TILING_MACRO)
				tile_flags |= R200_TXO_MACRO_TILE;
			if (reloc->tiling_flags & RADEON_TILING_MICRO)
				tile_flags |= R200_TXO_MICRO_TILE;

 
			tmp = idx_value & ~(0x7 << 2);
			tmp |= tile_flags;
			ib[idx] = tmp + ((u32)reloc->gpu_offset);
		} else
			ib[idx] = idx_value + ((u32)reloc->gpu_offset);
		track->textures[i].robj = reloc->robj;
		track->tex_dirty = true;
		break;
	case R200_PP_CUBIC_OFFSET_F1_0:

				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		track->textures[i].cube_info[face - 1].offset = idx_value;
		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
		track->textures[i].cube_info[face - 1].robj = reloc->robj;
		track->tex_dirty = true;
		break;
	case RADEON_RE_WIDTH_HEIGHT:
		track->maxy = ((idx_value >> 16) & 0x7FF);

			radeon_cs_dump_packet(p, pkt);
			return r;
		}

 
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
			if (reloc->tiling_flags & RADEON_TILING_MACRO)
			tile_flags |= RADEON_COLOR_TILE_ENABLE;
			if (reloc->tiling_flags & RADEON_TILING_MICRO)

			tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
 
		tmp = idx_value & ~(0x7 << 16);

			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
		break;
	case RADEON_PP_CNTL:
		{
			uint32_t temp = idx_value >> 4;
			for (i = 0; i < track->num_texture; i++)

		       reg, idx);
		return -EINVAL;
	}
	return 0;
}
 

 
void r200_set_safe_registers(struct radeon_device *rdev)
{
	rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;

Rev 3764	Rev 5078
Line 32...	Line 32...
32	#include "radeon_asic.h"	32	#include "radeon_asic.h"
Line 33...	Line 33...
33		33
34	#include "r100d.h"	34	#include "r100d.h"
Line 35...	Line -...
35	#include "r200_reg_safe.h"	-
36		-
37	#if 0	35	#include "r200_reg_safe.h"
Line 38...	Line 36...
38		36
39	#include "r100_track.h"	37	#include "r100_track.h"
40		38
Line 79...	Line 77...
79	vtx_size++;	77	vtx_size++;
80	if (vtx_fmt_0 & R200_VTX_N1)	78	if (vtx_fmt_0 & R200_VTX_N1)
81	vtx_size += 3;	79	vtx_size += 3;
82	return vtx_size;	80	return vtx_size;
83	}	81	}
84	#endif	-
Line 85...	Line 82...
85		82
86	int r200_copy_dma(struct radeon_device *rdev,	83	int r200_copy_dma(struct radeon_device *rdev,
87	uint64_t src_offset,	84	uint64_t src_offset,
88	uint64_t dst_offset,	85	uint64_t dst_offset,
Line 122...	Line 119...
122	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));	119	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
123	radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);	120	radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);
124	if (fence) {	121	if (fence) {
125	r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);	122	r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
126	}	123	}
127	radeon_ring_unlock_commit(rdev, ring);	124	radeon_ring_unlock_commit(rdev, ring, false);
128	return r;	125	return r;
129	}	126	}
130	#if 0	127
Line 131...	Line 128...
131		128
132	static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)	129	static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
133	{	130	{
134	int vtx_size, i, tex_size;	131	int vtx_size, i, tex_size;
Line 186...	Line 183...
186	return r;	183	return r;
187	}	184	}
188	track->zb.robj = reloc->robj;	185	track->zb.robj = reloc->robj;
189	track->zb.offset = idx_value;	186	track->zb.offset = idx_value;
190	track->zb_dirty = true;	187	track->zb_dirty = true;
191	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);	188	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
192	break;	189	break;
193	case RADEON_RB3D_COLOROFFSET:	190	case RADEON_RB3D_COLOROFFSET:
194	r = radeon_cs_packet_next_reloc(p, &reloc, 0);	191	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
195	if (r) {	192	if (r) {
196	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	193	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
Line 199...	Line 196...
199	return r;	196	return r;
200	}	197	}
201	track->cb[0].robj = reloc->robj;	198	track->cb[0].robj = reloc->robj;
202	track->cb[0].offset = idx_value;	199	track->cb[0].offset = idx_value;
203	track->cb_dirty = true;	200	track->cb_dirty = true;
204	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);	201	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
205	break;	202	break;
206	case R200_PP_TXOFFSET_0:	203	case R200_PP_TXOFFSET_0:
207	case R200_PP_TXOFFSET_1:	204	case R200_PP_TXOFFSET_1:
208	case R200_PP_TXOFFSET_2:	205	case R200_PP_TXOFFSET_2:
209	case R200_PP_TXOFFSET_3:	206	case R200_PP_TXOFFSET_3:
Line 216...	Line 213...
216	idx, reg);	213	idx, reg);
217	radeon_cs_dump_packet(p, pkt);	214	radeon_cs_dump_packet(p, pkt);
218	return r;	215	return r;
219	}	216	}
220	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {	217	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
221	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)	218	if (reloc->tiling_flags & RADEON_TILING_MACRO)
222	tile_flags \|= R200_TXO_MACRO_TILE;	219	tile_flags \|= R200_TXO_MACRO_TILE;
223	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)	220	if (reloc->tiling_flags & RADEON_TILING_MICRO)
224	tile_flags \|= R200_TXO_MICRO_TILE;	221	tile_flags \|= R200_TXO_MICRO_TILE;
Line 225...	Line 222...
225		222
226	tmp = idx_value & ~(0x7 << 2);	223	tmp = idx_value & ~(0x7 << 2);
227	tmp \|= tile_flags;	224	tmp \|= tile_flags;
228	ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);	225	ib[idx] = tmp + ((u32)reloc->gpu_offset);
229	} else	226	} else
230	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);	227	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
231	track->textures[i].robj = reloc->robj;	228	track->textures[i].robj = reloc->robj;
232	track->tex_dirty = true;	229	track->tex_dirty = true;
233	break;	230	break;
234	case R200_PP_CUBIC_OFFSET_F1_0:	231	case R200_PP_CUBIC_OFFSET_F1_0:
Line 269...	Line 266...
269	idx, reg);	266	idx, reg);
270	radeon_cs_dump_packet(p, pkt);	267	radeon_cs_dump_packet(p, pkt);
271	return r;	268	return r;
272	}	269	}
273	track->textures[i].cube_info[face - 1].offset = idx_value;	270	track->textures[i].cube_info[face - 1].offset = idx_value;
274	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);	271	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
275	track->textures[i].cube_info[face - 1].robj = reloc->robj;	272	track->textures[i].cube_info[face - 1].robj = reloc->robj;
276	track->tex_dirty = true;	273	track->tex_dirty = true;
277	break;	274	break;
278	case RADEON_RE_WIDTH_HEIGHT:	275	case RADEON_RE_WIDTH_HEIGHT:
279	track->maxy = ((idx_value >> 16) & 0x7FF);	276	track->maxy = ((idx_value >> 16) & 0x7FF);
Line 288...	Line 285...
288	radeon_cs_dump_packet(p, pkt);	285	radeon_cs_dump_packet(p, pkt);
289	return r;	286	return r;
290	}	287	}
Line 291...	Line 288...
291		288
292	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {	289	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
293	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)	290	if (reloc->tiling_flags & RADEON_TILING_MACRO)
294	tile_flags \|= RADEON_COLOR_TILE_ENABLE;	291	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
295	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)	292	if (reloc->tiling_flags & RADEON_TILING_MICRO)
Line 296...	Line 293...
296	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;	293	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
297		294
298	tmp = idx_value & ~(0x7 << 16);	295	tmp = idx_value & ~(0x7 << 16);
Line 363...	Line 360...
363	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	360	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
364	idx, reg);	361	idx, reg);
365	radeon_cs_dump_packet(p, pkt);	362	radeon_cs_dump_packet(p, pkt);
366	return r;	363	return r;
367	}	364	}
368	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);	365	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
369	break;	366	break;
370	case RADEON_PP_CNTL:	367	case RADEON_PP_CNTL:
371	{	368	{
372	uint32_t temp = idx_value >> 4;	369	uint32_t temp = idx_value >> 4;
373	for (i = 0; i < track->num_texture; i++)	370	for (i = 0; i < track->num_texture; i++)
Line 541...	Line 538...
541	reg, idx);	538	reg, idx);
542	return -EINVAL;	539	return -EINVAL;
543	}	540	}
544	return 0;	541	return 0;
545	}	542	}
546	#endif	-
Line 547...	Line 543...
547		543
548	void r200_set_safe_registers(struct radeon_device *rdev)	544	void r200_set_safe_registers(struct radeon_device *rdev)
549	{	545	{
550	rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;	546	rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r200.c – Rev 3764 → 5078