WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r200.c



	case RADEON_CRTC_GUI_TRIG_VLINE:
		r = r100_cs_packet_parse_vline(p);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		break;
		/* FIXME: only allow PACKET3 blit? easier to check for out of
		 * range access */

		r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		if (r)
			return r;
		break;
	case RADEON_RB3D_DEPTHOFFSET:
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		track->zb.robj = reloc->robj;
		track->zb.offset = idx_value;
		track->zb_dirty = true;
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		break;
	case RADEON_RB3D_COLOROFFSET:
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		track->cb[0].robj = reloc->robj;
		track->cb[0].offset = idx_value;
		track->cb_dirty = true;

	case R200_PP_TXOFFSET_2:
	case R200_PP_TXOFFSET_3:
	case R200_PP_TXOFFSET_4:
	case R200_PP_TXOFFSET_5:
		i = (reg - R200_PP_TXOFFSET_0) / 24;
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
				tile_flags |= R200_TXO_MACRO_TILE;

	case R200_PP_CUBIC_OFFSET_F3_5:
	case R200_PP_CUBIC_OFFSET_F4_5:
	case R200_PP_CUBIC_OFFSET_F5_5:
		i = (reg - R200_PP_TXOFFSET_0) / 24;
		face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		track->textures[i].cube_info[face - 1].offset = idx_value;
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		track->textures[i].cube_info[face - 1].robj = reloc->robj;

		track->maxy = ((idx_value >> 16) & 0x7FF);
		track->cb_dirty = true;
		track->zb_dirty = true;
		break;
	case RADEON_RB3D_COLORPITCH:
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}

 
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {

			break;
		}
		track->zb_dirty = true;
		break;
	case RADEON_RB3D_ZPASS_ADDR:
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			radeon_cs_dump_packet(p, pkt);
			return r;
		}
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		break;
	case RADEON_PP_CNTL:

Rev 2997	Rev 3764
Line 163...	Line 163...
163	case RADEON_CRTC_GUI_TRIG_VLINE:	163	case RADEON_CRTC_GUI_TRIG_VLINE:
164	r = r100_cs_packet_parse_vline(p);	164	r = r100_cs_packet_parse_vline(p);
165	if (r) {	165	if (r) {
166	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	166	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
167	idx, reg);	167	idx, reg);
168	r100_cs_dump_packet(p, pkt);	168	radeon_cs_dump_packet(p, pkt);
169	return r;	169	return r;
170	}	170	}
171	break;	171	break;
172	/* FIXME: only allow PACKET3 blit? easier to check for out of	172	/* FIXME: only allow PACKET3 blit? easier to check for out of
173	* range access */	173	* range access */
Line 176...	Line 176...
176	r = r100_reloc_pitch_offset(p, pkt, idx, reg);	176	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
177	if (r)	177	if (r)
178	return r;	178	return r;
179	break;	179	break;
180	case RADEON_RB3D_DEPTHOFFSET:	180	case RADEON_RB3D_DEPTHOFFSET:
181	r = r100_cs_packet_next_reloc(p, &reloc);	181	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
182	if (r) {	182	if (r) {
183	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	183	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
184	idx, reg);	184	idx, reg);
185	r100_cs_dump_packet(p, pkt);	185	radeon_cs_dump_packet(p, pkt);
186	return r;	186	return r;
187	}	187	}
188	track->zb.robj = reloc->robj;	188	track->zb.robj = reloc->robj;
189	track->zb.offset = idx_value;	189	track->zb.offset = idx_value;
190	track->zb_dirty = true;	190	track->zb_dirty = true;
191	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);	191	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
192	break;	192	break;
193	case RADEON_RB3D_COLOROFFSET:	193	case RADEON_RB3D_COLOROFFSET:
194	r = r100_cs_packet_next_reloc(p, &reloc);	194	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
195	if (r) {	195	if (r) {
196	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	196	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
197	idx, reg);	197	idx, reg);
198	r100_cs_dump_packet(p, pkt);	198	radeon_cs_dump_packet(p, pkt);
199	return r;	199	return r;
200	}	200	}
201	track->cb[0].robj = reloc->robj;	201	track->cb[0].robj = reloc->robj;
202	track->cb[0].offset = idx_value;	202	track->cb[0].offset = idx_value;
203	track->cb_dirty = true;	203	track->cb_dirty = true;
Line 208...	Line 208...
208	case R200_PP_TXOFFSET_2:	208	case R200_PP_TXOFFSET_2:
209	case R200_PP_TXOFFSET_3:	209	case R200_PP_TXOFFSET_3:
210	case R200_PP_TXOFFSET_4:	210	case R200_PP_TXOFFSET_4:
211	case R200_PP_TXOFFSET_5:	211	case R200_PP_TXOFFSET_5:
212	i = (reg - R200_PP_TXOFFSET_0) / 24;	212	i = (reg - R200_PP_TXOFFSET_0) / 24;
213	r = r100_cs_packet_next_reloc(p, &reloc);	213	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
214	if (r) {	214	if (r) {
215	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	215	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
216	idx, reg);	216	idx, reg);
217	r100_cs_dump_packet(p, pkt);	217	radeon_cs_dump_packet(p, pkt);
218	return r;	218	return r;
219	}	219	}
220	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {	220	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
221	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)	221	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
222	tile_flags \|= R200_TXO_MACRO_TILE;	222	tile_flags \|= R200_TXO_MACRO_TILE;
Line 261...	Line 261...
261	case R200_PP_CUBIC_OFFSET_F3_5:	261	case R200_PP_CUBIC_OFFSET_F3_5:
262	case R200_PP_CUBIC_OFFSET_F4_5:	262	case R200_PP_CUBIC_OFFSET_F4_5:
263	case R200_PP_CUBIC_OFFSET_F5_5:	263	case R200_PP_CUBIC_OFFSET_F5_5:
264	i = (reg - R200_PP_TXOFFSET_0) / 24;	264	i = (reg - R200_PP_TXOFFSET_0) / 24;
265	face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;	265	face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
266	r = r100_cs_packet_next_reloc(p, &reloc);	266	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
267	if (r) {	267	if (r) {
268	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	268	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
269	idx, reg);	269	idx, reg);
270	r100_cs_dump_packet(p, pkt);	270	radeon_cs_dump_packet(p, pkt);
271	return r;	271	return r;
272	}	272	}
273	track->textures[i].cube_info[face - 1].offset = idx_value;	273	track->textures[i].cube_info[face - 1].offset = idx_value;
274	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);	274	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
275	track->textures[i].cube_info[face - 1].robj = reloc->robj;	275	track->textures[i].cube_info[face - 1].robj = reloc->robj;
Line 279...	Line 279...
279	track->maxy = ((idx_value >> 16) & 0x7FF);	279	track->maxy = ((idx_value >> 16) & 0x7FF);
280	track->cb_dirty = true;	280	track->cb_dirty = true;
281	track->zb_dirty = true;	281	track->zb_dirty = true;
282	break;	282	break;
283	case RADEON_RB3D_COLORPITCH:	283	case RADEON_RB3D_COLORPITCH:
284	r = r100_cs_packet_next_reloc(p, &reloc);	284	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
285	if (r) {	285	if (r) {
286	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	286	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
287	idx, reg);	287	idx, reg);
288	r100_cs_dump_packet(p, pkt);	288	radeon_cs_dump_packet(p, pkt);
289	return r;	289	return r;
290	}	290	}
Line 291...	Line 291...
291		291
292	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {	292	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
Line 356...	Line 356...
356	break;	356	break;
357	}	357	}
358	track->zb_dirty = true;	358	track->zb_dirty = true;
359	break;	359	break;
360	case RADEON_RB3D_ZPASS_ADDR:	360	case RADEON_RB3D_ZPASS_ADDR:
361	r = r100_cs_packet_next_reloc(p, &reloc);	361	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
362	if (r) {	362	if (r) {
363	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	363	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
364	idx, reg);	364	idx, reg);
365	r100_cs_dump_packet(p, pkt);	365	radeon_cs_dump_packet(p, pkt);
366	return r;	366	return r;
367	}	367	}
368	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);	368	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
369	break;	369	break;
370	case RADEON_PP_CNTL:	370	case RADEON_PP_CNTL:

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r200.c – Rev 2997 → 3764