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Rev 2005 Rev 2997
Line 23... Line 23...
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 *
 23 
 *
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 * Authors: Dave Airlie
 24 
 * Authors: Dave Airlie
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 *          Alex Deucher
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 *          Alex Deucher
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 *          Jerome Glisse
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 *          Jerome Glisse
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 */
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 */
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#include "drmP.h"
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#include
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#include "drm.h"
 - 
 
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#include "radeon_drm.h"
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#include
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#include "radeon_reg.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "radeon_asic.h"
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#endif
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#endif
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 85 
 
87 
int r200_copy_dma(struct radeon_device *rdev,
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int r200_copy_dma(struct radeon_device *rdev,
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		  uint64_t src_offset,
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		  uint64_t src_offset,
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		  uint64_t dst_offset,
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		  uint64_t dst_offset,
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		  unsigned num_pages,
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		  unsigned num_gpu_pages,
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		  struct radeon_fence *fence)
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		  struct radeon_fence **fence)
- 
 
 91 
{
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{
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	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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	uint32_t size;
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	uint32_t size;
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	uint32_t cur_size;
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	uint32_t cur_size;
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	int i, num_loops;
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	int i, num_loops;
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	int r = 0;
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	int r = 0;
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 97 
 
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	/* radeon pitch is /64 */
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	/* radeon pitch is /64 */
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	size = num_pages << PAGE_SHIFT;
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	size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
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	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
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	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
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	r = radeon_ring_lock(rdev, num_loops * 4 + 64);
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	r = radeon_ring_lock(rdev, ring, num_loops * 4 + 64);
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	if (r) {
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	if (r) {
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		DRM_ERROR("radeon: moving bo (%d).\n", r);
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		DRM_ERROR("radeon: moving bo (%d).\n", r);
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		return r;
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		return r;
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	}
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	}
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	/* Must wait for 2D idle & clean before DMA or hangs might happen */
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	/* Must wait for 2D idle & clean before DMA or hangs might happen */
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	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
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	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
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	radeon_ring_write(rdev, (1 << 16));
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	radeon_ring_write(ring, (1 << 16));
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	for (i = 0; i < num_loops; i++) {
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	for (i = 0; i < num_loops; i++) {
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		cur_size = size;
 110 
		cur_size = size;
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		if (cur_size > 0x1FFFFF) {
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		if (cur_size > 0x1FFFFF) {
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			cur_size = 0x1FFFFF;
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			cur_size = 0x1FFFFF;
113 
		}
 113 
		}
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		size -= cur_size;
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		size -= cur_size;
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		radeon_ring_write(rdev, PACKET0(0x720, 2));
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		radeon_ring_write(ring, PACKET0(0x720, 2));
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		radeon_ring_write(rdev, src_offset);
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		radeon_ring_write(ring, src_offset);
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		radeon_ring_write(rdev, dst_offset);
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		radeon_ring_write(ring, dst_offset);
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		radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
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		radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30));
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		src_offset += cur_size;
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		src_offset += cur_size;
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		dst_offset += cur_size;
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		dst_offset += cur_size;
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	}
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	}
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	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
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	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
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	radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
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	radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);
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	if (fence) {
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	if (fence) {
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		r = radeon_fence_emit(rdev, fence);
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		r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
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	}
 126 
	}
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	radeon_ring_unlock_commit(rdev);
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	radeon_ring_unlock_commit(rdev, ring);
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	return r;
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	return r;
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}
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}
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	int i;
 154 
	int i;
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	int face;
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	int face;
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	u32 tile_flags = 0;
 156 
	u32 tile_flags = 0;
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	u32 idx_value;
 157 
	u32 idx_value;
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 158 
 
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	ib = p->ib->ptr;
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	ib = p->ib.ptr;
160 
	track = (struct r100_cs_track *)p->track;
 160 
	track = (struct r100_cs_track *)p->track;
161 
	idx_value = radeon_get_ib_value(p, idx);
 161 
	idx_value = radeon_get_ib_value(p, idx);
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	switch (reg) {
 162 
	switch (reg) {
163 
	case RADEON_CRTC_GUI_TRIG_VLINE:
 163 
	case RADEON_CRTC_GUI_TRIG_VLINE:
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			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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				  idx, reg);
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				  idx, reg);
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			r100_cs_dump_packet(p, pkt);
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			r100_cs_dump_packet(p, pkt);
218 
			return r;
 218 
			return r;
219 
		}
 219 
		}
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		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
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 221 
			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
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				tile_flags |= R200_TXO_MACRO_TILE;
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 223 
			if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
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 224 
				tile_flags |= R200_TXO_MICRO_TILE;
- 
 
 225 
 
- 
 
 226 
			tmp = idx_value & ~(0x7 << 2);
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 227 
			tmp |= tile_flags;
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 228 
			ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
- 
 
 229 
		} else
220 
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 230 
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
221 
		track->textures[i].robj = reloc->robj;
 231 
		track->textures[i].robj = reloc->robj;
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		track->tex_dirty = true;
 232 
		track->tex_dirty = true;
223 
		break;
 233 
		break;
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	case R200_PP_CUBIC_OFFSET_F1_0:
 234 
	case R200_PP_CUBIC_OFFSET_F1_0:
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277 
				  idx, reg);
 287 
				  idx, reg);
278 
			r100_cs_dump_packet(p, pkt);
 288 
			r100_cs_dump_packet(p, pkt);
279 
			return r;
 289 
			return r;
280 
		}
 290 
		}
Line -... Line 291...
- 
 
 291 
 
281 
 
 292 
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
282 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 293 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
283 
			tile_flags |= RADEON_COLOR_TILE_ENABLE;
 294 
			tile_flags |= RADEON_COLOR_TILE_ENABLE;
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		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 295 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
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			tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
 296 
			tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
286 
 
 297 
 
287 
		tmp = idx_value & ~(0x7 << 16);
 298 
		tmp = idx_value & ~(0x7 << 16);
- 
 
 299 
		tmp |= tile_flags;
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 300 
		ib[idx] = tmp;
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288 
		tmp |= tile_flags;
 301 
		} else
289 
		ib[idx] = tmp;
 302 
			ib[idx] = idx_value;
290 
 
 303 
 
291 
		track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
 304 
		track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;