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| Rev 1179 | Rev 1221 | ||
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| Line 379... | Line 379... | ||
| 379 | #define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) |
379 | #define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) |
| 380 | #define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF |
380 | #define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF |
| 381 | #define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) |
381 | #define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) |
| 382 | #define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) |
382 | #define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) |
| 383 | #define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF |
383 | #define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF |
| - | 384 | #define R_000148_MC_FB_LOCATION 0x000148 |
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| - | 385 | #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) |
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| - | 386 | #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) |
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| - | 387 | #define C_000148_MC_FB_START 0xFFFF0000 |
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| - | 388 | #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) |
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| - | 389 | #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) |
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| - | 390 | #define C_000148_MC_FB_TOP 0x0000FFFF |
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| - | 391 | #define R_00014C_MC_AGP_LOCATION 0x00014C |
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| - | 392 | #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) |
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| - | 393 | #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) |
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| - | 394 | #define C_00014C_MC_AGP_START 0xFFFF0000 |
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| - | 395 | #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) |
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| - | 396 | #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) |
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| - | 397 | #define C_00014C_MC_AGP_TOP 0x0000FFFF |
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| - | 398 | #define R_000170_AGP_BASE 0x000170 |
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| - | 399 | #define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) |
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| - | 400 | #define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) |
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| - | 401 | #define C_000170_AGP_BASE_ADDR 0x00000000 |
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| 384 | #define R_00023C_DISPLAY_BASE_ADDR 0x00023C |
402 | #define R_00023C_DISPLAY_BASE_ADDR 0x00023C |
| 385 | #define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) |
403 | #define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) |
| 386 | #define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) |
404 | #define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) |
| 387 | #define C_00023C_DISPLAY_BASE_ADDR 0x00000000 |
405 | #define C_00023C_DISPLAY_BASE_ADDR 0x00000000 |
| 388 | #define R_000260_CUR_OFFSET 0x000260 |
406 | #define R_000260_CUR_OFFSET 0x000260 |
| Line 401... | Line 419... | ||
| 401 | #define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) |
419 | #define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) |
| 402 | #define C_000360_CUR2_OFFSET 0xF8000000 |
420 | #define C_000360_CUR2_OFFSET 0xF8000000 |
| 403 | #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) |
421 | #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) |
| 404 | #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) |
422 | #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) |
| 405 | #define C_000360_CUR2_LOCK 0x7FFFFFFF |
423 | #define C_000360_CUR2_LOCK 0x7FFFFFFF |
| 406 | #define R_0003C0_GENMO_WT 0x0003C0 |
424 | #define R_0003C2_GENMO_WT 0x0003C0 |
| 407 | #define S_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) |
425 | #define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) |
| 408 | #define G_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) |
426 | #define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) |
| 409 | #define C_0003C0_GENMO_MONO_ADDRESS_B 0xFFFFFFFE |
427 | #define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE |
| 410 | #define S_0003C0_VGA_RAM_EN(x) (((x) & 0x1) << 1) |
428 | #define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1) |
| 411 | #define G_0003C0_VGA_RAM_EN(x) (((x) >> 1) & 0x1) |
429 | #define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1) |
| 412 | #define C_0003C0_VGA_RAM_EN 0xFFFFFFFD |
430 | #define C_0003C2_VGA_RAM_EN 0xFD |
| 413 | #define S_0003C0_VGA_CKSEL(x) (((x) & 0x3) << 2) |
431 | #define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2) |
| 414 | #define G_0003C0_VGA_CKSEL(x) (((x) >> 2) & 0x3) |
432 | #define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3) |
| 415 | #define C_0003C0_VGA_CKSEL 0xFFFFFFF3 |
433 | #define C_0003C2_VGA_CKSEL 0xF3 |
| 416 | #define S_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) |
434 | #define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) |
| 417 | #define G_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) |
435 | #define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) |
| 418 | #define C_0003C0_ODD_EVEN_MD_PGSEL 0xFFFFFFDF |
436 | #define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF |
| 419 | #define S_0003C0_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) |
437 | #define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) |
| 420 | #define G_0003C0_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) |
438 | #define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) |
| 421 | #define C_0003C0_VGA_HSYNC_POL 0xFFFFFFBF |
439 | #define C_0003C2_VGA_HSYNC_POL 0xBF |
| 422 | #define S_0003C0_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) |
440 | #define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) |
| 423 | #define G_0003C0_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) |
441 | #define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) |
| 424 | #define C_0003C0_VGA_VSYNC_POL 0xFFFFFF7F |
442 | #define C_0003C2_VGA_VSYNC_POL 0x7F |
| 425 | #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 |
443 | #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 |
| 426 | #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) |
444 | #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) |
| 427 | #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) |
445 | #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) |
| 428 | #define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE |
446 | #define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE |
| 429 | #define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) |
447 | #define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) |
| Line 543... | Line 561... | ||
| 543 | #define C_000770_SCRATCH_SWAP 0xFFFCFFFF |
561 | #define C_000770_SCRATCH_SWAP 0xFFFCFFFF |
| 544 | #define R_000774_SCRATCH_ADDR 0x000774 |
562 | #define R_000774_SCRATCH_ADDR 0x000774 |
| 545 | #define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) |
563 | #define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) |
| 546 | #define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) |
564 | #define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) |
| 547 | #define C_000774_SCRATCH_ADDR 0x0000001F |
565 | #define C_000774_SCRATCH_ADDR 0x0000001F |
| - | 566 | #define R_0007C0_CP_STAT 0x0007C0 |
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| - | 567 | #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) |
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| - | 568 | #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) |
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| - | 569 | #define C_0007C0_MRU_BUSY 0xFFFFFFFE |
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| - | 570 | #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) |
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| - | 571 | #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) |
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| - | 572 | #define C_0007C0_MWU_BUSY 0xFFFFFFFD |
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| - | 573 | #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) |
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| - | 574 | #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) |
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| - | 575 | #define C_0007C0_RSIU_BUSY 0xFFFFFFFB |
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| - | 576 | #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) |
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| - | 577 | #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) |
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| - | 578 | #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 |
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| - | 579 | #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) |
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| - | 580 | #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) |
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| - | 581 | #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF |
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| - | 582 | #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) |
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| - | 583 | #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) |
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| - | 584 | #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF |
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| - | 585 | #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) |
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| - | 586 | #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) |
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| - | 587 | #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF |
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| - | 588 | #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) |
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| - | 589 | #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) |
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| - | 590 | #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF |
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| - | 591 | #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) |
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| - | 592 | #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) |
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| - | 593 | #define C_0007C0_CSI_BUSY 0xFFFFDFFF |
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| - | 594 | #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) |
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| - | 595 | #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) |
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| - | 596 | #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF |
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| - | 597 | #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) |
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| - | 598 | #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) |
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| - | 599 | #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF |
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| - | 600 | #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) |
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| - | 601 | #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) |
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| - | 602 | #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF |
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| - | 603 | #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) |
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| - | 604 | #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) |
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| - | 605 | #define C_0007C0_CP_BUSY 0x7FFFFFFF |
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| 548 | #define R_000E40_RBBM_STATUS 0x000E40 |
606 | #define R_000E40_RBBM_STATUS 0x000E40 |
| 549 | #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) |
607 | #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) |
| 550 | #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) |
608 | #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) |
| 551 | #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 |
609 | #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 |
| 552 | #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) |
610 | #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) |
| Line 602... | Line 660... | ||
| 602 | #define C_000E40_PB_BUSY 0xFEFFFFFF |
660 | #define C_000E40_PB_BUSY 0xFEFFFFFF |
| 603 | #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) |
661 | #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) |
| 604 | #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) |
662 | #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) |
| 605 | #define C_000E40_GUI_ACTIVE 0x7FFFFFFF |
663 | #define C_000E40_GUI_ACTIVE 0x7FFFFFFF |
| Line -... | Line 664... | ||
| - | 664 | ||
| - | 665 | ||
| - | 666 | #define R_00000D_SCLK_CNTL 0x00000D |
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| - | 667 | #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) |
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| - | 668 | #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) |
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| - | 669 | #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 |
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| - | 670 | #define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8) |
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| - | 671 | #define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7) |
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| - | 672 | #define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF |
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| - | 673 | #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) |
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| - | 674 | #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) |
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| - | 675 | #define C_00000D_FORCE_CP 0xFFFEFFFF |
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| - | 676 | #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) |
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| - | 677 | #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) |
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| - | 678 | #define C_00000D_FORCE_HDP 0xFFFDFFFF |
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| - | 679 | #define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18) |
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| - | 680 | #define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1) |
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| - | 681 | #define C_00000D_FORCE_DISP 0xFFFBFFFF |
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| - | 682 | #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) |
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| - | 683 | #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) |
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| - | 684 | #define C_00000D_FORCE_TOP 0xFFF7FFFF |
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| - | 685 | #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) |
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| - | 686 | #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) |
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| - | 687 | #define C_00000D_FORCE_E2 0xFFEFFFFF |
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| - | 688 | #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) |
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| - | 689 | #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) |
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| - | 690 | #define C_00000D_FORCE_SE 0xFFDFFFFF |
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| - | 691 | #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) |
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| - | 692 | #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) |
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| - | 693 | #define C_00000D_FORCE_IDCT 0xFFBFFFFF |
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| - | 694 | #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) |
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| - | 695 | #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) |
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| - | 696 | #define C_00000D_FORCE_VIP 0xFF7FFFFF |
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| - | 697 | #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) |
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| - | 698 | #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) |
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| - | 699 | #define C_00000D_FORCE_RE 0xFEFFFFFF |
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| - | 700 | #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) |
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| - | 701 | #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) |
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| - | 702 | #define C_00000D_FORCE_PB 0xFDFFFFFF |
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| - | 703 | #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) |
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| - | 704 | #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) |
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| - | 705 | #define C_00000D_FORCE_TAM 0xFBFFFFFF |
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| - | 706 | #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) |
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| - | 707 | #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) |
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| - | 708 | #define C_00000D_FORCE_TDM 0xF7FFFFFF |
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| - | 709 | #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) |
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| - | 710 | #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) |
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| - | 711 | #define C_00000D_FORCE_RB 0xEFFFFFFF |
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| - | 712 | ||
| 606 | 713 | ||