WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r100.c



	/* Unused on older asics, since we don't have semaphores or multiple rings */
	BUG();
	return false;
}

 
struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
		   uint64_t src_offset,
		   uint64_t dst_offset,
		   unsigned num_gpu_pages,
				    struct reservation_object *resv)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
	struct radeon_fence *fence;
	uint32_t cur_pages;
	uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
	uint32_t pitch;
	uint32_t stride_pixels;

	/* Ask for enough room for blit + flush + fence */
	ndw = 64 + (10 * num_loops);
	r = radeon_ring_lock(rdev, ring, ndw);
	if (r) {
		DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		return ERR_PTR(-EINVAL);
	}
	while (num_gpu_pages > 0) {
		cur_pages = num_gpu_pages;
		if (cur_pages > 8191) {
			cur_pages = 8191;

	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
	radeon_ring_write(ring,
			  RADEON_WAIT_2D_IDLECLEAN |
			  RADEON_WAIT_HOST_IDLECLEAN |
			  RADEON_WAIT_DMA_GUI_IDLE);
	r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
	if (r) {
		radeon_ring_unlock_undo(rdev, ring);
		return ERR_PTR(r);
	}
	radeon_ring_unlock_commit(rdev, ring, false);
	return fence;
}

 
static int r100_cp_wait_for_idle(struct radeon_device *rdev)
{

			    unsigned reg)
{
	int r;
	u32 tile_flags = 0;
	u32 tmp;
	struct radeon_bo_list *reloc;
	u32 value;

 
	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
	if (r) {

int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
			     struct radeon_cs_packet *pkt,
			     int idx)
{
	unsigned c, i;
	struct radeon_bo_list *reloc;
	struct r100_cs_track *track;
	int r = 0;
	volatile uint32_t *ib;
	u32 idx_value;

 
static int r100_packet0_check(struct radeon_cs_parser *p,
			      struct radeon_cs_packet *pkt,
			      unsigned idx, unsigned reg)
{
	struct radeon_bo_list *reloc;
	struct r100_cs_track *track;
	volatile uint32_t *ib;
	uint32_t tmp;
	int r;

}

 
static int r100_packet3_check(struct radeon_cs_parser *p,
			      struct radeon_cs_packet *pkt)
{
	struct radeon_bo_list *reloc;
	struct r100_cs_track *track;
	unsigned idx;
	volatile uint32_t *ib;

					  pkt.type);
				return -EINVAL;
		}
		if (r)
			return r;
	} while (p->idx < p->chunk_ib->length_dw);
	return 0;
}

 
static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)

	struct drm_display_mode *mode1 = NULL;
	struct drm_display_mode *mode2 = NULL;
	uint32_t pixel_bytes1 = 0;
	uint32_t pixel_bytes2 = 0;

 
	if (!rdev->mode_info.mode_config_initialized)
		return;
 

	radeon_update_display_priority(rdev);
 
	if (rdev->mode_info.crtcs[0]->base.enabled) {

Rev 5139	Rev 5271
Line 867...	Line 867...
867	/* Unused on older asics, since we don't have semaphores or multiple rings */	867	/* Unused on older asics, since we don't have semaphores or multiple rings */
868	BUG();	868	BUG();
869	return false;	869	return false;
870	}	870	}
Line 871...	Line 871...
871		871
872	int r100_copy_blit(struct radeon_device *rdev,	872	struct radeon_fence r100_copy_blit(struct radeon_device rdev,
873	uint64_t src_offset,	873	uint64_t src_offset,
874	uint64_t dst_offset,	874	uint64_t dst_offset,
875	unsigned num_gpu_pages,	875	unsigned num_gpu_pages,
876	struct radeon_fence **fence)	876	struct reservation_object *resv)
877	{	877	{
-		878	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
878	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	879	struct radeon_fence *fence;
879	uint32_t cur_pages;	880	uint32_t cur_pages;
880	uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;	881	uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
881	uint32_t pitch;	882	uint32_t pitch;
882	uint32_t stride_pixels;	883	uint32_t stride_pixels;
Line 894...	Line 895...
894	/* Ask for enough room for blit + flush + fence */	895	/* Ask for enough room for blit + flush + fence */
895	ndw = 64 + (10 * num_loops);	896	ndw = 64 + (10 * num_loops);
896	r = radeon_ring_lock(rdev, ring, ndw);	897	r = radeon_ring_lock(rdev, ring, ndw);
897	if (r) {	898	if (r) {
898	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);	899	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
899	return -EINVAL;	900	return ERR_PTR(-EINVAL);
900	}	901	}
901	while (num_gpu_pages > 0) {	902	while (num_gpu_pages > 0) {
902	cur_pages = num_gpu_pages;	903	cur_pages = num_gpu_pages;
903	if (cur_pages > 8191) {	904	if (cur_pages > 8191) {
904	cur_pages = 8191;	905	cur_pages = 8191;
Line 934...	Line 935...
934	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));	935	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
935	radeon_ring_write(ring,	936	radeon_ring_write(ring,
936	RADEON_WAIT_2D_IDLECLEAN \|	937	RADEON_WAIT_2D_IDLECLEAN \|
937	RADEON_WAIT_HOST_IDLECLEAN \|	938	RADEON_WAIT_HOST_IDLECLEAN \|
938	RADEON_WAIT_DMA_GUI_IDLE);	939	RADEON_WAIT_DMA_GUI_IDLE);
-		940	r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
939	if (fence) {	941	if (r) {
940	r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);	942	radeon_ring_unlock_undo(rdev, ring);
-		943	return ERR_PTR(r);
941	}	944	}
942	radeon_ring_unlock_commit(rdev, ring, false);	945	radeon_ring_unlock_commit(rdev, ring, false);
943	return r;	946	return fence;
944	}	947	}
Line 945...	Line 948...
945		948
946	static int r100_cp_wait_for_idle(struct radeon_device *rdev)	949	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
947	{	950	{
Line 1245...	Line 1248...
1245	unsigned reg)	1248	unsigned reg)
1246	{	1249	{
1247	int r;	1250	int r;
1248	u32 tile_flags = 0;	1251	u32 tile_flags = 0;
1249	u32 tmp;	1252	u32 tmp;
1250	struct radeon_cs_reloc *reloc;	1253	struct radeon_bo_list *reloc;
1251	u32 value;	1254	u32 value;
Line 1252...	Line 1255...
1252		1255
1253	r = radeon_cs_packet_next_reloc(p, &reloc, 0);	1256	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1254	if (r) {	1257	if (r) {
Line 1284...	Line 1287...
1284	int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,	1287	int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1285	struct radeon_cs_packet *pkt,	1288	struct radeon_cs_packet *pkt,
1286	int idx)	1289	int idx)
1287	{	1290	{
1288	unsigned c, i;	1291	unsigned c, i;
1289	struct radeon_cs_reloc *reloc;	1292	struct radeon_bo_list *reloc;
1290	struct r100_cs_track *track;	1293	struct r100_cs_track *track;
1291	int r = 0;	1294	int r = 0;
1292	volatile uint32_t *ib;	1295	volatile uint32_t *ib;
1293	u32 idx_value;	1296	u32 idx_value;
Line 1533...	Line 1536...
1533		1536
1534	static int r100_packet0_check(struct radeon_cs_parser *p,	1537	static int r100_packet0_check(struct radeon_cs_parser *p,
1535	struct radeon_cs_packet *pkt,	1538	struct radeon_cs_packet *pkt,
1536	unsigned idx, unsigned reg)	1539	unsigned idx, unsigned reg)
1537	{	1540	{
1538	struct radeon_cs_reloc *reloc;	1541	struct radeon_bo_list *reloc;
1539	struct r100_cs_track *track;	1542	struct r100_cs_track *track;
1540	volatile uint32_t *ib;	1543	volatile uint32_t *ib;
1541	uint32_t tmp;	1544	uint32_t tmp;
1542	int r;	1545	int r;
Line 1892...	Line 1895...
1892	}	1895	}
Line 1893...	Line 1896...
1893		1896
1894	static int r100_packet3_check(struct radeon_cs_parser *p,	1897	static int r100_packet3_check(struct radeon_cs_parser *p,
1895	struct radeon_cs_packet *pkt)	1898	struct radeon_cs_packet *pkt)
1896	{	1899	{
1897	struct radeon_cs_reloc *reloc;	1900	struct radeon_bo_list *reloc;
1898	struct r100_cs_track *track;	1901	struct r100_cs_track *track;
1899	unsigned idx;	1902	unsigned idx;
1900	volatile uint32_t *ib;	1903	volatile uint32_t *ib;
Line 2052...	Line 2055...
2052	pkt.type);	2055	pkt.type);
2053	return -EINVAL;	2056	return -EINVAL;
2054	}	2057	}
2055	if (r)	2058	if (r)
2056	return r;	2059	return r;
2057	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);	2060	} while (p->idx < p->chunk_ib->length_dw);
2058	return 0;	2061	return 0;
2059	}	2062	}
Line 2060...	Line 2063...
2060		2063
2061	static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)	2064	static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
Line 3198...	Line 3201...
3198	struct drm_display_mode *mode1 = NULL;	3201	struct drm_display_mode *mode1 = NULL;
3199	struct drm_display_mode *mode2 = NULL;	3202	struct drm_display_mode *mode2 = NULL;
3200	uint32_t pixel_bytes1 = 0;	3203	uint32_t pixel_bytes1 = 0;
3201	uint32_t pixel_bytes2 = 0;	3204	uint32_t pixel_bytes2 = 0;
Line -...	Line 3205...
-		3205
-		3206	if (!rdev->mode_info.mode_config_initialized)
-		3207	return;
3202		3208
Line 3203...	Line 3209...
3203	radeon_update_display_priority(rdev);	3209	radeon_update_display_priority(rdev);
3204		3210
3205	if (rdev->mode_info.crtcs[0]->base.enabled) {	3211	if (rdev->mode_info.crtcs[0]->base.enabled) {

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r100.c – Rev 5139 → 5271