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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include "radeon_reg.h" |
32 | #include "radeon_reg.h" |
33 | #include "radeon.h" |
33 | #include "radeon.h" |
34 | #include "radeon_asic.h" |
34 | #include "radeon_asic.h" |
35 | #include "r100d.h" |
35 | #include "r100d.h" |
36 | #include "rs100d.h" |
36 | #include "rs100d.h" |
37 | #include "rv200d.h" |
37 | #include "rv200d.h" |
38 | #include "rv250d.h" |
38 | #include "rv250d.h" |
39 | #include "atom.h" |
39 | #include "atom.h" |
40 | 40 | ||
41 | #include |
41 | #include |
42 | #include |
42 | #include |
43 | 43 | ||
44 | #include "r100_reg_safe.h" |
44 | #include "r100_reg_safe.h" |
45 | #include "rn50_reg_safe.h" |
45 | #include "rn50_reg_safe.h" |
46 | 46 | ||
47 | /* Firmware Names */ |
47 | /* Firmware Names */ |
48 | #define FIRMWARE_R100 "radeon/R100_cp.bin" |
48 | #define FIRMWARE_R100 "radeon/R100_cp.bin" |
49 | #define FIRMWARE_R200 "radeon/R200_cp.bin" |
49 | #define FIRMWARE_R200 "radeon/R200_cp.bin" |
50 | #define FIRMWARE_R300 "radeon/R300_cp.bin" |
50 | #define FIRMWARE_R300 "radeon/R300_cp.bin" |
51 | #define FIRMWARE_R420 "radeon/R420_cp.bin" |
51 | #define FIRMWARE_R420 "radeon/R420_cp.bin" |
52 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" |
52 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" |
53 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" |
53 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" |
54 | #define FIRMWARE_R520 "radeon/R520_cp.bin" |
54 | #define FIRMWARE_R520 "radeon/R520_cp.bin" |
55 | 55 | ||
56 | MODULE_FIRMWARE(FIRMWARE_R100); |
56 | MODULE_FIRMWARE(FIRMWARE_R100); |
57 | MODULE_FIRMWARE(FIRMWARE_R200); |
57 | MODULE_FIRMWARE(FIRMWARE_R200); |
58 | MODULE_FIRMWARE(FIRMWARE_R300); |
58 | MODULE_FIRMWARE(FIRMWARE_R300); |
59 | MODULE_FIRMWARE(FIRMWARE_R420); |
59 | MODULE_FIRMWARE(FIRMWARE_R420); |
60 | MODULE_FIRMWARE(FIRMWARE_RS690); |
60 | MODULE_FIRMWARE(FIRMWARE_RS690); |
61 | MODULE_FIRMWARE(FIRMWARE_RS600); |
61 | MODULE_FIRMWARE(FIRMWARE_RS600); |
62 | MODULE_FIRMWARE(FIRMWARE_R520); |
62 | MODULE_FIRMWARE(FIRMWARE_R520); |
63 | 63 | ||
64 | 64 | ||
65 | /* This files gather functions specifics to: |
65 | /* This files gather functions specifics to: |
66 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
66 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
67 | * and others in some cases. |
67 | * and others in some cases. |
68 | */ |
68 | */ |
69 | 69 | ||
70 | /** |
70 | /** |
71 | * r100_wait_for_vblank - vblank wait asic callback. |
71 | * r100_wait_for_vblank - vblank wait asic callback. |
72 | * |
72 | * |
73 | * @rdev: radeon_device pointer |
73 | * @rdev: radeon_device pointer |
74 | * @crtc: crtc to wait for vblank on |
74 | * @crtc: crtc to wait for vblank on |
75 | * |
75 | * |
76 | * Wait for vblank on the requested crtc (r1xx-r4xx). |
76 | * Wait for vblank on the requested crtc (r1xx-r4xx). |
77 | */ |
77 | */ |
78 | void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) |
78 | void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) |
79 | { |
79 | { |
80 | int i; |
80 | int i; |
81 | 81 | ||
82 | if (crtc >= rdev->num_crtc) |
82 | if (crtc >= rdev->num_crtc) |
83 | return; |
83 | return; |
84 | 84 | ||
85 | if (crtc == 0) { |
85 | if (crtc == 0) { |
86 | if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) { |
86 | if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) { |
87 | for (i = 0; i < rdev->usec_timeout; i++) { |
87 | for (i = 0; i < rdev->usec_timeout; i++) { |
88 | if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)) |
88 | if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)) |
89 | break; |
89 | break; |
90 | udelay(1); |
90 | udelay(1); |
91 | } |
91 | } |
92 | for (i = 0; i < rdev->usec_timeout; i++) { |
92 | for (i = 0; i < rdev->usec_timeout; i++) { |
93 | if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) |
93 | if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) |
94 | break; |
94 | break; |
95 | udelay(1); |
95 | udelay(1); |
96 | } |
96 | } |
97 | } |
97 | } |
98 | } else { |
98 | } else { |
99 | if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) { |
99 | if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) { |
100 | for (i = 0; i < rdev->usec_timeout; i++) { |
100 | for (i = 0; i < rdev->usec_timeout; i++) { |
101 | if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)) |
101 | if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)) |
102 | break; |
102 | break; |
103 | udelay(1); |
103 | udelay(1); |
104 | } |
104 | } |
105 | for (i = 0; i < rdev->usec_timeout; i++) { |
105 | for (i = 0; i < rdev->usec_timeout; i++) { |
106 | if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) |
106 | if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) |
107 | break; |
107 | break; |
108 | udelay(1); |
108 | udelay(1); |
109 | } |
109 | } |
110 | } |
110 | } |
111 | } |
111 | } |
112 | } |
112 | } |
113 | u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
113 | u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
114 | { |
114 | { |
115 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
115 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
116 | u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; |
116 | u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; |
117 | int i; |
117 | int i; |
118 | 118 | ||
119 | /* Lock the graphics update lock */ |
119 | /* Lock the graphics update lock */ |
120 | /* update the scanout addresses */ |
120 | /* update the scanout addresses */ |
121 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); |
121 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); |
122 | 122 | ||
123 | /* Wait for update_pending to go high. */ |
123 | /* Wait for update_pending to go high. */ |
124 | for (i = 0; i < rdev->usec_timeout; i++) { |
124 | for (i = 0; i < rdev->usec_timeout; i++) { |
125 | if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) |
125 | if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) |
126 | break; |
126 | break; |
127 | udelay(1); |
127 | udelay(1); |
128 | } |
128 | } |
129 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
129 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
130 | 130 | ||
131 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
131 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
132 | tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; |
132 | tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; |
133 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); |
133 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); |
134 | 134 | ||
135 | /* Return current update_pending status: */ |
135 | /* Return current update_pending status: */ |
136 | return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; |
136 | return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; |
137 | } |
137 | } |
138 | bool r100_gui_idle(struct radeon_device *rdev) |
138 | bool r100_gui_idle(struct radeon_device *rdev) |
139 | { |
139 | { |
140 | if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) |
140 | if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) |
141 | return false; |
141 | return false; |
142 | else |
142 | else |
143 | return true; |
143 | return true; |
144 | } |
144 | } |
145 | 145 | ||
146 | /* hpd for digital panel detect/disconnect */ |
146 | /* hpd for digital panel detect/disconnect */ |
147 | /** |
147 | /** |
148 | * r100_hpd_sense - hpd sense callback. |
148 | * r100_hpd_sense - hpd sense callback. |
149 | * |
149 | * |
150 | * @rdev: radeon_device pointer |
150 | * @rdev: radeon_device pointer |
151 | * @hpd: hpd (hotplug detect) pin |
151 | * @hpd: hpd (hotplug detect) pin |
152 | * |
152 | * |
153 | * Checks if a digital monitor is connected (r1xx-r4xx). |
153 | * Checks if a digital monitor is connected (r1xx-r4xx). |
154 | * Returns true if connected, false if not connected. |
154 | * Returns true if connected, false if not connected. |
155 | */ |
155 | */ |
156 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
156 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
157 | { |
157 | { |
158 | bool connected = false; |
158 | bool connected = false; |
159 | 159 | ||
160 | switch (hpd) { |
160 | switch (hpd) { |
161 | case RADEON_HPD_1: |
161 | case RADEON_HPD_1: |
162 | if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) |
162 | if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) |
163 | connected = true; |
163 | connected = true; |
164 | break; |
164 | break; |
165 | case RADEON_HPD_2: |
165 | case RADEON_HPD_2: |
166 | if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) |
166 | if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) |
167 | connected = true; |
167 | connected = true; |
168 | break; |
168 | break; |
169 | default: |
169 | default: |
170 | break; |
170 | break; |
171 | } |
171 | } |
172 | return connected; |
172 | return connected; |
173 | } |
173 | } |
174 | 174 | ||
175 | /** |
175 | /** |
176 | * r100_hpd_set_polarity - hpd set polarity callback. |
176 | * r100_hpd_set_polarity - hpd set polarity callback. |
177 | * |
177 | * |
178 | * @rdev: radeon_device pointer |
178 | * @rdev: radeon_device pointer |
179 | * @hpd: hpd (hotplug detect) pin |
179 | * @hpd: hpd (hotplug detect) pin |
180 | * |
180 | * |
181 | * Set the polarity of the hpd pin (r1xx-r4xx). |
181 | * Set the polarity of the hpd pin (r1xx-r4xx). |
182 | */ |
182 | */ |
183 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
183 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
184 | enum radeon_hpd_id hpd) |
184 | enum radeon_hpd_id hpd) |
185 | { |
185 | { |
186 | u32 tmp; |
186 | u32 tmp; |
187 | bool connected = r100_hpd_sense(rdev, hpd); |
187 | bool connected = r100_hpd_sense(rdev, hpd); |
188 | 188 | ||
189 | switch (hpd) { |
189 | switch (hpd) { |
190 | case RADEON_HPD_1: |
190 | case RADEON_HPD_1: |
191 | tmp = RREG32(RADEON_FP_GEN_CNTL); |
191 | tmp = RREG32(RADEON_FP_GEN_CNTL); |
192 | if (connected) |
192 | if (connected) |
193 | tmp &= ~RADEON_FP_DETECT_INT_POL; |
193 | tmp &= ~RADEON_FP_DETECT_INT_POL; |
194 | else |
194 | else |
195 | tmp |= RADEON_FP_DETECT_INT_POL; |
195 | tmp |= RADEON_FP_DETECT_INT_POL; |
196 | WREG32(RADEON_FP_GEN_CNTL, tmp); |
196 | WREG32(RADEON_FP_GEN_CNTL, tmp); |
197 | break; |
197 | break; |
198 | case RADEON_HPD_2: |
198 | case RADEON_HPD_2: |
199 | tmp = RREG32(RADEON_FP2_GEN_CNTL); |
199 | tmp = RREG32(RADEON_FP2_GEN_CNTL); |
200 | if (connected) |
200 | if (connected) |
201 | tmp &= ~RADEON_FP2_DETECT_INT_POL; |
201 | tmp &= ~RADEON_FP2_DETECT_INT_POL; |
202 | else |
202 | else |
203 | tmp |= RADEON_FP2_DETECT_INT_POL; |
203 | tmp |= RADEON_FP2_DETECT_INT_POL; |
204 | WREG32(RADEON_FP2_GEN_CNTL, tmp); |
204 | WREG32(RADEON_FP2_GEN_CNTL, tmp); |
205 | break; |
205 | break; |
206 | default: |
206 | default: |
207 | break; |
207 | break; |
208 | } |
208 | } |
209 | } |
209 | } |
210 | 210 | ||
211 | /** |
211 | /** |
212 | * r100_hpd_init - hpd setup callback. |
212 | * r100_hpd_init - hpd setup callback. |
213 | * |
213 | * |
214 | * @rdev: radeon_device pointer |
214 | * @rdev: radeon_device pointer |
215 | * |
215 | * |
216 | * Setup the hpd pins used by the card (r1xx-r4xx). |
216 | * Setup the hpd pins used by the card (r1xx-r4xx). |
217 | * Set the polarity, and enable the hpd interrupts. |
217 | * Set the polarity, and enable the hpd interrupts. |
218 | */ |
218 | */ |
219 | void r100_hpd_init(struct radeon_device *rdev) |
219 | void r100_hpd_init(struct radeon_device *rdev) |
220 | { |
220 | { |
221 | struct drm_device *dev = rdev->ddev; |
221 | struct drm_device *dev = rdev->ddev; |
222 | struct drm_connector *connector; |
222 | struct drm_connector *connector; |
223 | unsigned enable = 0; |
223 | unsigned enable = 0; |
224 | 224 | ||
225 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
225 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
226 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
226 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
227 | enable |= 1 << radeon_connector->hpd.hpd; |
227 | enable |= 1 << radeon_connector->hpd.hpd; |
228 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
228 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
229 | } |
229 | } |
230 | // radeon_irq_kms_enable_hpd(rdev, enable); |
230 | // radeon_irq_kms_enable_hpd(rdev, enable); |
231 | } |
231 | } |
232 | 232 | ||
233 | /** |
233 | /** |
234 | * r100_hpd_fini - hpd tear down callback. |
234 | * r100_hpd_fini - hpd tear down callback. |
235 | * |
235 | * |
236 | * @rdev: radeon_device pointer |
236 | * @rdev: radeon_device pointer |
237 | * |
237 | * |
238 | * Tear down the hpd pins used by the card (r1xx-r4xx). |
238 | * Tear down the hpd pins used by the card (r1xx-r4xx). |
239 | * Disable the hpd interrupts. |
239 | * Disable the hpd interrupts. |
240 | */ |
240 | */ |
241 | void r100_hpd_fini(struct radeon_device *rdev) |
241 | void r100_hpd_fini(struct radeon_device *rdev) |
242 | { |
242 | { |
243 | struct drm_device *dev = rdev->ddev; |
243 | struct drm_device *dev = rdev->ddev; |
244 | struct drm_connector *connector; |
244 | struct drm_connector *connector; |
245 | unsigned disable = 0; |
245 | unsigned disable = 0; |
246 | 246 | ||
247 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
247 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
248 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
248 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
249 | disable |= 1 << radeon_connector->hpd.hpd; |
249 | disable |= 1 << radeon_connector->hpd.hpd; |
250 | } |
250 | } |
251 | // radeon_irq_kms_disable_hpd(rdev, disable); |
251 | // radeon_irq_kms_disable_hpd(rdev, disable); |
252 | } |
252 | } |
253 | 253 | ||
254 | /* |
254 | /* |
255 | * PCI GART |
255 | * PCI GART |
256 | */ |
256 | */ |
257 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev) |
257 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev) |
258 | { |
258 | { |
259 | /* TODO: can we do somethings here ? */ |
259 | /* TODO: can we do somethings here ? */ |
260 | /* It seems hw only cache one entry so we should discard this |
260 | /* It seems hw only cache one entry so we should discard this |
261 | * entry otherwise if first GPU GART read hit this entry it |
261 | * entry otherwise if first GPU GART read hit this entry it |
262 | * could end up in wrong address. */ |
262 | * could end up in wrong address. */ |
263 | } |
263 | } |
264 | 264 | ||
265 | int r100_pci_gart_init(struct radeon_device *rdev) |
265 | int r100_pci_gart_init(struct radeon_device *rdev) |
266 | { |
266 | { |
267 | int r; |
267 | int r; |
268 | 268 | ||
269 | if (rdev->gart.ptr) { |
269 | if (rdev->gart.ptr) { |
270 | WARN(1, "R100 PCI GART already initialized\n"); |
270 | WARN(1, "R100 PCI GART already initialized\n"); |
271 | return 0; |
271 | return 0; |
272 | } |
272 | } |
273 | /* Initialize common gart structure */ |
273 | /* Initialize common gart structure */ |
274 | r = radeon_gart_init(rdev); |
274 | r = radeon_gart_init(rdev); |
275 | if (r) |
275 | if (r) |
276 | return r; |
276 | return r; |
277 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
277 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
278 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
278 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
279 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
279 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
280 | return radeon_gart_table_ram_alloc(rdev); |
280 | return radeon_gart_table_ram_alloc(rdev); |
281 | } |
281 | } |
282 | 282 | ||
283 | int r100_pci_gart_enable(struct radeon_device *rdev) |
283 | int r100_pci_gart_enable(struct radeon_device *rdev) |
284 | { |
284 | { |
285 | uint32_t tmp; |
285 | uint32_t tmp; |
286 | 286 | ||
287 | radeon_gart_restore(rdev); |
287 | radeon_gart_restore(rdev); |
288 | /* discard memory request outside of configured range */ |
288 | /* discard memory request outside of configured range */ |
289 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
289 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
290 | WREG32(RADEON_AIC_CNTL, tmp); |
290 | WREG32(RADEON_AIC_CNTL, tmp); |
291 | /* set address range for PCI address translate */ |
291 | /* set address range for PCI address translate */ |
292 | WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); |
292 | WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); |
293 | WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); |
293 | WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); |
294 | /* set PCI GART page-table base address */ |
294 | /* set PCI GART page-table base address */ |
295 | WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); |
295 | WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); |
296 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; |
296 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; |
297 | WREG32(RADEON_AIC_CNTL, tmp); |
297 | WREG32(RADEON_AIC_CNTL, tmp); |
298 | r100_pci_gart_tlb_flush(rdev); |
298 | r100_pci_gart_tlb_flush(rdev); |
299 | DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", |
299 | DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", |
300 | (unsigned)(rdev->mc.gtt_size >> 20), |
300 | (unsigned)(rdev->mc.gtt_size >> 20), |
301 | (unsigned long long)rdev->gart.table_addr); |
301 | (unsigned long long)rdev->gart.table_addr); |
302 | rdev->gart.ready = true; |
302 | rdev->gart.ready = true; |
303 | return 0; |
303 | return 0; |
304 | } |
304 | } |
305 | 305 | ||
306 | void r100_pci_gart_disable(struct radeon_device *rdev) |
306 | void r100_pci_gart_disable(struct radeon_device *rdev) |
307 | { |
307 | { |
308 | uint32_t tmp; |
308 | uint32_t tmp; |
309 | 309 | ||
310 | /* discard memory request outside of configured range */ |
310 | /* discard memory request outside of configured range */ |
311 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
311 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
312 | WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
312 | WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
313 | WREG32(RADEON_AIC_LO_ADDR, 0); |
313 | WREG32(RADEON_AIC_LO_ADDR, 0); |
314 | WREG32(RADEON_AIC_HI_ADDR, 0); |
314 | WREG32(RADEON_AIC_HI_ADDR, 0); |
315 | } |
315 | } |
316 | 316 | ||
317 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
317 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
318 | { |
318 | { |
319 | u32 *gtt = rdev->gart.ptr; |
319 | u32 *gtt = rdev->gart.ptr; |
320 | 320 | ||
321 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
321 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
322 | return -EINVAL; |
322 | return -EINVAL; |
323 | } |
323 | } |
324 | gtt[i] = cpu_to_le32(lower_32_bits(addr)); |
324 | gtt[i] = cpu_to_le32(lower_32_bits(addr)); |
325 | return 0; |
325 | return 0; |
326 | } |
326 | } |
327 | 327 | ||
328 | void r100_pci_gart_fini(struct radeon_device *rdev) |
328 | void r100_pci_gart_fini(struct radeon_device *rdev) |
329 | { |
329 | { |
330 | radeon_gart_fini(rdev); |
330 | radeon_gart_fini(rdev); |
331 | r100_pci_gart_disable(rdev); |
331 | r100_pci_gart_disable(rdev); |
332 | radeon_gart_table_ram_free(rdev); |
332 | radeon_gart_table_ram_free(rdev); |
333 | } |
333 | } |
334 | 334 | ||
335 | int r100_irq_set(struct radeon_device *rdev) |
335 | int r100_irq_set(struct radeon_device *rdev) |
336 | { |
336 | { |
337 | uint32_t tmp = 0; |
337 | uint32_t tmp = 0; |
338 | 338 | ||
339 | if (!rdev->irq.installed) { |
339 | if (!rdev->irq.installed) { |
340 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
340 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
341 | WREG32(R_000040_GEN_INT_CNTL, 0); |
341 | WREG32(R_000040_GEN_INT_CNTL, 0); |
342 | return -EINVAL; |
342 | return -EINVAL; |
343 | } |
343 | } |
344 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
344 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
345 | tmp |= RADEON_SW_INT_ENABLE; |
345 | tmp |= RADEON_SW_INT_ENABLE; |
346 | } |
346 | } |
347 | if (rdev->irq.crtc_vblank_int[0] || |
347 | if (rdev->irq.crtc_vblank_int[0] || |
348 | atomic_read(&rdev->irq.pflip[0])) { |
348 | atomic_read(&rdev->irq.pflip[0])) { |
349 | tmp |= RADEON_CRTC_VBLANK_MASK; |
349 | tmp |= RADEON_CRTC_VBLANK_MASK; |
350 | } |
350 | } |
351 | if (rdev->irq.crtc_vblank_int[1] || |
351 | if (rdev->irq.crtc_vblank_int[1] || |
352 | atomic_read(&rdev->irq.pflip[1])) { |
352 | atomic_read(&rdev->irq.pflip[1])) { |
353 | tmp |= RADEON_CRTC2_VBLANK_MASK; |
353 | tmp |= RADEON_CRTC2_VBLANK_MASK; |
354 | } |
354 | } |
355 | if (rdev->irq.hpd[0]) { |
355 | if (rdev->irq.hpd[0]) { |
356 | tmp |= RADEON_FP_DETECT_MASK; |
356 | tmp |= RADEON_FP_DETECT_MASK; |
357 | } |
357 | } |
358 | if (rdev->irq.hpd[1]) { |
358 | if (rdev->irq.hpd[1]) { |
359 | tmp |= RADEON_FP2_DETECT_MASK; |
359 | tmp |= RADEON_FP2_DETECT_MASK; |
360 | } |
360 | } |
361 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
361 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
362 | return 0; |
362 | return 0; |
363 | } |
363 | } |
364 | 364 | ||
365 | void r100_irq_disable(struct radeon_device *rdev) |
365 | void r100_irq_disable(struct radeon_device *rdev) |
366 | { |
366 | { |
367 | u32 tmp; |
367 | u32 tmp; |
368 | 368 | ||
369 | WREG32(R_000040_GEN_INT_CNTL, 0); |
369 | WREG32(R_000040_GEN_INT_CNTL, 0); |
370 | /* Wait and acknowledge irq */ |
370 | /* Wait and acknowledge irq */ |
371 | mdelay(1); |
371 | mdelay(1); |
372 | tmp = RREG32(R_000044_GEN_INT_STATUS); |
372 | tmp = RREG32(R_000044_GEN_INT_STATUS); |
373 | WREG32(R_000044_GEN_INT_STATUS, tmp); |
373 | WREG32(R_000044_GEN_INT_STATUS, tmp); |
374 | } |
374 | } |
375 | 375 | ||
376 | static uint32_t r100_irq_ack(struct radeon_device *rdev) |
376 | static uint32_t r100_irq_ack(struct radeon_device *rdev) |
377 | { |
377 | { |
378 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
378 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
379 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
379 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
380 | RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | |
380 | RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | |
381 | RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; |
381 | RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; |
382 | 382 | ||
383 | if (irqs) { |
383 | if (irqs) { |
384 | WREG32(RADEON_GEN_INT_STATUS, irqs); |
384 | WREG32(RADEON_GEN_INT_STATUS, irqs); |
385 | } |
385 | } |
386 | return irqs & irq_mask; |
386 | return irqs & irq_mask; |
387 | } |
387 | } |
388 | 388 | ||
389 | int r100_irq_process(struct radeon_device *rdev) |
389 | int r100_irq_process(struct radeon_device *rdev) |
390 | { |
390 | { |
391 | uint32_t status, msi_rearm; |
391 | uint32_t status, msi_rearm; |
392 | bool queue_hotplug = false; |
392 | bool queue_hotplug = false; |
- | 393 | ||
393 | 394 | ||
394 | status = r100_irq_ack(rdev); |
395 | status = r100_irq_ack(rdev); |
395 | if (!status) { |
396 | if (!status) { |
396 | return IRQ_NONE; |
397 | return IRQ_NONE; |
397 | } |
398 | } |
398 | if (rdev->shutdown) { |
399 | if (rdev->shutdown) { |
399 | return IRQ_NONE; |
400 | return IRQ_NONE; |
400 | } |
401 | } |
401 | while (status) { |
402 | while (status) { |
402 | /* SW interrupt */ |
403 | /* SW interrupt */ |
403 | if (status & RADEON_SW_INT_TEST) { |
404 | if (status & RADEON_SW_INT_TEST) { |
404 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
405 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
405 | } |
406 | } |
406 | /* Vertical blank interrupts */ |
407 | /* Vertical blank interrupts */ |
407 | if (status & RADEON_CRTC_VBLANK_STAT) { |
408 | if (status & RADEON_CRTC_VBLANK_STAT) { |
408 | if (rdev->irq.crtc_vblank_int[0]) { |
409 | if (rdev->irq.crtc_vblank_int[0]) { |
409 | // drm_handle_vblank(rdev->ddev, 0); |
410 | // drm_handle_vblank(rdev->ddev, 0); |
410 | rdev->pm.vblank_sync = true; |
411 | rdev->pm.vblank_sync = true; |
411 | // wake_up(&rdev->irq.vblank_queue); |
412 | // wake_up(&rdev->irq.vblank_queue); |
412 | } |
413 | } |
413 | // if (rdev->irq.pflip[0]) |
414 | // if (rdev->irq.pflip[0]) |
414 | // radeon_crtc_handle_flip(rdev, 0); |
415 | // radeon_crtc_handle_flip(rdev, 0); |
415 | } |
416 | } |
416 | if (status & RADEON_CRTC2_VBLANK_STAT) { |
417 | if (status & RADEON_CRTC2_VBLANK_STAT) { |
417 | if (rdev->irq.crtc_vblank_int[1]) { |
418 | if (rdev->irq.crtc_vblank_int[1]) { |
418 | // drm_handle_vblank(rdev->ddev, 1); |
419 | // drm_handle_vblank(rdev->ddev, 1); |
419 | rdev->pm.vblank_sync = true; |
420 | rdev->pm.vblank_sync = true; |
420 | // wake_up(&rdev->irq.vblank_queue); |
421 | // wake_up(&rdev->irq.vblank_queue); |
421 | } |
422 | } |
422 | // if (rdev->irq.pflip[1]) |
423 | // if (rdev->irq.pflip[1]) |
423 | // radeon_crtc_handle_flip(rdev, 1); |
424 | // radeon_crtc_handle_flip(rdev, 1); |
424 | } |
425 | } |
425 | if (status & RADEON_FP_DETECT_STAT) { |
426 | if (status & RADEON_FP_DETECT_STAT) { |
426 | queue_hotplug = true; |
427 | queue_hotplug = true; |
427 | DRM_DEBUG("HPD1\n"); |
428 | DRM_DEBUG("HPD1\n"); |
428 | } |
429 | } |
429 | if (status & RADEON_FP2_DETECT_STAT) { |
430 | if (status & RADEON_FP2_DETECT_STAT) { |
430 | queue_hotplug = true; |
431 | queue_hotplug = true; |
431 | DRM_DEBUG("HPD2\n"); |
432 | DRM_DEBUG("HPD2\n"); |
432 | } |
433 | } |
433 | status = r100_irq_ack(rdev); |
434 | status = r100_irq_ack(rdev); |
434 | } |
435 | } |
435 | // if (queue_hotplug) |
436 | // if (queue_hotplug) |
436 | // schedule_work(&rdev->hotplug_work); |
437 | // schedule_work(&rdev->hotplug_work); |
437 | if (rdev->msi_enabled) { |
438 | if (rdev->msi_enabled) { |
438 | switch (rdev->family) { |
439 | switch (rdev->family) { |
439 | case CHIP_RS400: |
440 | case CHIP_RS400: |
440 | case CHIP_RS480: |
441 | case CHIP_RS480: |
441 | msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; |
442 | msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; |
442 | WREG32(RADEON_AIC_CNTL, msi_rearm); |
443 | WREG32(RADEON_AIC_CNTL, msi_rearm); |
443 | WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); |
444 | WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); |
444 | break; |
445 | break; |
445 | default: |
446 | default: |
446 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
447 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
447 | break; |
448 | break; |
448 | } |
449 | } |
449 | } |
450 | } |
450 | return IRQ_HANDLED; |
451 | return IRQ_HANDLED; |
451 | } |
452 | } |
452 | 453 | ||
453 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) |
454 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) |
454 | { |
455 | { |
455 | if (crtc == 0) |
456 | if (crtc == 0) |
456 | return RREG32(RADEON_CRTC_CRNT_FRAME); |
457 | return RREG32(RADEON_CRTC_CRNT_FRAME); |
457 | else |
458 | else |
458 | return RREG32(RADEON_CRTC2_CRNT_FRAME); |
459 | return RREG32(RADEON_CRTC2_CRNT_FRAME); |
459 | } |
460 | } |
460 | 461 | ||
461 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
462 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
462 | * for enough space (today caller are ib schedule and buffer move) */ |
463 | * for enough space (today caller are ib schedule and buffer move) */ |
463 | void r100_fence_ring_emit(struct radeon_device *rdev, |
464 | void r100_fence_ring_emit(struct radeon_device *rdev, |
464 | struct radeon_fence *fence) |
465 | struct radeon_fence *fence) |
465 | { |
466 | { |
466 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
467 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
467 | 468 | ||
468 | /* We have to make sure that caches are flushed before |
469 | /* We have to make sure that caches are flushed before |
469 | * CPU might read something from VRAM. */ |
470 | * CPU might read something from VRAM. */ |
470 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); |
471 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); |
471 | radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); |
472 | radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); |
472 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); |
473 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); |
473 | radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); |
474 | radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); |
474 | /* Wait until IDLE & CLEAN */ |
475 | /* Wait until IDLE & CLEAN */ |
475 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
476 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
476 | radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
477 | radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
477 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
478 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
478 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl | |
479 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl | |
479 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
480 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
480 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
481 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
481 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl); |
482 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl); |
482 | /* Emit fence sequence & fire IRQ */ |
483 | /* Emit fence sequence & fire IRQ */ |
483 | radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); |
484 | radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); |
484 | radeon_ring_write(ring, fence->seq); |
485 | radeon_ring_write(ring, fence->seq); |
485 | radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
486 | radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
486 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); |
487 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); |
487 | } |
488 | } |
488 | 489 | ||
489 | void r100_semaphore_ring_emit(struct radeon_device *rdev, |
490 | void r100_semaphore_ring_emit(struct radeon_device *rdev, |
490 | struct radeon_ring *ring, |
491 | struct radeon_ring *ring, |
491 | struct radeon_semaphore *semaphore, |
492 | struct radeon_semaphore *semaphore, |
492 | bool emit_wait) |
493 | bool emit_wait) |
493 | { |
494 | { |
494 | /* Unused on older asics, since we don't have semaphores or multiple rings */ |
495 | /* Unused on older asics, since we don't have semaphores or multiple rings */ |
495 | BUG(); |
496 | BUG(); |
496 | } |
497 | } |
497 | 498 | ||
498 | int r100_copy_blit(struct radeon_device *rdev, |
499 | int r100_copy_blit(struct radeon_device *rdev, |
499 | uint64_t src_offset, |
500 | uint64_t src_offset, |
500 | uint64_t dst_offset, |
501 | uint64_t dst_offset, |
501 | unsigned num_gpu_pages, |
502 | unsigned num_gpu_pages, |
502 | struct radeon_fence **fence) |
503 | struct radeon_fence **fence) |
503 | { |
504 | { |
504 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
505 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
505 | uint32_t cur_pages; |
506 | uint32_t cur_pages; |
506 | uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; |
507 | uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; |
507 | uint32_t pitch; |
508 | uint32_t pitch; |
508 | uint32_t stride_pixels; |
509 | uint32_t stride_pixels; |
509 | unsigned ndw; |
510 | unsigned ndw; |
510 | int num_loops; |
511 | int num_loops; |
511 | int r = 0; |
512 | int r = 0; |
512 | 513 | ||
513 | /* radeon limited to 16k stride */ |
514 | /* radeon limited to 16k stride */ |
514 | stride_bytes &= 0x3fff; |
515 | stride_bytes &= 0x3fff; |
515 | /* radeon pitch is /64 */ |
516 | /* radeon pitch is /64 */ |
516 | pitch = stride_bytes / 64; |
517 | pitch = stride_bytes / 64; |
517 | stride_pixels = stride_bytes / 4; |
518 | stride_pixels = stride_bytes / 4; |
518 | num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); |
519 | num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); |
519 | 520 | ||
520 | /* Ask for enough room for blit + flush + fence */ |
521 | /* Ask for enough room for blit + flush + fence */ |
521 | ndw = 64 + (10 * num_loops); |
522 | ndw = 64 + (10 * num_loops); |
522 | r = radeon_ring_lock(rdev, ring, ndw); |
523 | r = radeon_ring_lock(rdev, ring, ndw); |
523 | if (r) { |
524 | if (r) { |
524 | DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); |
525 | DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); |
525 | return -EINVAL; |
526 | return -EINVAL; |
526 | } |
527 | } |
527 | while (num_gpu_pages > 0) { |
528 | while (num_gpu_pages > 0) { |
528 | cur_pages = num_gpu_pages; |
529 | cur_pages = num_gpu_pages; |
529 | if (cur_pages > 8191) { |
530 | if (cur_pages > 8191) { |
530 | cur_pages = 8191; |
531 | cur_pages = 8191; |
531 | } |
532 | } |
532 | num_gpu_pages -= cur_pages; |
533 | num_gpu_pages -= cur_pages; |
533 | 534 | ||
534 | /* pages are in Y direction - height |
535 | /* pages are in Y direction - height |
535 | page width in X direction - width */ |
536 | page width in X direction - width */ |
536 | radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); |
537 | radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); |
537 | radeon_ring_write(ring, |
538 | radeon_ring_write(ring, |
538 | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
539 | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
539 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
540 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
540 | RADEON_GMC_SRC_CLIPPING | |
541 | RADEON_GMC_SRC_CLIPPING | |
541 | RADEON_GMC_DST_CLIPPING | |
542 | RADEON_GMC_DST_CLIPPING | |
542 | RADEON_GMC_BRUSH_NONE | |
543 | RADEON_GMC_BRUSH_NONE | |
543 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | |
544 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | |
544 | RADEON_GMC_SRC_DATATYPE_COLOR | |
545 | RADEON_GMC_SRC_DATATYPE_COLOR | |
545 | RADEON_ROP3_S | |
546 | RADEON_ROP3_S | |
546 | RADEON_DP_SRC_SOURCE_MEMORY | |
547 | RADEON_DP_SRC_SOURCE_MEMORY | |
547 | RADEON_GMC_CLR_CMP_CNTL_DIS | |
548 | RADEON_GMC_CLR_CMP_CNTL_DIS | |
548 | RADEON_GMC_WR_MSK_DIS); |
549 | RADEON_GMC_WR_MSK_DIS); |
549 | radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); |
550 | radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); |
550 | radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); |
551 | radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); |
551 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); |
552 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); |
552 | radeon_ring_write(ring, 0); |
553 | radeon_ring_write(ring, 0); |
553 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); |
554 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); |
554 | radeon_ring_write(ring, num_gpu_pages); |
555 | radeon_ring_write(ring, num_gpu_pages); |
555 | radeon_ring_write(ring, num_gpu_pages); |
556 | radeon_ring_write(ring, num_gpu_pages); |
556 | radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); |
557 | radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); |
557 | } |
558 | } |
558 | radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); |
559 | radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); |
559 | radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); |
560 | radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); |
560 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
561 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
561 | radeon_ring_write(ring, |
562 | radeon_ring_write(ring, |
562 | RADEON_WAIT_2D_IDLECLEAN | |
563 | RADEON_WAIT_2D_IDLECLEAN | |
563 | RADEON_WAIT_HOST_IDLECLEAN | |
564 | RADEON_WAIT_HOST_IDLECLEAN | |
564 | RADEON_WAIT_DMA_GUI_IDLE); |
565 | RADEON_WAIT_DMA_GUI_IDLE); |
565 | if (fence) { |
566 | if (fence) { |
566 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
567 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
567 | } |
568 | } |
568 | radeon_ring_unlock_commit(rdev, ring); |
569 | radeon_ring_unlock_commit(rdev, ring); |
569 | return r; |
570 | return r; |
570 | } |
571 | } |
571 | 572 | ||
572 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
573 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
573 | { |
574 | { |
574 | unsigned i; |
575 | unsigned i; |
575 | u32 tmp; |
576 | u32 tmp; |
576 | 577 | ||
577 | for (i = 0; i < rdev->usec_timeout; i++) { |
578 | for (i = 0; i < rdev->usec_timeout; i++) { |
578 | tmp = RREG32(R_000E40_RBBM_STATUS); |
579 | tmp = RREG32(R_000E40_RBBM_STATUS); |
579 | if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { |
580 | if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { |
580 | return 0; |
581 | return 0; |
581 | } |
582 | } |
582 | udelay(1); |
583 | udelay(1); |
583 | } |
584 | } |
584 | return -1; |
585 | return -1; |
585 | } |
586 | } |
586 | 587 | ||
587 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
588 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
588 | { |
589 | { |
589 | int r; |
590 | int r; |
590 | 591 | ||
591 | r = radeon_ring_lock(rdev, ring, 2); |
592 | r = radeon_ring_lock(rdev, ring, 2); |
592 | if (r) { |
593 | if (r) { |
593 | return; |
594 | return; |
594 | } |
595 | } |
595 | radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); |
596 | radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); |
596 | radeon_ring_write(ring, |
597 | radeon_ring_write(ring, |
597 | RADEON_ISYNC_ANY2D_IDLE3D | |
598 | RADEON_ISYNC_ANY2D_IDLE3D | |
598 | RADEON_ISYNC_ANY3D_IDLE2D | |
599 | RADEON_ISYNC_ANY3D_IDLE2D | |
599 | RADEON_ISYNC_WAIT_IDLEGUI | |
600 | RADEON_ISYNC_WAIT_IDLEGUI | |
600 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
601 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
601 | radeon_ring_unlock_commit(rdev, ring); |
602 | radeon_ring_unlock_commit(rdev, ring); |
602 | } |
603 | } |
603 | 604 | ||
604 | 605 | ||
605 | /* Load the microcode for the CP */ |
606 | /* Load the microcode for the CP */ |
606 | static int r100_cp_init_microcode(struct radeon_device *rdev) |
607 | static int r100_cp_init_microcode(struct radeon_device *rdev) |
607 | { |
608 | { |
608 | struct platform_device *pdev; |
609 | struct platform_device *pdev; |
609 | const char *fw_name = NULL; |
610 | const char *fw_name = NULL; |
610 | int err; |
611 | int err; |
611 | 612 | ||
612 | DRM_DEBUG_KMS("\n"); |
613 | DRM_DEBUG_KMS("\n"); |
613 | 614 | ||
614 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
615 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
615 | err = IS_ERR(pdev); |
616 | err = IS_ERR(pdev); |
616 | if (err) { |
617 | if (err) { |
617 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
618 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
618 | return -EINVAL; |
619 | return -EINVAL; |
619 | } |
620 | } |
620 | if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
621 | if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
621 | (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || |
622 | (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || |
622 | (rdev->family == CHIP_RS200)) { |
623 | (rdev->family == CHIP_RS200)) { |
623 | DRM_INFO("Loading R100 Microcode\n"); |
624 | DRM_INFO("Loading R100 Microcode\n"); |
624 | fw_name = FIRMWARE_R100; |
625 | fw_name = FIRMWARE_R100; |
625 | } else if ((rdev->family == CHIP_R200) || |
626 | } else if ((rdev->family == CHIP_R200) || |
626 | (rdev->family == CHIP_RV250) || |
627 | (rdev->family == CHIP_RV250) || |
627 | (rdev->family == CHIP_RV280) || |
628 | (rdev->family == CHIP_RV280) || |
628 | (rdev->family == CHIP_RS300)) { |
629 | (rdev->family == CHIP_RS300)) { |
629 | DRM_INFO("Loading R200 Microcode\n"); |
630 | DRM_INFO("Loading R200 Microcode\n"); |
630 | fw_name = FIRMWARE_R200; |
631 | fw_name = FIRMWARE_R200; |
631 | } else if ((rdev->family == CHIP_R300) || |
632 | } else if ((rdev->family == CHIP_R300) || |
632 | (rdev->family == CHIP_R350) || |
633 | (rdev->family == CHIP_R350) || |
633 | (rdev->family == CHIP_RV350) || |
634 | (rdev->family == CHIP_RV350) || |
634 | (rdev->family == CHIP_RV380) || |
635 | (rdev->family == CHIP_RV380) || |
635 | (rdev->family == CHIP_RS400) || |
636 | (rdev->family == CHIP_RS400) || |
636 | (rdev->family == CHIP_RS480)) { |
637 | (rdev->family == CHIP_RS480)) { |
637 | DRM_INFO("Loading R300 Microcode\n"); |
638 | DRM_INFO("Loading R300 Microcode\n"); |
638 | fw_name = FIRMWARE_R300; |
639 | fw_name = FIRMWARE_R300; |
639 | } else if ((rdev->family == CHIP_R420) || |
640 | } else if ((rdev->family == CHIP_R420) || |
640 | (rdev->family == CHIP_R423) || |
641 | (rdev->family == CHIP_R423) || |
641 | (rdev->family == CHIP_RV410)) { |
642 | (rdev->family == CHIP_RV410)) { |
642 | DRM_INFO("Loading R400 Microcode\n"); |
643 | DRM_INFO("Loading R400 Microcode\n"); |
643 | fw_name = FIRMWARE_R420; |
644 | fw_name = FIRMWARE_R420; |
644 | } else if ((rdev->family == CHIP_RS690) || |
645 | } else if ((rdev->family == CHIP_RS690) || |
645 | (rdev->family == CHIP_RS740)) { |
646 | (rdev->family == CHIP_RS740)) { |
646 | DRM_INFO("Loading RS690/RS740 Microcode\n"); |
647 | DRM_INFO("Loading RS690/RS740 Microcode\n"); |
647 | fw_name = FIRMWARE_RS690; |
648 | fw_name = FIRMWARE_RS690; |
648 | } else if (rdev->family == CHIP_RS600) { |
649 | } else if (rdev->family == CHIP_RS600) { |
649 | DRM_INFO("Loading RS600 Microcode\n"); |
650 | DRM_INFO("Loading RS600 Microcode\n"); |
650 | fw_name = FIRMWARE_RS600; |
651 | fw_name = FIRMWARE_RS600; |
651 | } else if ((rdev->family == CHIP_RV515) || |
652 | } else if ((rdev->family == CHIP_RV515) || |
652 | (rdev->family == CHIP_R520) || |
653 | (rdev->family == CHIP_R520) || |
653 | (rdev->family == CHIP_RV530) || |
654 | (rdev->family == CHIP_RV530) || |
654 | (rdev->family == CHIP_R580) || |
655 | (rdev->family == CHIP_R580) || |
655 | (rdev->family == CHIP_RV560) || |
656 | (rdev->family == CHIP_RV560) || |
656 | (rdev->family == CHIP_RV570)) { |
657 | (rdev->family == CHIP_RV570)) { |
657 | DRM_INFO("Loading R500 Microcode\n"); |
658 | DRM_INFO("Loading R500 Microcode\n"); |
658 | fw_name = FIRMWARE_R520; |
659 | fw_name = FIRMWARE_R520; |
659 | } |
660 | } |
660 | 661 | ||
661 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
662 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
662 | platform_device_unregister(pdev); |
663 | platform_device_unregister(pdev); |
663 | if (err) { |
664 | if (err) { |
664 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", |
665 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", |
665 | fw_name); |
666 | fw_name); |
666 | } else if (rdev->me_fw->size % 8) { |
667 | } else if (rdev->me_fw->size % 8) { |
667 | printk(KERN_ERR |
668 | printk(KERN_ERR |
668 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", |
669 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", |
669 | rdev->me_fw->size, fw_name); |
670 | rdev->me_fw->size, fw_name); |
670 | err = -EINVAL; |
671 | err = -EINVAL; |
671 | release_firmware(rdev->me_fw); |
672 | release_firmware(rdev->me_fw); |
672 | rdev->me_fw = NULL; |
673 | rdev->me_fw = NULL; |
673 | } |
674 | } |
674 | return err; |
675 | return err; |
675 | } |
676 | } |
676 | 677 | ||
677 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
678 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
678 | { |
679 | { |
679 | const __be32 *fw_data; |
680 | const __be32 *fw_data; |
680 | int i, size; |
681 | int i, size; |
681 | 682 | ||
682 | if (r100_gui_wait_for_idle(rdev)) { |
683 | if (r100_gui_wait_for_idle(rdev)) { |
683 | printk(KERN_WARNING "Failed to wait GUI idle while " |
684 | printk(KERN_WARNING "Failed to wait GUI idle while " |
684 | "programming pipes. Bad things might happen.\n"); |
685 | "programming pipes. Bad things might happen.\n"); |
685 | } |
686 | } |
686 | 687 | ||
687 | if (rdev->me_fw) { |
688 | if (rdev->me_fw) { |
688 | size = rdev->me_fw->size / 4; |
689 | size = rdev->me_fw->size / 4; |
689 | fw_data = (const __be32 *)&rdev->me_fw->data[0]; |
690 | fw_data = (const __be32 *)&rdev->me_fw->data[0]; |
690 | WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
691 | WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
691 | for (i = 0; i < size; i += 2) { |
692 | for (i = 0; i < size; i += 2) { |
692 | WREG32(RADEON_CP_ME_RAM_DATAH, |
693 | WREG32(RADEON_CP_ME_RAM_DATAH, |
693 | be32_to_cpup(&fw_data[i])); |
694 | be32_to_cpup(&fw_data[i])); |
694 | WREG32(RADEON_CP_ME_RAM_DATAL, |
695 | WREG32(RADEON_CP_ME_RAM_DATAL, |
695 | be32_to_cpup(&fw_data[i + 1])); |
696 | be32_to_cpup(&fw_data[i + 1])); |
696 | } |
697 | } |
697 | } |
698 | } |
698 | } |
699 | } |
699 | 700 | ||
700 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) |
701 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) |
701 | { |
702 | { |
702 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
703 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
703 | unsigned rb_bufsz; |
704 | unsigned rb_bufsz; |
704 | unsigned rb_blksz; |
705 | unsigned rb_blksz; |
705 | unsigned max_fetch; |
706 | unsigned max_fetch; |
706 | unsigned pre_write_timer; |
707 | unsigned pre_write_timer; |
707 | unsigned pre_write_limit; |
708 | unsigned pre_write_limit; |
708 | unsigned indirect2_start; |
709 | unsigned indirect2_start; |
709 | unsigned indirect1_start; |
710 | unsigned indirect1_start; |
710 | uint32_t tmp; |
711 | uint32_t tmp; |
711 | int r; |
712 | int r; |
712 | 713 | ||
713 | if (r100_debugfs_cp_init(rdev)) { |
714 | if (r100_debugfs_cp_init(rdev)) { |
714 | DRM_ERROR("Failed to register debugfs file for CP !\n"); |
715 | DRM_ERROR("Failed to register debugfs file for CP !\n"); |
715 | } |
716 | } |
716 | if (!rdev->me_fw) { |
717 | if (!rdev->me_fw) { |
717 | r = r100_cp_init_microcode(rdev); |
718 | r = r100_cp_init_microcode(rdev); |
718 | if (r) { |
719 | if (r) { |
719 | DRM_ERROR("Failed to load firmware!\n"); |
720 | DRM_ERROR("Failed to load firmware!\n"); |
720 | return r; |
721 | return r; |
721 | } |
722 | } |
722 | } |
723 | } |
723 | 724 | ||
724 | /* Align ring size */ |
725 | /* Align ring size */ |
725 | rb_bufsz = drm_order(ring_size / 8); |
726 | rb_bufsz = drm_order(ring_size / 8); |
726 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
727 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
727 | r100_cp_load_microcode(rdev); |
728 | r100_cp_load_microcode(rdev); |
728 | r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, |
729 | r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, |
729 | RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR, |
730 | RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR, |
730 | 0, 0x7fffff, RADEON_CP_PACKET2); |
731 | 0, 0x7fffff, RADEON_CP_PACKET2); |
731 | if (r) { |
732 | if (r) { |
732 | return r; |
733 | return r; |
733 | } |
734 | } |
734 | /* Each time the cp read 1024 bytes (16 dword/quadword) update |
735 | /* Each time the cp read 1024 bytes (16 dword/quadword) update |
735 | * the rptr copy in system ram */ |
736 | * the rptr copy in system ram */ |
736 | rb_blksz = 9; |
737 | rb_blksz = 9; |
737 | /* cp will read 128bytes at a time (4 dwords) */ |
738 | /* cp will read 128bytes at a time (4 dwords) */ |
738 | max_fetch = 1; |
739 | max_fetch = 1; |
739 | ring->align_mask = 16 - 1; |
740 | ring->align_mask = 16 - 1; |
740 | /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ |
741 | /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ |
741 | pre_write_timer = 64; |
742 | pre_write_timer = 64; |
742 | /* Force CP_RB_WPTR write if written more than one time before the |
743 | /* Force CP_RB_WPTR write if written more than one time before the |
743 | * delay expire |
744 | * delay expire |
744 | */ |
745 | */ |
745 | pre_write_limit = 0; |
746 | pre_write_limit = 0; |
746 | /* Setup the cp cache like this (cache size is 96 dwords) : |
747 | /* Setup the cp cache like this (cache size is 96 dwords) : |
747 | * RING 0 to 15 |
748 | * RING 0 to 15 |
748 | * INDIRECT1 16 to 79 |
749 | * INDIRECT1 16 to 79 |
749 | * INDIRECT2 80 to 95 |
750 | * INDIRECT2 80 to 95 |
750 | * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
751 | * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
751 | * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) |
752 | * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) |
752 | * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
753 | * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
753 | * Idea being that most of the gpu cmd will be through indirect1 buffer |
754 | * Idea being that most of the gpu cmd will be through indirect1 buffer |
754 | * so it gets the bigger cache. |
755 | * so it gets the bigger cache. |
755 | */ |
756 | */ |
756 | indirect2_start = 80; |
757 | indirect2_start = 80; |
757 | indirect1_start = 16; |
758 | indirect1_start = 16; |
758 | /* cp setup */ |
759 | /* cp setup */ |
759 | WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); |
760 | WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); |
760 | tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
761 | tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
761 | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
762 | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
762 | REG_SET(RADEON_MAX_FETCH, max_fetch)); |
763 | REG_SET(RADEON_MAX_FETCH, max_fetch)); |
763 | #ifdef __BIG_ENDIAN |
764 | #ifdef __BIG_ENDIAN |
764 | tmp |= RADEON_BUF_SWAP_32BIT; |
765 | tmp |= RADEON_BUF_SWAP_32BIT; |
765 | #endif |
766 | #endif |
766 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); |
767 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); |
767 | 768 | ||
768 | /* Set ring address */ |
769 | /* Set ring address */ |
769 | DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); |
770 | DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); |
770 | WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); |
771 | WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); |
771 | /* Force read & write ptr to 0 */ |
772 | /* Force read & write ptr to 0 */ |
772 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); |
773 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); |
773 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
774 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
774 | ring->wptr = 0; |
775 | ring->wptr = 0; |
775 | WREG32(RADEON_CP_RB_WPTR, ring->wptr); |
776 | WREG32(RADEON_CP_RB_WPTR, ring->wptr); |
776 | 777 | ||
777 | /* set the wb address whether it's enabled or not */ |
778 | /* set the wb address whether it's enabled or not */ |
778 | WREG32(R_00070C_CP_RB_RPTR_ADDR, |
779 | WREG32(R_00070C_CP_RB_RPTR_ADDR, |
779 | S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); |
780 | S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); |
780 | WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); |
781 | WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); |
781 | 782 | ||
782 | if (rdev->wb.enabled) |
783 | if (rdev->wb.enabled) |
783 | WREG32(R_000770_SCRATCH_UMSK, 0xff); |
784 | WREG32(R_000770_SCRATCH_UMSK, 0xff); |
784 | else { |
785 | else { |
785 | tmp |= RADEON_RB_NO_UPDATE; |
786 | tmp |= RADEON_RB_NO_UPDATE; |
786 | WREG32(R_000770_SCRATCH_UMSK, 0); |
787 | WREG32(R_000770_SCRATCH_UMSK, 0); |
787 | } |
788 | } |
788 | 789 | ||
789 | WREG32(RADEON_CP_RB_CNTL, tmp); |
790 | WREG32(RADEON_CP_RB_CNTL, tmp); |
790 | udelay(10); |
791 | udelay(10); |
791 | ring->rptr = RREG32(RADEON_CP_RB_RPTR); |
792 | ring->rptr = RREG32(RADEON_CP_RB_RPTR); |
792 | /* Set cp mode to bus mastering & enable cp*/ |
793 | /* Set cp mode to bus mastering & enable cp*/ |
793 | WREG32(RADEON_CP_CSQ_MODE, |
794 | WREG32(RADEON_CP_CSQ_MODE, |
794 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | |
795 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | |
795 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); |
796 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); |
796 | WREG32(RADEON_CP_RB_WPTR_DELAY, 0); |
797 | WREG32(RADEON_CP_RB_WPTR_DELAY, 0); |
797 | WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); |
798 | WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); |
798 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
799 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
799 | radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
800 | radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
800 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
801 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
801 | if (r) { |
802 | if (r) { |
802 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); |
803 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); |
803 | return r; |
804 | return r; |
804 | } |
805 | } |
805 | ring->ready = true; |
806 | ring->ready = true; |
806 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
807 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
807 | return 0; |
808 | return 0; |
808 | } |
809 | } |
809 | 810 | ||
810 | void r100_cp_fini(struct radeon_device *rdev) |
811 | void r100_cp_fini(struct radeon_device *rdev) |
811 | { |
812 | { |
812 | if (r100_cp_wait_for_idle(rdev)) { |
813 | if (r100_cp_wait_for_idle(rdev)) { |
813 | DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); |
814 | DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); |
814 | } |
815 | } |
815 | /* Disable ring */ |
816 | /* Disable ring */ |
816 | r100_cp_disable(rdev); |
817 | r100_cp_disable(rdev); |
817 | radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
818 | radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
818 | DRM_INFO("radeon: cp finalized\n"); |
819 | DRM_INFO("radeon: cp finalized\n"); |
819 | } |
820 | } |
820 | 821 | ||
821 | void r100_cp_disable(struct radeon_device *rdev) |
822 | void r100_cp_disable(struct radeon_device *rdev) |
822 | { |
823 | { |
823 | /* Disable ring */ |
824 | /* Disable ring */ |
824 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
825 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
825 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
826 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
826 | WREG32(RADEON_CP_CSQ_MODE, 0); |
827 | WREG32(RADEON_CP_CSQ_MODE, 0); |
827 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
828 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
828 | WREG32(R_000770_SCRATCH_UMSK, 0); |
829 | WREG32(R_000770_SCRATCH_UMSK, 0); |
829 | if (r100_gui_wait_for_idle(rdev)) { |
830 | if (r100_gui_wait_for_idle(rdev)) { |
830 | printk(KERN_WARNING "Failed to wait GUI idle while " |
831 | printk(KERN_WARNING "Failed to wait GUI idle while " |
831 | "programming pipes. Bad things might happen.\n"); |
832 | "programming pipes. Bad things might happen.\n"); |
832 | } |
833 | } |
833 | } |
834 | } |
834 | 835 | ||
835 | #if 0 |
836 | #if 0 |
836 | /* |
837 | /* |
837 | * CS functions |
838 | * CS functions |
838 | */ |
839 | */ |
839 | int r100_reloc_pitch_offset(struct radeon_cs_parser *p, |
840 | int r100_reloc_pitch_offset(struct radeon_cs_parser *p, |
840 | struct radeon_cs_packet *pkt, |
841 | struct radeon_cs_packet *pkt, |
841 | unsigned idx, |
842 | unsigned idx, |
842 | unsigned reg) |
843 | unsigned reg) |
843 | { |
844 | { |
844 | int r; |
845 | int r; |
845 | u32 tile_flags = 0; |
846 | u32 tile_flags = 0; |
846 | u32 tmp; |
847 | u32 tmp; |
847 | struct radeon_cs_reloc *reloc; |
848 | struct radeon_cs_reloc *reloc; |
848 | u32 value; |
849 | u32 value; |
849 | 850 | ||
850 | r = r100_cs_packet_next_reloc(p, &reloc); |
851 | r = r100_cs_packet_next_reloc(p, &reloc); |
851 | if (r) { |
852 | if (r) { |
852 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
853 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
853 | idx, reg); |
854 | idx, reg); |
854 | r100_cs_dump_packet(p, pkt); |
855 | r100_cs_dump_packet(p, pkt); |
855 | return r; |
856 | return r; |
856 | } |
857 | } |
857 | 858 | ||
858 | value = radeon_get_ib_value(p, idx); |
859 | value = radeon_get_ib_value(p, idx); |
859 | tmp = value & 0x003fffff; |
860 | tmp = value & 0x003fffff; |
860 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); |
861 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); |
861 | 862 | ||
862 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
863 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
863 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
864 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
864 | tile_flags |= RADEON_DST_TILE_MACRO; |
865 | tile_flags |= RADEON_DST_TILE_MACRO; |
865 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { |
866 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { |
866 | if (reg == RADEON_SRC_PITCH_OFFSET) { |
867 | if (reg == RADEON_SRC_PITCH_OFFSET) { |
867 | DRM_ERROR("Cannot src blit from microtiled surface\n"); |
868 | DRM_ERROR("Cannot src blit from microtiled surface\n"); |
868 | r100_cs_dump_packet(p, pkt); |
869 | r100_cs_dump_packet(p, pkt); |
869 | return -EINVAL; |
870 | return -EINVAL; |
870 | } |
871 | } |
871 | tile_flags |= RADEON_DST_TILE_MICRO; |
872 | tile_flags |= RADEON_DST_TILE_MICRO; |
872 | } |
873 | } |
873 | 874 | ||
874 | tmp |= tile_flags; |
875 | tmp |= tile_flags; |
875 | p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; |
876 | p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; |
876 | } else |
877 | } else |
877 | p->ib.ptr[idx] = (value & 0xffc00000) | tmp; |
878 | p->ib.ptr[idx] = (value & 0xffc00000) | tmp; |
878 | return 0; |
879 | return 0; |
879 | } |
880 | } |
880 | 881 | ||
881 | int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, |
882 | int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, |
882 | struct radeon_cs_packet *pkt, |
883 | struct radeon_cs_packet *pkt, |
883 | int idx) |
884 | int idx) |
884 | { |
885 | { |
885 | unsigned c, i; |
886 | unsigned c, i; |
886 | struct radeon_cs_reloc *reloc; |
887 | struct radeon_cs_reloc *reloc; |
887 | struct r100_cs_track *track; |
888 | struct r100_cs_track *track; |
888 | int r = 0; |
889 | int r = 0; |
889 | volatile uint32_t *ib; |
890 | volatile uint32_t *ib; |
890 | u32 idx_value; |
891 | u32 idx_value; |
891 | 892 | ||
892 | ib = p->ib.ptr; |
893 | ib = p->ib.ptr; |
893 | track = (struct r100_cs_track *)p->track; |
894 | track = (struct r100_cs_track *)p->track; |
894 | c = radeon_get_ib_value(p, idx++) & 0x1F; |
895 | c = radeon_get_ib_value(p, idx++) & 0x1F; |
895 | if (c > 16) { |
896 | if (c > 16) { |
896 | DRM_ERROR("Only 16 vertex buffers are allowed %d\n", |
897 | DRM_ERROR("Only 16 vertex buffers are allowed %d\n", |
897 | pkt->opcode); |
898 | pkt->opcode); |
898 | r100_cs_dump_packet(p, pkt); |
899 | r100_cs_dump_packet(p, pkt); |
899 | return -EINVAL; |
900 | return -EINVAL; |
900 | } |
901 | } |
901 | track->num_arrays = c; |
902 | track->num_arrays = c; |
902 | for (i = 0; i < (c - 1); i+=2, idx+=3) { |
903 | for (i = 0; i < (c - 1); i+=2, idx+=3) { |
903 | r = r100_cs_packet_next_reloc(p, &reloc); |
904 | r = r100_cs_packet_next_reloc(p, &reloc); |
904 | if (r) { |
905 | if (r) { |
905 | DRM_ERROR("No reloc for packet3 %d\n", |
906 | DRM_ERROR("No reloc for packet3 %d\n", |
906 | pkt->opcode); |
907 | pkt->opcode); |
907 | r100_cs_dump_packet(p, pkt); |
908 | r100_cs_dump_packet(p, pkt); |
908 | return r; |
909 | return r; |
909 | } |
910 | } |
910 | idx_value = radeon_get_ib_value(p, idx); |
911 | idx_value = radeon_get_ib_value(p, idx); |
911 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
912 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
912 | 913 | ||
913 | track->arrays[i + 0].esize = idx_value >> 8; |
914 | track->arrays[i + 0].esize = idx_value >> 8; |
914 | track->arrays[i + 0].robj = reloc->robj; |
915 | track->arrays[i + 0].robj = reloc->robj; |
915 | track->arrays[i + 0].esize &= 0x7F; |
916 | track->arrays[i + 0].esize &= 0x7F; |
916 | r = r100_cs_packet_next_reloc(p, &reloc); |
917 | r = r100_cs_packet_next_reloc(p, &reloc); |
917 | if (r) { |
918 | if (r) { |
918 | DRM_ERROR("No reloc for packet3 %d\n", |
919 | DRM_ERROR("No reloc for packet3 %d\n", |
919 | pkt->opcode); |
920 | pkt->opcode); |
920 | r100_cs_dump_packet(p, pkt); |
921 | r100_cs_dump_packet(p, pkt); |
921 | return r; |
922 | return r; |
922 | } |
923 | } |
923 | ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); |
924 | ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); |
924 | track->arrays[i + 1].robj = reloc->robj; |
925 | track->arrays[i + 1].robj = reloc->robj; |
925 | track->arrays[i + 1].esize = idx_value >> 24; |
926 | track->arrays[i + 1].esize = idx_value >> 24; |
926 | track->arrays[i + 1].esize &= 0x7F; |
927 | track->arrays[i + 1].esize &= 0x7F; |
927 | } |
928 | } |
928 | if (c & 1) { |
929 | if (c & 1) { |
929 | r = r100_cs_packet_next_reloc(p, &reloc); |
930 | r = r100_cs_packet_next_reloc(p, &reloc); |
930 | if (r) { |
931 | if (r) { |
931 | DRM_ERROR("No reloc for packet3 %d\n", |
932 | DRM_ERROR("No reloc for packet3 %d\n", |
932 | pkt->opcode); |
933 | pkt->opcode); |
933 | r100_cs_dump_packet(p, pkt); |
934 | r100_cs_dump_packet(p, pkt); |
934 | return r; |
935 | return r; |
935 | } |
936 | } |
936 | idx_value = radeon_get_ib_value(p, idx); |
937 | idx_value = radeon_get_ib_value(p, idx); |
937 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
938 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
938 | track->arrays[i + 0].robj = reloc->robj; |
939 | track->arrays[i + 0].robj = reloc->robj; |
939 | track->arrays[i + 0].esize = idx_value >> 8; |
940 | track->arrays[i + 0].esize = idx_value >> 8; |
940 | track->arrays[i + 0].esize &= 0x7F; |
941 | track->arrays[i + 0].esize &= 0x7F; |
941 | } |
942 | } |
942 | return r; |
943 | return r; |
943 | } |
944 | } |
944 | 945 | ||
945 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
946 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
946 | struct radeon_cs_packet *pkt, |
947 | struct radeon_cs_packet *pkt, |
947 | const unsigned *auth, unsigned n, |
948 | const unsigned *auth, unsigned n, |
948 | radeon_packet0_check_t check) |
949 | radeon_packet0_check_t check) |
949 | { |
950 | { |
950 | unsigned reg; |
951 | unsigned reg; |
951 | unsigned i, j, m; |
952 | unsigned i, j, m; |
952 | unsigned idx; |
953 | unsigned idx; |
953 | int r; |
954 | int r; |
954 | 955 | ||
955 | idx = pkt->idx + 1; |
956 | idx = pkt->idx + 1; |
956 | reg = pkt->reg; |
957 | reg = pkt->reg; |
957 | /* Check that register fall into register range |
958 | /* Check that register fall into register range |
958 | * determined by the number of entry (n) in the |
959 | * determined by the number of entry (n) in the |
959 | * safe register bitmap. |
960 | * safe register bitmap. |
960 | */ |
961 | */ |
961 | if (pkt->one_reg_wr) { |
962 | if (pkt->one_reg_wr) { |
962 | if ((reg >> 7) > n) { |
963 | if ((reg >> 7) > n) { |
963 | return -EINVAL; |
964 | return -EINVAL; |
964 | } |
965 | } |
965 | } else { |
966 | } else { |
966 | if (((reg + (pkt->count << 2)) >> 7) > n) { |
967 | if (((reg + (pkt->count << 2)) >> 7) > n) { |
967 | return -EINVAL; |
968 | return -EINVAL; |
968 | } |
969 | } |
969 | } |
970 | } |
970 | for (i = 0; i <= pkt->count; i++, idx++) { |
971 | for (i = 0; i <= pkt->count; i++, idx++) { |
971 | j = (reg >> 7); |
972 | j = (reg >> 7); |
972 | m = 1 << ((reg >> 2) & 31); |
973 | m = 1 << ((reg >> 2) & 31); |
973 | if (auth[j] & m) { |
974 | if (auth[j] & m) { |
974 | r = check(p, pkt, idx, reg); |
975 | r = check(p, pkt, idx, reg); |
975 | if (r) { |
976 | if (r) { |
976 | return r; |
977 | return r; |
977 | } |
978 | } |
978 | } |
979 | } |
979 | if (pkt->one_reg_wr) { |
980 | if (pkt->one_reg_wr) { |
980 | if (!(auth[j] & m)) { |
981 | if (!(auth[j] & m)) { |
981 | break; |
982 | break; |
982 | } |
983 | } |
983 | } else { |
984 | } else { |
984 | reg += 4; |
985 | reg += 4; |
985 | } |
986 | } |
986 | } |
987 | } |
987 | return 0; |
988 | return 0; |
988 | } |
989 | } |
989 | 990 | ||
990 | void r100_cs_dump_packet(struct radeon_cs_parser *p, |
991 | void r100_cs_dump_packet(struct radeon_cs_parser *p, |
991 | struct radeon_cs_packet *pkt) |
992 | struct radeon_cs_packet *pkt) |
992 | { |
993 | { |
993 | volatile uint32_t *ib; |
994 | volatile uint32_t *ib; |
994 | unsigned i; |
995 | unsigned i; |
995 | unsigned idx; |
996 | unsigned idx; |
996 | 997 | ||
997 | ib = p->ib.ptr; |
998 | ib = p->ib.ptr; |
998 | idx = pkt->idx; |
999 | idx = pkt->idx; |
999 | for (i = 0; i <= (pkt->count + 1); i++, idx++) { |
1000 | for (i = 0; i <= (pkt->count + 1); i++, idx++) { |
1000 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); |
1001 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); |
1001 | } |
1002 | } |
1002 | } |
1003 | } |
1003 | 1004 | ||
1004 | /** |
1005 | /** |
1005 | * r100_cs_packet_parse() - parse cp packet and point ib index to next packet |
1006 | * r100_cs_packet_parse() - parse cp packet and point ib index to next packet |
1006 | * @parser: parser structure holding parsing context. |
1007 | * @parser: parser structure holding parsing context. |
1007 | * @pkt: where to store packet informations |
1008 | * @pkt: where to store packet informations |
1008 | * |
1009 | * |
1009 | * Assume that chunk_ib_index is properly set. Will return -EINVAL |
1010 | * Assume that chunk_ib_index is properly set. Will return -EINVAL |
1010 | * if packet is bigger than remaining ib size. or if packets is unknown. |
1011 | * if packet is bigger than remaining ib size. or if packets is unknown. |
1011 | **/ |
1012 | **/ |
1012 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
1013 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
1013 | struct radeon_cs_packet *pkt, |
1014 | struct radeon_cs_packet *pkt, |
1014 | unsigned idx) |
1015 | unsigned idx) |
1015 | { |
1016 | { |
1016 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; |
1017 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; |
1017 | uint32_t header; |
1018 | uint32_t header; |
1018 | 1019 | ||
1019 | if (idx >= ib_chunk->length_dw) { |
1020 | if (idx >= ib_chunk->length_dw) { |
1020 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", |
1021 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", |
1021 | idx, ib_chunk->length_dw); |
1022 | idx, ib_chunk->length_dw); |
1022 | return -EINVAL; |
1023 | return -EINVAL; |
1023 | } |
1024 | } |
1024 | header = radeon_get_ib_value(p, idx); |
1025 | header = radeon_get_ib_value(p, idx); |
1025 | pkt->idx = idx; |
1026 | pkt->idx = idx; |
1026 | pkt->type = CP_PACKET_GET_TYPE(header); |
1027 | pkt->type = CP_PACKET_GET_TYPE(header); |
1027 | pkt->count = CP_PACKET_GET_COUNT(header); |
1028 | pkt->count = CP_PACKET_GET_COUNT(header); |
1028 | switch (pkt->type) { |
1029 | switch (pkt->type) { |
1029 | case PACKET_TYPE0: |
1030 | case PACKET_TYPE0: |
1030 | pkt->reg = CP_PACKET0_GET_REG(header); |
1031 | pkt->reg = CP_PACKET0_GET_REG(header); |
1031 | pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); |
1032 | pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); |
1032 | break; |
1033 | break; |
1033 | case PACKET_TYPE3: |
1034 | case PACKET_TYPE3: |
1034 | pkt->opcode = CP_PACKET3_GET_OPCODE(header); |
1035 | pkt->opcode = CP_PACKET3_GET_OPCODE(header); |
1035 | break; |
1036 | break; |
1036 | case PACKET_TYPE2: |
1037 | case PACKET_TYPE2: |
1037 | pkt->count = -1; |
1038 | pkt->count = -1; |
1038 | break; |
1039 | break; |
1039 | default: |
1040 | default: |
1040 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); |
1041 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); |
1041 | return -EINVAL; |
1042 | return -EINVAL; |
1042 | } |
1043 | } |
1043 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { |
1044 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { |
1044 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", |
1045 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", |
1045 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); |
1046 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); |
1046 | return -EINVAL; |
1047 | return -EINVAL; |
1047 | } |
1048 | } |
1048 | return 0; |
1049 | return 0; |
1049 | } |
1050 | } |
1050 | 1051 | ||
1051 | /** |
1052 | /** |
1052 | * r100_cs_packet_next_vline() - parse userspace VLINE packet |
1053 | * r100_cs_packet_next_vline() - parse userspace VLINE packet |
1053 | * @parser: parser structure holding parsing context. |
1054 | * @parser: parser structure holding parsing context. |
1054 | * |
1055 | * |
1055 | * Userspace sends a special sequence for VLINE waits. |
1056 | * Userspace sends a special sequence for VLINE waits. |
1056 | * PACKET0 - VLINE_START_END + value |
1057 | * PACKET0 - VLINE_START_END + value |
1057 | * PACKET0 - WAIT_UNTIL +_value |
1058 | * PACKET0 - WAIT_UNTIL +_value |
1058 | * RELOC (P3) - crtc_id in reloc. |
1059 | * RELOC (P3) - crtc_id in reloc. |
1059 | * |
1060 | * |
1060 | * This function parses this and relocates the VLINE START END |
1061 | * This function parses this and relocates the VLINE START END |
1061 | * and WAIT UNTIL packets to the correct crtc. |
1062 | * and WAIT UNTIL packets to the correct crtc. |
1062 | * It also detects a switched off crtc and nulls out the |
1063 | * It also detects a switched off crtc and nulls out the |
1063 | * wait in that case. |
1064 | * wait in that case. |
1064 | */ |
1065 | */ |
1065 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) |
1066 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) |
1066 | { |
1067 | { |
1067 | struct drm_mode_object *obj; |
1068 | struct drm_mode_object *obj; |
1068 | struct drm_crtc *crtc; |
1069 | struct drm_crtc *crtc; |
1069 | struct radeon_crtc *radeon_crtc; |
1070 | struct radeon_crtc *radeon_crtc; |
1070 | struct radeon_cs_packet p3reloc, waitreloc; |
1071 | struct radeon_cs_packet p3reloc, waitreloc; |
1071 | int crtc_id; |
1072 | int crtc_id; |
1072 | int r; |
1073 | int r; |
1073 | uint32_t header, h_idx, reg; |
1074 | uint32_t header, h_idx, reg; |
1074 | volatile uint32_t *ib; |
1075 | volatile uint32_t *ib; |
1075 | 1076 | ||
1076 | ib = p->ib.ptr; |
1077 | ib = p->ib.ptr; |
1077 | 1078 | ||
1078 | /* parse the wait until */ |
1079 | /* parse the wait until */ |
1079 | r = r100_cs_packet_parse(p, &waitreloc, p->idx); |
1080 | r = r100_cs_packet_parse(p, &waitreloc, p->idx); |
1080 | if (r) |
1081 | if (r) |
1081 | return r; |
1082 | return r; |
1082 | 1083 | ||
1083 | /* check its a wait until and only 1 count */ |
1084 | /* check its a wait until and only 1 count */ |
1084 | if (waitreloc.reg != RADEON_WAIT_UNTIL || |
1085 | if (waitreloc.reg != RADEON_WAIT_UNTIL || |
1085 | waitreloc.count != 0) { |
1086 | waitreloc.count != 0) { |
1086 | DRM_ERROR("vline wait had illegal wait until segment\n"); |
1087 | DRM_ERROR("vline wait had illegal wait until segment\n"); |
1087 | return -EINVAL; |
1088 | return -EINVAL; |
1088 | } |
1089 | } |
1089 | 1090 | ||
1090 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
1091 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
1091 | DRM_ERROR("vline wait had illegal wait until\n"); |
1092 | DRM_ERROR("vline wait had illegal wait until\n"); |
1092 | return -EINVAL; |
1093 | return -EINVAL; |
1093 | } |
1094 | } |
1094 | 1095 | ||
1095 | /* jump over the NOP */ |
1096 | /* jump over the NOP */ |
1096 | r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
1097 | r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
1097 | if (r) |
1098 | if (r) |
1098 | return r; |
1099 | return r; |
1099 | 1100 | ||
1100 | h_idx = p->idx - 2; |
1101 | h_idx = p->idx - 2; |
1101 | p->idx += waitreloc.count + 2; |
1102 | p->idx += waitreloc.count + 2; |
1102 | p->idx += p3reloc.count + 2; |
1103 | p->idx += p3reloc.count + 2; |
1103 | 1104 | ||
1104 | header = radeon_get_ib_value(p, h_idx); |
1105 | header = radeon_get_ib_value(p, h_idx); |
1105 | crtc_id = radeon_get_ib_value(p, h_idx + 5); |
1106 | crtc_id = radeon_get_ib_value(p, h_idx + 5); |
1106 | reg = CP_PACKET0_GET_REG(header); |
1107 | reg = CP_PACKET0_GET_REG(header); |
1107 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
1108 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
1108 | if (!obj) { |
1109 | if (!obj) { |
1109 | DRM_ERROR("cannot find crtc %d\n", crtc_id); |
1110 | DRM_ERROR("cannot find crtc %d\n", crtc_id); |
1110 | return -EINVAL; |
1111 | return -EINVAL; |
1111 | } |
1112 | } |
1112 | crtc = obj_to_crtc(obj); |
1113 | crtc = obj_to_crtc(obj); |
1113 | radeon_crtc = to_radeon_crtc(crtc); |
1114 | radeon_crtc = to_radeon_crtc(crtc); |
1114 | crtc_id = radeon_crtc->crtc_id; |
1115 | crtc_id = radeon_crtc->crtc_id; |
1115 | 1116 | ||
1116 | if (!crtc->enabled) { |
1117 | if (!crtc->enabled) { |
1117 | /* if the CRTC isn't enabled - we need to nop out the wait until */ |
1118 | /* if the CRTC isn't enabled - we need to nop out the wait until */ |
1118 | ib[h_idx + 2] = PACKET2(0); |
1119 | ib[h_idx + 2] = PACKET2(0); |
1119 | ib[h_idx + 3] = PACKET2(0); |
1120 | ib[h_idx + 3] = PACKET2(0); |
1120 | } else if (crtc_id == 1) { |
1121 | } else if (crtc_id == 1) { |
1121 | switch (reg) { |
1122 | switch (reg) { |
1122 | case AVIVO_D1MODE_VLINE_START_END: |
1123 | case AVIVO_D1MODE_VLINE_START_END: |
1123 | header &= ~R300_CP_PACKET0_REG_MASK; |
1124 | header &= ~R300_CP_PACKET0_REG_MASK; |
1124 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
1125 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
1125 | break; |
1126 | break; |
1126 | case RADEON_CRTC_GUI_TRIG_VLINE: |
1127 | case RADEON_CRTC_GUI_TRIG_VLINE: |
1127 | header &= ~R300_CP_PACKET0_REG_MASK; |
1128 | header &= ~R300_CP_PACKET0_REG_MASK; |
1128 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
1129 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
1129 | break; |
1130 | break; |
1130 | default: |
1131 | default: |
1131 | DRM_ERROR("unknown crtc reloc\n"); |
1132 | DRM_ERROR("unknown crtc reloc\n"); |
1132 | return -EINVAL; |
1133 | return -EINVAL; |
1133 | } |
1134 | } |
1134 | ib[h_idx] = header; |
1135 | ib[h_idx] = header; |
1135 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; |
1136 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; |
1136 | } |
1137 | } |
1137 | 1138 | ||
1138 | return 0; |
1139 | return 0; |
1139 | } |
1140 | } |
1140 | 1141 | ||
1141 | /** |
1142 | /** |
1142 | * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 |
1143 | * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 |
1143 | * @parser: parser structure holding parsing context. |
1144 | * @parser: parser structure holding parsing context. |
1144 | * @data: pointer to relocation data |
1145 | * @data: pointer to relocation data |
1145 | * @offset_start: starting offset |
1146 | * @offset_start: starting offset |
1146 | * @offset_mask: offset mask (to align start offset on) |
1147 | * @offset_mask: offset mask (to align start offset on) |
1147 | * @reloc: reloc informations |
1148 | * @reloc: reloc informations |
1148 | * |
1149 | * |
1149 | * Check next packet is relocation packet3, do bo validation and compute |
1150 | * Check next packet is relocation packet3, do bo validation and compute |
1150 | * GPU offset using the provided start. |
1151 | * GPU offset using the provided start. |
1151 | **/ |
1152 | **/ |
1152 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
1153 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
1153 | struct radeon_cs_reloc **cs_reloc) |
1154 | struct radeon_cs_reloc **cs_reloc) |
1154 | { |
1155 | { |
1155 | struct radeon_cs_chunk *relocs_chunk; |
1156 | struct radeon_cs_chunk *relocs_chunk; |
1156 | struct radeon_cs_packet p3reloc; |
1157 | struct radeon_cs_packet p3reloc; |
1157 | unsigned idx; |
1158 | unsigned idx; |
1158 | int r; |
1159 | int r; |
1159 | 1160 | ||
1160 | if (p->chunk_relocs_idx == -1) { |
1161 | if (p->chunk_relocs_idx == -1) { |
1161 | DRM_ERROR("No relocation chunk !\n"); |
1162 | DRM_ERROR("No relocation chunk !\n"); |
1162 | return -EINVAL; |
1163 | return -EINVAL; |
1163 | } |
1164 | } |
1164 | *cs_reloc = NULL; |
1165 | *cs_reloc = NULL; |
1165 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
1166 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
1166 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); |
1167 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); |
1167 | if (r) { |
1168 | if (r) { |
1168 | return r; |
1169 | return r; |
1169 | } |
1170 | } |
1170 | p->idx += p3reloc.count + 2; |
1171 | p->idx += p3reloc.count + 2; |
1171 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { |
1172 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { |
1172 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", |
1173 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", |
1173 | p3reloc.idx); |
1174 | p3reloc.idx); |
1174 | r100_cs_dump_packet(p, &p3reloc); |
1175 | r100_cs_dump_packet(p, &p3reloc); |
1175 | return -EINVAL; |
1176 | return -EINVAL; |
1176 | } |
1177 | } |
1177 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
1178 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
1178 | if (idx >= relocs_chunk->length_dw) { |
1179 | if (idx >= relocs_chunk->length_dw) { |
1179 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
1180 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
1180 | idx, relocs_chunk->length_dw); |
1181 | idx, relocs_chunk->length_dw); |
1181 | r100_cs_dump_packet(p, &p3reloc); |
1182 | r100_cs_dump_packet(p, &p3reloc); |
1182 | return -EINVAL; |
1183 | return -EINVAL; |
1183 | } |
1184 | } |
1184 | /* FIXME: we assume reloc size is 4 dwords */ |
1185 | /* FIXME: we assume reloc size is 4 dwords */ |
1185 | *cs_reloc = p->relocs_ptr[(idx / 4)]; |
1186 | *cs_reloc = p->relocs_ptr[(idx / 4)]; |
1186 | return 0; |
1187 | return 0; |
1187 | } |
1188 | } |
1188 | 1189 | ||
1189 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
1190 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
1190 | { |
1191 | { |
1191 | int vtx_size; |
1192 | int vtx_size; |
1192 | vtx_size = 2; |
1193 | vtx_size = 2; |
1193 | /* ordered according to bits in spec */ |
1194 | /* ordered according to bits in spec */ |
1194 | if (vtx_fmt & RADEON_SE_VTX_FMT_W0) |
1195 | if (vtx_fmt & RADEON_SE_VTX_FMT_W0) |
1195 | vtx_size++; |
1196 | vtx_size++; |
1196 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) |
1197 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) |
1197 | vtx_size += 3; |
1198 | vtx_size += 3; |
1198 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) |
1199 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) |
1199 | vtx_size++; |
1200 | vtx_size++; |
1200 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) |
1201 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) |
1201 | vtx_size++; |
1202 | vtx_size++; |
1202 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) |
1203 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) |
1203 | vtx_size += 3; |
1204 | vtx_size += 3; |
1204 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) |
1205 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) |
1205 | vtx_size++; |
1206 | vtx_size++; |
1206 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) |
1207 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) |
1207 | vtx_size++; |
1208 | vtx_size++; |
1208 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) |
1209 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) |
1209 | vtx_size += 2; |
1210 | vtx_size += 2; |
1210 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) |
1211 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) |
1211 | vtx_size += 2; |
1212 | vtx_size += 2; |
1212 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) |
1213 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) |
1213 | vtx_size++; |
1214 | vtx_size++; |
1214 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) |
1215 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) |
1215 | vtx_size += 2; |
1216 | vtx_size += 2; |
1216 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) |
1217 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) |
1217 | vtx_size++; |
1218 | vtx_size++; |
1218 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) |
1219 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) |
1219 | vtx_size += 2; |
1220 | vtx_size += 2; |
1220 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) |
1221 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) |
1221 | vtx_size++; |
1222 | vtx_size++; |
1222 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) |
1223 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) |
1223 | vtx_size++; |
1224 | vtx_size++; |
1224 | /* blend weight */ |
1225 | /* blend weight */ |
1225 | if (vtx_fmt & (0x7 << 15)) |
1226 | if (vtx_fmt & (0x7 << 15)) |
1226 | vtx_size += (vtx_fmt >> 15) & 0x7; |
1227 | vtx_size += (vtx_fmt >> 15) & 0x7; |
1227 | if (vtx_fmt & RADEON_SE_VTX_FMT_N0) |
1228 | if (vtx_fmt & RADEON_SE_VTX_FMT_N0) |
1228 | vtx_size += 3; |
1229 | vtx_size += 3; |
1229 | if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) |
1230 | if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) |
1230 | vtx_size += 2; |
1231 | vtx_size += 2; |
1231 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) |
1232 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) |
1232 | vtx_size++; |
1233 | vtx_size++; |
1233 | if (vtx_fmt & RADEON_SE_VTX_FMT_W1) |
1234 | if (vtx_fmt & RADEON_SE_VTX_FMT_W1) |
1234 | vtx_size++; |
1235 | vtx_size++; |
1235 | if (vtx_fmt & RADEON_SE_VTX_FMT_N1) |
1236 | if (vtx_fmt & RADEON_SE_VTX_FMT_N1) |
1236 | vtx_size++; |
1237 | vtx_size++; |
1237 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z) |
1238 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z) |
1238 | vtx_size++; |
1239 | vtx_size++; |
1239 | return vtx_size; |
1240 | return vtx_size; |
1240 | } |
1241 | } |
1241 | 1242 | ||
1242 | static int r100_packet0_check(struct radeon_cs_parser *p, |
1243 | static int r100_packet0_check(struct radeon_cs_parser *p, |
1243 | struct radeon_cs_packet *pkt, |
1244 | struct radeon_cs_packet *pkt, |
1244 | unsigned idx, unsigned reg) |
1245 | unsigned idx, unsigned reg) |
1245 | { |
1246 | { |
1246 | struct radeon_cs_reloc *reloc; |
1247 | struct radeon_cs_reloc *reloc; |
1247 | struct r100_cs_track *track; |
1248 | struct r100_cs_track *track; |
1248 | volatile uint32_t *ib; |
1249 | volatile uint32_t *ib; |
1249 | uint32_t tmp; |
1250 | uint32_t tmp; |
1250 | int r; |
1251 | int r; |
1251 | int i, face; |
1252 | int i, face; |
1252 | u32 tile_flags = 0; |
1253 | u32 tile_flags = 0; |
1253 | u32 idx_value; |
1254 | u32 idx_value; |
1254 | 1255 | ||
1255 | ib = p->ib.ptr; |
1256 | ib = p->ib.ptr; |
1256 | track = (struct r100_cs_track *)p->track; |
1257 | track = (struct r100_cs_track *)p->track; |
1257 | 1258 | ||
1258 | idx_value = radeon_get_ib_value(p, idx); |
1259 | idx_value = radeon_get_ib_value(p, idx); |
1259 | 1260 | ||
1260 | switch (reg) { |
1261 | switch (reg) { |
1261 | case RADEON_CRTC_GUI_TRIG_VLINE: |
1262 | case RADEON_CRTC_GUI_TRIG_VLINE: |
1262 | r = r100_cs_packet_parse_vline(p); |
1263 | r = r100_cs_packet_parse_vline(p); |
1263 | if (r) { |
1264 | if (r) { |
1264 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1265 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1265 | idx, reg); |
1266 | idx, reg); |
1266 | r100_cs_dump_packet(p, pkt); |
1267 | r100_cs_dump_packet(p, pkt); |
1267 | return r; |
1268 | return r; |
1268 | } |
1269 | } |
1269 | break; |
1270 | break; |
1270 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
1271 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
1271 | * range access */ |
1272 | * range access */ |
1272 | case RADEON_DST_PITCH_OFFSET: |
1273 | case RADEON_DST_PITCH_OFFSET: |
1273 | case RADEON_SRC_PITCH_OFFSET: |
1274 | case RADEON_SRC_PITCH_OFFSET: |
1274 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
1275 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
1275 | if (r) |
1276 | if (r) |
1276 | return r; |
1277 | return r; |
1277 | break; |
1278 | break; |
1278 | case RADEON_RB3D_DEPTHOFFSET: |
1279 | case RADEON_RB3D_DEPTHOFFSET: |
1279 | r = r100_cs_packet_next_reloc(p, &reloc); |
1280 | r = r100_cs_packet_next_reloc(p, &reloc); |
1280 | if (r) { |
1281 | if (r) { |
1281 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1282 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1282 | idx, reg); |
1283 | idx, reg); |
1283 | r100_cs_dump_packet(p, pkt); |
1284 | r100_cs_dump_packet(p, pkt); |
1284 | return r; |
1285 | return r; |
1285 | } |
1286 | } |
1286 | track->zb.robj = reloc->robj; |
1287 | track->zb.robj = reloc->robj; |
1287 | track->zb.offset = idx_value; |
1288 | track->zb.offset = idx_value; |
1288 | track->zb_dirty = true; |
1289 | track->zb_dirty = true; |
1289 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1290 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1290 | break; |
1291 | break; |
1291 | case RADEON_RB3D_COLOROFFSET: |
1292 | case RADEON_RB3D_COLOROFFSET: |
1292 | r = r100_cs_packet_next_reloc(p, &reloc); |
1293 | r = r100_cs_packet_next_reloc(p, &reloc); |
1293 | if (r) { |
1294 | if (r) { |
1294 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1295 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1295 | idx, reg); |
1296 | idx, reg); |
1296 | r100_cs_dump_packet(p, pkt); |
1297 | r100_cs_dump_packet(p, pkt); |
1297 | return r; |
1298 | return r; |
1298 | } |
1299 | } |
1299 | track->cb[0].robj = reloc->robj; |
1300 | track->cb[0].robj = reloc->robj; |
1300 | track->cb[0].offset = idx_value; |
1301 | track->cb[0].offset = idx_value; |
1301 | track->cb_dirty = true; |
1302 | track->cb_dirty = true; |
1302 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1303 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1303 | break; |
1304 | break; |
1304 | case RADEON_PP_TXOFFSET_0: |
1305 | case RADEON_PP_TXOFFSET_0: |
1305 | case RADEON_PP_TXOFFSET_1: |
1306 | case RADEON_PP_TXOFFSET_1: |
1306 | case RADEON_PP_TXOFFSET_2: |
1307 | case RADEON_PP_TXOFFSET_2: |
1307 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; |
1308 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; |
1308 | r = r100_cs_packet_next_reloc(p, &reloc); |
1309 | r = r100_cs_packet_next_reloc(p, &reloc); |
1309 | if (r) { |
1310 | if (r) { |
1310 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1311 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1311 | idx, reg); |
1312 | idx, reg); |
1312 | r100_cs_dump_packet(p, pkt); |
1313 | r100_cs_dump_packet(p, pkt); |
1313 | return r; |
1314 | return r; |
1314 | } |
1315 | } |
1315 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1316 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1316 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
1317 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
1317 | tile_flags |= RADEON_TXO_MACRO_TILE; |
1318 | tile_flags |= RADEON_TXO_MACRO_TILE; |
1318 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
1319 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
1319 | tile_flags |= RADEON_TXO_MICRO_TILE_X2; |
1320 | tile_flags |= RADEON_TXO_MICRO_TILE_X2; |
1320 | 1321 | ||
1321 | tmp = idx_value & ~(0x7 << 2); |
1322 | tmp = idx_value & ~(0x7 << 2); |
1322 | tmp |= tile_flags; |
1323 | tmp |= tile_flags; |
1323 | ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); |
1324 | ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); |
1324 | } else |
1325 | } else |
1325 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1326 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1326 | track->textures[i].robj = reloc->robj; |
1327 | track->textures[i].robj = reloc->robj; |
1327 | track->tex_dirty = true; |
1328 | track->tex_dirty = true; |
1328 | break; |
1329 | break; |
1329 | case RADEON_PP_CUBIC_OFFSET_T0_0: |
1330 | case RADEON_PP_CUBIC_OFFSET_T0_0: |
1330 | case RADEON_PP_CUBIC_OFFSET_T0_1: |
1331 | case RADEON_PP_CUBIC_OFFSET_T0_1: |
1331 | case RADEON_PP_CUBIC_OFFSET_T0_2: |
1332 | case RADEON_PP_CUBIC_OFFSET_T0_2: |
1332 | case RADEON_PP_CUBIC_OFFSET_T0_3: |
1333 | case RADEON_PP_CUBIC_OFFSET_T0_3: |
1333 | case RADEON_PP_CUBIC_OFFSET_T0_4: |
1334 | case RADEON_PP_CUBIC_OFFSET_T0_4: |
1334 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; |
1335 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; |
1335 | r = r100_cs_packet_next_reloc(p, &reloc); |
1336 | r = r100_cs_packet_next_reloc(p, &reloc); |
1336 | if (r) { |
1337 | if (r) { |
1337 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1338 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1338 | idx, reg); |
1339 | idx, reg); |
1339 | r100_cs_dump_packet(p, pkt); |
1340 | r100_cs_dump_packet(p, pkt); |
1340 | return r; |
1341 | return r; |
1341 | } |
1342 | } |
1342 | track->textures[0].cube_info[i].offset = idx_value; |
1343 | track->textures[0].cube_info[i].offset = idx_value; |
1343 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1344 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1344 | track->textures[0].cube_info[i].robj = reloc->robj; |
1345 | track->textures[0].cube_info[i].robj = reloc->robj; |
1345 | track->tex_dirty = true; |
1346 | track->tex_dirty = true; |
1346 | break; |
1347 | break; |
1347 | case RADEON_PP_CUBIC_OFFSET_T1_0: |
1348 | case RADEON_PP_CUBIC_OFFSET_T1_0: |
1348 | case RADEON_PP_CUBIC_OFFSET_T1_1: |
1349 | case RADEON_PP_CUBIC_OFFSET_T1_1: |
1349 | case RADEON_PP_CUBIC_OFFSET_T1_2: |
1350 | case RADEON_PP_CUBIC_OFFSET_T1_2: |
1350 | case RADEON_PP_CUBIC_OFFSET_T1_3: |
1351 | case RADEON_PP_CUBIC_OFFSET_T1_3: |
1351 | case RADEON_PP_CUBIC_OFFSET_T1_4: |
1352 | case RADEON_PP_CUBIC_OFFSET_T1_4: |
1352 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; |
1353 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; |
1353 | r = r100_cs_packet_next_reloc(p, &reloc); |
1354 | r = r100_cs_packet_next_reloc(p, &reloc); |
1354 | if (r) { |
1355 | if (r) { |
1355 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1356 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1356 | idx, reg); |
1357 | idx, reg); |
1357 | r100_cs_dump_packet(p, pkt); |
1358 | r100_cs_dump_packet(p, pkt); |
1358 | return r; |
1359 | return r; |
1359 | } |
1360 | } |
1360 | track->textures[1].cube_info[i].offset = idx_value; |
1361 | track->textures[1].cube_info[i].offset = idx_value; |
1361 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1362 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1362 | track->textures[1].cube_info[i].robj = reloc->robj; |
1363 | track->textures[1].cube_info[i].robj = reloc->robj; |
1363 | track->tex_dirty = true; |
1364 | track->tex_dirty = true; |
1364 | break; |
1365 | break; |
1365 | case RADEON_PP_CUBIC_OFFSET_T2_0: |
1366 | case RADEON_PP_CUBIC_OFFSET_T2_0: |
1366 | case RADEON_PP_CUBIC_OFFSET_T2_1: |
1367 | case RADEON_PP_CUBIC_OFFSET_T2_1: |
1367 | case RADEON_PP_CUBIC_OFFSET_T2_2: |
1368 | case RADEON_PP_CUBIC_OFFSET_T2_2: |
1368 | case RADEON_PP_CUBIC_OFFSET_T2_3: |
1369 | case RADEON_PP_CUBIC_OFFSET_T2_3: |
1369 | case RADEON_PP_CUBIC_OFFSET_T2_4: |
1370 | case RADEON_PP_CUBIC_OFFSET_T2_4: |
1370 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; |
1371 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; |
1371 | r = r100_cs_packet_next_reloc(p, &reloc); |
1372 | r = r100_cs_packet_next_reloc(p, &reloc); |
1372 | if (r) { |
1373 | if (r) { |
1373 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1374 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1374 | idx, reg); |
1375 | idx, reg); |
1375 | r100_cs_dump_packet(p, pkt); |
1376 | r100_cs_dump_packet(p, pkt); |
1376 | return r; |
1377 | return r; |
1377 | } |
1378 | } |
1378 | track->textures[2].cube_info[i].offset = idx_value; |
1379 | track->textures[2].cube_info[i].offset = idx_value; |
1379 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1380 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1380 | track->textures[2].cube_info[i].robj = reloc->robj; |
1381 | track->textures[2].cube_info[i].robj = reloc->robj; |
1381 | track->tex_dirty = true; |
1382 | track->tex_dirty = true; |
1382 | break; |
1383 | break; |
1383 | case RADEON_RE_WIDTH_HEIGHT: |
1384 | case RADEON_RE_WIDTH_HEIGHT: |
1384 | track->maxy = ((idx_value >> 16) & 0x7FF); |
1385 | track->maxy = ((idx_value >> 16) & 0x7FF); |
1385 | track->cb_dirty = true; |
1386 | track->cb_dirty = true; |
1386 | track->zb_dirty = true; |
1387 | track->zb_dirty = true; |
1387 | break; |
1388 | break; |
1388 | case RADEON_RB3D_COLORPITCH: |
1389 | case RADEON_RB3D_COLORPITCH: |
1389 | r = r100_cs_packet_next_reloc(p, &reloc); |
1390 | r = r100_cs_packet_next_reloc(p, &reloc); |
1390 | if (r) { |
1391 | if (r) { |
1391 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1392 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1392 | idx, reg); |
1393 | idx, reg); |
1393 | r100_cs_dump_packet(p, pkt); |
1394 | r100_cs_dump_packet(p, pkt); |
1394 | return r; |
1395 | return r; |
1395 | } |
1396 | } |
1396 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1397 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1397 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
1398 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
1398 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
1399 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
1399 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
1400 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
1400 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
1401 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
1401 | 1402 | ||
1402 | tmp = idx_value & ~(0x7 << 16); |
1403 | tmp = idx_value & ~(0x7 << 16); |
1403 | tmp |= tile_flags; |
1404 | tmp |= tile_flags; |
1404 | ib[idx] = tmp; |
1405 | ib[idx] = tmp; |
1405 | } else |
1406 | } else |
1406 | ib[idx] = idx_value; |
1407 | ib[idx] = idx_value; |
1407 | 1408 | ||
1408 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
1409 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
1409 | track->cb_dirty = true; |
1410 | track->cb_dirty = true; |
1410 | break; |
1411 | break; |
1411 | case RADEON_RB3D_DEPTHPITCH: |
1412 | case RADEON_RB3D_DEPTHPITCH: |
1412 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
1413 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
1413 | track->zb_dirty = true; |
1414 | track->zb_dirty = true; |
1414 | break; |
1415 | break; |
1415 | case RADEON_RB3D_CNTL: |
1416 | case RADEON_RB3D_CNTL: |
1416 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
1417 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
1417 | case 7: |
1418 | case 7: |
1418 | case 8: |
1419 | case 8: |
1419 | case 9: |
1420 | case 9: |
1420 | case 11: |
1421 | case 11: |
1421 | case 12: |
1422 | case 12: |
1422 | track->cb[0].cpp = 1; |
1423 | track->cb[0].cpp = 1; |
1423 | break; |
1424 | break; |
1424 | case 3: |
1425 | case 3: |
1425 | case 4: |
1426 | case 4: |
1426 | case 15: |
1427 | case 15: |
1427 | track->cb[0].cpp = 2; |
1428 | track->cb[0].cpp = 2; |
1428 | break; |
1429 | break; |
1429 | case 6: |
1430 | case 6: |
1430 | track->cb[0].cpp = 4; |
1431 | track->cb[0].cpp = 4; |
1431 | break; |
1432 | break; |
1432 | default: |
1433 | default: |
1433 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
1434 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
1434 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
1435 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
1435 | return -EINVAL; |
1436 | return -EINVAL; |
1436 | } |
1437 | } |
1437 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
1438 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
1438 | track->cb_dirty = true; |
1439 | track->cb_dirty = true; |
1439 | track->zb_dirty = true; |
1440 | track->zb_dirty = true; |
1440 | break; |
1441 | break; |
1441 | case RADEON_RB3D_ZSTENCILCNTL: |
1442 | case RADEON_RB3D_ZSTENCILCNTL: |
1442 | switch (idx_value & 0xf) { |
1443 | switch (idx_value & 0xf) { |
1443 | case 0: |
1444 | case 0: |
1444 | track->zb.cpp = 2; |
1445 | track->zb.cpp = 2; |
1445 | break; |
1446 | break; |
1446 | case 2: |
1447 | case 2: |
1447 | case 3: |
1448 | case 3: |
1448 | case 4: |
1449 | case 4: |
1449 | case 5: |
1450 | case 5: |
1450 | case 9: |
1451 | case 9: |
1451 | case 11: |
1452 | case 11: |
1452 | track->zb.cpp = 4; |
1453 | track->zb.cpp = 4; |
1453 | break; |
1454 | break; |
1454 | default: |
1455 | default: |
1455 | break; |
1456 | break; |
1456 | } |
1457 | } |
1457 | track->zb_dirty = true; |
1458 | track->zb_dirty = true; |
1458 | break; |
1459 | break; |
1459 | case RADEON_RB3D_ZPASS_ADDR: |
1460 | case RADEON_RB3D_ZPASS_ADDR: |
1460 | r = r100_cs_packet_next_reloc(p, &reloc); |
1461 | r = r100_cs_packet_next_reloc(p, &reloc); |
1461 | if (r) { |
1462 | if (r) { |
1462 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1463 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1463 | idx, reg); |
1464 | idx, reg); |
1464 | r100_cs_dump_packet(p, pkt); |
1465 | r100_cs_dump_packet(p, pkt); |
1465 | return r; |
1466 | return r; |
1466 | } |
1467 | } |
1467 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1468 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1468 | break; |
1469 | break; |
1469 | case RADEON_PP_CNTL: |
1470 | case RADEON_PP_CNTL: |
1470 | { |
1471 | { |
1471 | uint32_t temp = idx_value >> 4; |
1472 | uint32_t temp = idx_value >> 4; |
1472 | for (i = 0; i < track->num_texture; i++) |
1473 | for (i = 0; i < track->num_texture; i++) |
1473 | track->textures[i].enabled = !!(temp & (1 << i)); |
1474 | track->textures[i].enabled = !!(temp & (1 << i)); |
1474 | track->tex_dirty = true; |
1475 | track->tex_dirty = true; |
1475 | } |
1476 | } |
1476 | break; |
1477 | break; |
1477 | case RADEON_SE_VF_CNTL: |
1478 | case RADEON_SE_VF_CNTL: |
1478 | track->vap_vf_cntl = idx_value; |
1479 | track->vap_vf_cntl = idx_value; |
1479 | break; |
1480 | break; |
1480 | case RADEON_SE_VTX_FMT: |
1481 | case RADEON_SE_VTX_FMT: |
1481 | track->vtx_size = r100_get_vtx_size(idx_value); |
1482 | track->vtx_size = r100_get_vtx_size(idx_value); |
1482 | break; |
1483 | break; |
1483 | case RADEON_PP_TEX_SIZE_0: |
1484 | case RADEON_PP_TEX_SIZE_0: |
1484 | case RADEON_PP_TEX_SIZE_1: |
1485 | case RADEON_PP_TEX_SIZE_1: |
1485 | case RADEON_PP_TEX_SIZE_2: |
1486 | case RADEON_PP_TEX_SIZE_2: |
1486 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; |
1487 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; |
1487 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
1488 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
1488 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
1489 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
1489 | track->tex_dirty = true; |
1490 | track->tex_dirty = true; |
1490 | break; |
1491 | break; |
1491 | case RADEON_PP_TEX_PITCH_0: |
1492 | case RADEON_PP_TEX_PITCH_0: |
1492 | case RADEON_PP_TEX_PITCH_1: |
1493 | case RADEON_PP_TEX_PITCH_1: |
1493 | case RADEON_PP_TEX_PITCH_2: |
1494 | case RADEON_PP_TEX_PITCH_2: |
1494 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; |
1495 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; |
1495 | track->textures[i].pitch = idx_value + 32; |
1496 | track->textures[i].pitch = idx_value + 32; |
1496 | track->tex_dirty = true; |
1497 | track->tex_dirty = true; |
1497 | break; |
1498 | break; |
1498 | case RADEON_PP_TXFILTER_0: |
1499 | case RADEON_PP_TXFILTER_0: |
1499 | case RADEON_PP_TXFILTER_1: |
1500 | case RADEON_PP_TXFILTER_1: |
1500 | case RADEON_PP_TXFILTER_2: |
1501 | case RADEON_PP_TXFILTER_2: |
1501 | i = (reg - RADEON_PP_TXFILTER_0) / 24; |
1502 | i = (reg - RADEON_PP_TXFILTER_0) / 24; |
1502 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
1503 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
1503 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
1504 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
1504 | tmp = (idx_value >> 23) & 0x7; |
1505 | tmp = (idx_value >> 23) & 0x7; |
1505 | if (tmp == 2 || tmp == 6) |
1506 | if (tmp == 2 || tmp == 6) |
1506 | track->textures[i].roundup_w = false; |
1507 | track->textures[i].roundup_w = false; |
1507 | tmp = (idx_value >> 27) & 0x7; |
1508 | tmp = (idx_value >> 27) & 0x7; |
1508 | if (tmp == 2 || tmp == 6) |
1509 | if (tmp == 2 || tmp == 6) |
1509 | track->textures[i].roundup_h = false; |
1510 | track->textures[i].roundup_h = false; |
1510 | track->tex_dirty = true; |
1511 | track->tex_dirty = true; |
1511 | break; |
1512 | break; |
1512 | case RADEON_PP_TXFORMAT_0: |
1513 | case RADEON_PP_TXFORMAT_0: |
1513 | case RADEON_PP_TXFORMAT_1: |
1514 | case RADEON_PP_TXFORMAT_1: |
1514 | case RADEON_PP_TXFORMAT_2: |
1515 | case RADEON_PP_TXFORMAT_2: |
1515 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; |
1516 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; |
1516 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
1517 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
1517 | track->textures[i].use_pitch = 1; |
1518 | track->textures[i].use_pitch = 1; |
1518 | } else { |
1519 | } else { |
1519 | track->textures[i].use_pitch = 0; |
1520 | track->textures[i].use_pitch = 0; |
1520 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
1521 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
1521 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
1522 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
1522 | } |
1523 | } |
1523 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
1524 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
1524 | track->textures[i].tex_coord_type = 2; |
1525 | track->textures[i].tex_coord_type = 2; |
1525 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
1526 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
1526 | case RADEON_TXFORMAT_I8: |
1527 | case RADEON_TXFORMAT_I8: |
1527 | case RADEON_TXFORMAT_RGB332: |
1528 | case RADEON_TXFORMAT_RGB332: |
1528 | case RADEON_TXFORMAT_Y8: |
1529 | case RADEON_TXFORMAT_Y8: |
1529 | track->textures[i].cpp = 1; |
1530 | track->textures[i].cpp = 1; |
1530 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1531 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1531 | break; |
1532 | break; |
1532 | case RADEON_TXFORMAT_AI88: |
1533 | case RADEON_TXFORMAT_AI88: |
1533 | case RADEON_TXFORMAT_ARGB1555: |
1534 | case RADEON_TXFORMAT_ARGB1555: |
1534 | case RADEON_TXFORMAT_RGB565: |
1535 | case RADEON_TXFORMAT_RGB565: |
1535 | case RADEON_TXFORMAT_ARGB4444: |
1536 | case RADEON_TXFORMAT_ARGB4444: |
1536 | case RADEON_TXFORMAT_VYUY422: |
1537 | case RADEON_TXFORMAT_VYUY422: |
1537 | case RADEON_TXFORMAT_YVYU422: |
1538 | case RADEON_TXFORMAT_YVYU422: |
1538 | case RADEON_TXFORMAT_SHADOW16: |
1539 | case RADEON_TXFORMAT_SHADOW16: |
1539 | case RADEON_TXFORMAT_LDUDV655: |
1540 | case RADEON_TXFORMAT_LDUDV655: |
1540 | case RADEON_TXFORMAT_DUDV88: |
1541 | case RADEON_TXFORMAT_DUDV88: |
1541 | track->textures[i].cpp = 2; |
1542 | track->textures[i].cpp = 2; |
1542 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1543 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1543 | break; |
1544 | break; |
1544 | case RADEON_TXFORMAT_ARGB8888: |
1545 | case RADEON_TXFORMAT_ARGB8888: |
1545 | case RADEON_TXFORMAT_RGBA8888: |
1546 | case RADEON_TXFORMAT_RGBA8888: |
1546 | case RADEON_TXFORMAT_SHADOW32: |
1547 | case RADEON_TXFORMAT_SHADOW32: |
1547 | case RADEON_TXFORMAT_LDUDUV8888: |
1548 | case RADEON_TXFORMAT_LDUDUV8888: |
1548 | track->textures[i].cpp = 4; |
1549 | track->textures[i].cpp = 4; |
1549 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1550 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1550 | break; |
1551 | break; |
1551 | case RADEON_TXFORMAT_DXT1: |
1552 | case RADEON_TXFORMAT_DXT1: |
1552 | track->textures[i].cpp = 1; |
1553 | track->textures[i].cpp = 1; |
1553 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
1554 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
1554 | break; |
1555 | break; |
1555 | case RADEON_TXFORMAT_DXT23: |
1556 | case RADEON_TXFORMAT_DXT23: |
1556 | case RADEON_TXFORMAT_DXT45: |
1557 | case RADEON_TXFORMAT_DXT45: |
1557 | track->textures[i].cpp = 1; |
1558 | track->textures[i].cpp = 1; |
1558 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; |
1559 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; |
1559 | break; |
1560 | break; |
1560 | } |
1561 | } |
1561 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1562 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1562 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
1563 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
1563 | track->tex_dirty = true; |
1564 | track->tex_dirty = true; |
1564 | break; |
1565 | break; |
1565 | case RADEON_PP_CUBIC_FACES_0: |
1566 | case RADEON_PP_CUBIC_FACES_0: |
1566 | case RADEON_PP_CUBIC_FACES_1: |
1567 | case RADEON_PP_CUBIC_FACES_1: |
1567 | case RADEON_PP_CUBIC_FACES_2: |
1568 | case RADEON_PP_CUBIC_FACES_2: |
1568 | tmp = idx_value; |
1569 | tmp = idx_value; |
1569 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
1570 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
1570 | for (face = 0; face < 4; face++) { |
1571 | for (face = 0; face < 4; face++) { |
1571 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
1572 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
1572 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
1573 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
1573 | } |
1574 | } |
1574 | track->tex_dirty = true; |
1575 | track->tex_dirty = true; |
1575 | break; |
1576 | break; |
1576 | default: |
1577 | default: |
1577 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
1578 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
1578 | reg, idx); |
1579 | reg, idx); |
1579 | return -EINVAL; |
1580 | return -EINVAL; |
1580 | } |
1581 | } |
1581 | return 0; |
1582 | return 0; |
1582 | } |
1583 | } |
1583 | 1584 | ||
1584 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1585 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1585 | struct radeon_cs_packet *pkt, |
1586 | struct radeon_cs_packet *pkt, |
1586 | struct radeon_bo *robj) |
1587 | struct radeon_bo *robj) |
1587 | { |
1588 | { |
1588 | unsigned idx; |
1589 | unsigned idx; |
1589 | u32 value; |
1590 | u32 value; |
1590 | idx = pkt->idx + 1; |
1591 | idx = pkt->idx + 1; |
1591 | value = radeon_get_ib_value(p, idx + 2); |
1592 | value = radeon_get_ib_value(p, idx + 2); |
1592 | if ((value + 1) > radeon_bo_size(robj)) { |
1593 | if ((value + 1) > radeon_bo_size(robj)) { |
1593 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
1594 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
1594 | "(need %u have %lu) !\n", |
1595 | "(need %u have %lu) !\n", |
1595 | value + 1, |
1596 | value + 1, |
1596 | radeon_bo_size(robj)); |
1597 | radeon_bo_size(robj)); |
1597 | return -EINVAL; |
1598 | return -EINVAL; |
1598 | } |
1599 | } |
1599 | return 0; |
1600 | return 0; |
1600 | } |
1601 | } |
1601 | 1602 | ||
1602 | static int r100_packet3_check(struct radeon_cs_parser *p, |
1603 | static int r100_packet3_check(struct radeon_cs_parser *p, |
1603 | struct radeon_cs_packet *pkt) |
1604 | struct radeon_cs_packet *pkt) |
1604 | { |
1605 | { |
1605 | struct radeon_cs_reloc *reloc; |
1606 | struct radeon_cs_reloc *reloc; |
1606 | struct r100_cs_track *track; |
1607 | struct r100_cs_track *track; |
1607 | unsigned idx; |
1608 | unsigned idx; |
1608 | volatile uint32_t *ib; |
1609 | volatile uint32_t *ib; |
1609 | int r; |
1610 | int r; |
1610 | 1611 | ||
1611 | ib = p->ib.ptr; |
1612 | ib = p->ib.ptr; |
1612 | idx = pkt->idx + 1; |
1613 | idx = pkt->idx + 1; |
1613 | track = (struct r100_cs_track *)p->track; |
1614 | track = (struct r100_cs_track *)p->track; |
1614 | switch (pkt->opcode) { |
1615 | switch (pkt->opcode) { |
1615 | case PACKET3_3D_LOAD_VBPNTR: |
1616 | case PACKET3_3D_LOAD_VBPNTR: |
1616 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1617 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1617 | if (r) |
1618 | if (r) |
1618 | return r; |
1619 | return r; |
1619 | break; |
1620 | break; |
1620 | case PACKET3_INDX_BUFFER: |
1621 | case PACKET3_INDX_BUFFER: |
1621 | r = r100_cs_packet_next_reloc(p, &reloc); |
1622 | r = r100_cs_packet_next_reloc(p, &reloc); |
1622 | if (r) { |
1623 | if (r) { |
1623 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
1624 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
1624 | r100_cs_dump_packet(p, pkt); |
1625 | r100_cs_dump_packet(p, pkt); |
1625 | return r; |
1626 | return r; |
1626 | } |
1627 | } |
1627 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); |
1628 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); |
1628 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1629 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1629 | if (r) { |
1630 | if (r) { |
1630 | return r; |
1631 | return r; |
1631 | } |
1632 | } |
1632 | break; |
1633 | break; |
1633 | case 0x23: |
1634 | case 0x23: |
1634 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
1635 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
1635 | r = r100_cs_packet_next_reloc(p, &reloc); |
1636 | r = r100_cs_packet_next_reloc(p, &reloc); |
1636 | if (r) { |
1637 | if (r) { |
1637 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
1638 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
1638 | r100_cs_dump_packet(p, pkt); |
1639 | r100_cs_dump_packet(p, pkt); |
1639 | return r; |
1640 | return r; |
1640 | } |
1641 | } |
1641 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); |
1642 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); |
1642 | track->num_arrays = 1; |
1643 | track->num_arrays = 1; |
1643 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
1644 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
1644 | 1645 | ||
1645 | track->arrays[0].robj = reloc->robj; |
1646 | track->arrays[0].robj = reloc->robj; |
1646 | track->arrays[0].esize = track->vtx_size; |
1647 | track->arrays[0].esize = track->vtx_size; |
1647 | 1648 | ||
1648 | track->max_indx = radeon_get_ib_value(p, idx+1); |
1649 | track->max_indx = radeon_get_ib_value(p, idx+1); |
1649 | 1650 | ||
1650 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
1651 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
1651 | track->immd_dwords = pkt->count - 1; |
1652 | track->immd_dwords = pkt->count - 1; |
1652 | r = r100_cs_track_check(p->rdev, track); |
1653 | r = r100_cs_track_check(p->rdev, track); |
1653 | if (r) |
1654 | if (r) |
1654 | return r; |
1655 | return r; |
1655 | break; |
1656 | break; |
1656 | case PACKET3_3D_DRAW_IMMD: |
1657 | case PACKET3_3D_DRAW_IMMD: |
1657 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
1658 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
1658 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1659 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1659 | return -EINVAL; |
1660 | return -EINVAL; |
1660 | } |
1661 | } |
1661 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); |
1662 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); |
1662 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1663 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1663 | track->immd_dwords = pkt->count - 1; |
1664 | track->immd_dwords = pkt->count - 1; |
1664 | r = r100_cs_track_check(p->rdev, track); |
1665 | r = r100_cs_track_check(p->rdev, track); |
1665 | if (r) |
1666 | if (r) |
1666 | return r; |
1667 | return r; |
1667 | break; |
1668 | break; |
1668 | /* triggers drawing using in-packet vertex data */ |
1669 | /* triggers drawing using in-packet vertex data */ |
1669 | case PACKET3_3D_DRAW_IMMD_2: |
1670 | case PACKET3_3D_DRAW_IMMD_2: |
1670 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
1671 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
1671 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1672 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1672 | return -EINVAL; |
1673 | return -EINVAL; |
1673 | } |
1674 | } |
1674 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1675 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1675 | track->immd_dwords = pkt->count; |
1676 | track->immd_dwords = pkt->count; |
1676 | r = r100_cs_track_check(p->rdev, track); |
1677 | r = r100_cs_track_check(p->rdev, track); |
1677 | if (r) |
1678 | if (r) |
1678 | return r; |
1679 | return r; |
1679 | break; |
1680 | break; |
1680 | /* triggers drawing using in-packet vertex data */ |
1681 | /* triggers drawing using in-packet vertex data */ |
1681 | case PACKET3_3D_DRAW_VBUF_2: |
1682 | case PACKET3_3D_DRAW_VBUF_2: |
1682 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1683 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1683 | r = r100_cs_track_check(p->rdev, track); |
1684 | r = r100_cs_track_check(p->rdev, track); |
1684 | if (r) |
1685 | if (r) |
1685 | return r; |
1686 | return r; |
1686 | break; |
1687 | break; |
1687 | /* triggers drawing of vertex buffers setup elsewhere */ |
1688 | /* triggers drawing of vertex buffers setup elsewhere */ |
1688 | case PACKET3_3D_DRAW_INDX_2: |
1689 | case PACKET3_3D_DRAW_INDX_2: |
1689 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1690 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1690 | r = r100_cs_track_check(p->rdev, track); |
1691 | r = r100_cs_track_check(p->rdev, track); |
1691 | if (r) |
1692 | if (r) |
1692 | return r; |
1693 | return r; |
1693 | break; |
1694 | break; |
1694 | /* triggers drawing using indices to vertex buffer */ |
1695 | /* triggers drawing using indices to vertex buffer */ |
1695 | case PACKET3_3D_DRAW_VBUF: |
1696 | case PACKET3_3D_DRAW_VBUF: |
1696 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1697 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1697 | r = r100_cs_track_check(p->rdev, track); |
1698 | r = r100_cs_track_check(p->rdev, track); |
1698 | if (r) |
1699 | if (r) |
1699 | return r; |
1700 | return r; |
1700 | break; |
1701 | break; |
1701 | /* triggers drawing of vertex buffers setup elsewhere */ |
1702 | /* triggers drawing of vertex buffers setup elsewhere */ |
1702 | case PACKET3_3D_DRAW_INDX: |
1703 | case PACKET3_3D_DRAW_INDX: |
1703 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1704 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1704 | r = r100_cs_track_check(p->rdev, track); |
1705 | r = r100_cs_track_check(p->rdev, track); |
1705 | if (r) |
1706 | if (r) |
1706 | return r; |
1707 | return r; |
1707 | break; |
1708 | break; |
1708 | /* triggers drawing using indices to vertex buffer */ |
1709 | /* triggers drawing using indices to vertex buffer */ |
1709 | case PACKET3_3D_CLEAR_HIZ: |
1710 | case PACKET3_3D_CLEAR_HIZ: |
1710 | case PACKET3_3D_CLEAR_ZMASK: |
1711 | case PACKET3_3D_CLEAR_ZMASK: |
1711 | if (p->rdev->hyperz_filp != p->filp) |
1712 | if (p->rdev->hyperz_filp != p->filp) |
1712 | return -EINVAL; |
1713 | return -EINVAL; |
1713 | break; |
1714 | break; |
1714 | case PACKET3_NOP: |
1715 | case PACKET3_NOP: |
1715 | break; |
1716 | break; |
1716 | default: |
1717 | default: |
1717 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
1718 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
1718 | return -EINVAL; |
1719 | return -EINVAL; |
1719 | } |
1720 | } |
1720 | return 0; |
1721 | return 0; |
1721 | } |
1722 | } |
1722 | 1723 | ||
1723 | int r100_cs_parse(struct radeon_cs_parser *p) |
1724 | int r100_cs_parse(struct radeon_cs_parser *p) |
1724 | { |
1725 | { |
1725 | struct radeon_cs_packet pkt; |
1726 | struct radeon_cs_packet pkt; |
1726 | struct r100_cs_track *track; |
1727 | struct r100_cs_track *track; |
1727 | int r; |
1728 | int r; |
1728 | 1729 | ||
1729 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
1730 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
1730 | if (!track) |
1731 | if (!track) |
1731 | return -ENOMEM; |
1732 | return -ENOMEM; |
1732 | r100_cs_track_clear(p->rdev, track); |
1733 | r100_cs_track_clear(p->rdev, track); |
1733 | p->track = track; |
1734 | p->track = track; |
1734 | do { |
1735 | do { |
1735 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
1736 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
1736 | if (r) { |
1737 | if (r) { |
1737 | return r; |
1738 | return r; |
1738 | } |
1739 | } |
1739 | p->idx += pkt.count + 2; |
1740 | p->idx += pkt.count + 2; |
1740 | switch (pkt.type) { |
1741 | switch (pkt.type) { |
1741 | case PACKET_TYPE0: |
1742 | case PACKET_TYPE0: |
1742 | if (p->rdev->family >= CHIP_R200) |
1743 | if (p->rdev->family >= CHIP_R200) |
1743 | r = r100_cs_parse_packet0(p, &pkt, |
1744 | r = r100_cs_parse_packet0(p, &pkt, |
1744 | p->rdev->config.r100.reg_safe_bm, |
1745 | p->rdev->config.r100.reg_safe_bm, |
1745 | p->rdev->config.r100.reg_safe_bm_size, |
1746 | p->rdev->config.r100.reg_safe_bm_size, |
1746 | &r200_packet0_check); |
1747 | &r200_packet0_check); |
1747 | else |
1748 | else |
1748 | r = r100_cs_parse_packet0(p, &pkt, |
1749 | r = r100_cs_parse_packet0(p, &pkt, |
1749 | p->rdev->config.r100.reg_safe_bm, |
1750 | p->rdev->config.r100.reg_safe_bm, |
1750 | p->rdev->config.r100.reg_safe_bm_size, |
1751 | p->rdev->config.r100.reg_safe_bm_size, |
1751 | &r100_packet0_check); |
1752 | &r100_packet0_check); |
1752 | break; |
1753 | break; |
1753 | case PACKET_TYPE2: |
1754 | case PACKET_TYPE2: |
1754 | break; |
1755 | break; |
1755 | case PACKET_TYPE3: |
1756 | case PACKET_TYPE3: |
1756 | r = r100_packet3_check(p, &pkt); |
1757 | r = r100_packet3_check(p, &pkt); |
1757 | break; |
1758 | break; |
1758 | default: |
1759 | default: |
1759 | DRM_ERROR("Unknown packet type %d !\n", |
1760 | DRM_ERROR("Unknown packet type %d !\n", |
1760 | pkt.type); |
1761 | pkt.type); |
1761 | return -EINVAL; |
1762 | return -EINVAL; |
1762 | } |
1763 | } |
1763 | if (r) { |
1764 | if (r) { |
1764 | return r; |
1765 | return r; |
1765 | } |
1766 | } |
1766 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
1767 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
1767 | return 0; |
1768 | return 0; |
1768 | } |
1769 | } |
1769 | 1770 | ||
1770 | static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) |
1771 | static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) |
1771 | { |
1772 | { |
1772 | DRM_ERROR("pitch %d\n", t->pitch); |
1773 | DRM_ERROR("pitch %d\n", t->pitch); |
1773 | DRM_ERROR("use_pitch %d\n", t->use_pitch); |
1774 | DRM_ERROR("use_pitch %d\n", t->use_pitch); |
1774 | DRM_ERROR("width %d\n", t->width); |
1775 | DRM_ERROR("width %d\n", t->width); |
1775 | DRM_ERROR("width_11 %d\n", t->width_11); |
1776 | DRM_ERROR("width_11 %d\n", t->width_11); |
1776 | DRM_ERROR("height %d\n", t->height); |
1777 | DRM_ERROR("height %d\n", t->height); |
1777 | DRM_ERROR("height_11 %d\n", t->height_11); |
1778 | DRM_ERROR("height_11 %d\n", t->height_11); |
1778 | DRM_ERROR("num levels %d\n", t->num_levels); |
1779 | DRM_ERROR("num levels %d\n", t->num_levels); |
1779 | DRM_ERROR("depth %d\n", t->txdepth); |
1780 | DRM_ERROR("depth %d\n", t->txdepth); |
1780 | DRM_ERROR("bpp %d\n", t->cpp); |
1781 | DRM_ERROR("bpp %d\n", t->cpp); |
1781 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); |
1782 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); |
1782 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); |
1783 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); |
1783 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); |
1784 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); |
1784 | DRM_ERROR("compress format %d\n", t->compress_format); |
1785 | DRM_ERROR("compress format %d\n", t->compress_format); |
1785 | } |
1786 | } |
1786 | 1787 | ||
1787 | static int r100_track_compress_size(int compress_format, int w, int h) |
1788 | static int r100_track_compress_size(int compress_format, int w, int h) |
1788 | { |
1789 | { |
1789 | int block_width, block_height, block_bytes; |
1790 | int block_width, block_height, block_bytes; |
1790 | int wblocks, hblocks; |
1791 | int wblocks, hblocks; |
1791 | int min_wblocks; |
1792 | int min_wblocks; |
1792 | int sz; |
1793 | int sz; |
1793 | 1794 | ||
1794 | block_width = 4; |
1795 | block_width = 4; |
1795 | block_height = 4; |
1796 | block_height = 4; |
1796 | 1797 | ||
1797 | switch (compress_format) { |
1798 | switch (compress_format) { |
1798 | case R100_TRACK_COMP_DXT1: |
1799 | case R100_TRACK_COMP_DXT1: |
1799 | block_bytes = 8; |
1800 | block_bytes = 8; |
1800 | min_wblocks = 4; |
1801 | min_wblocks = 4; |
1801 | break; |
1802 | break; |
1802 | default: |
1803 | default: |
1803 | case R100_TRACK_COMP_DXT35: |
1804 | case R100_TRACK_COMP_DXT35: |
1804 | block_bytes = 16; |
1805 | block_bytes = 16; |
1805 | min_wblocks = 2; |
1806 | min_wblocks = 2; |
1806 | break; |
1807 | break; |
1807 | } |
1808 | } |
1808 | 1809 | ||
1809 | hblocks = (h + block_height - 1) / block_height; |
1810 | hblocks = (h + block_height - 1) / block_height; |
1810 | wblocks = (w + block_width - 1) / block_width; |
1811 | wblocks = (w + block_width - 1) / block_width; |
1811 | if (wblocks < min_wblocks) |
1812 | if (wblocks < min_wblocks) |
1812 | wblocks = min_wblocks; |
1813 | wblocks = min_wblocks; |
1813 | sz = wblocks * hblocks * block_bytes; |
1814 | sz = wblocks * hblocks * block_bytes; |
1814 | return sz; |
1815 | return sz; |
1815 | } |
1816 | } |
1816 | 1817 | ||
1817 | static int r100_cs_track_cube(struct radeon_device *rdev, |
1818 | static int r100_cs_track_cube(struct radeon_device *rdev, |
1818 | struct r100_cs_track *track, unsigned idx) |
1819 | struct r100_cs_track *track, unsigned idx) |
1819 | { |
1820 | { |
1820 | unsigned face, w, h; |
1821 | unsigned face, w, h; |
1821 | struct radeon_bo *cube_robj; |
1822 | struct radeon_bo *cube_robj; |
1822 | unsigned long size; |
1823 | unsigned long size; |
1823 | unsigned compress_format = track->textures[idx].compress_format; |
1824 | unsigned compress_format = track->textures[idx].compress_format; |
1824 | 1825 | ||
1825 | for (face = 0; face < 5; face++) { |
1826 | for (face = 0; face < 5; face++) { |
1826 | cube_robj = track->textures[idx].cube_info[face].robj; |
1827 | cube_robj = track->textures[idx].cube_info[face].robj; |
1827 | w = track->textures[idx].cube_info[face].width; |
1828 | w = track->textures[idx].cube_info[face].width; |
1828 | h = track->textures[idx].cube_info[face].height; |
1829 | h = track->textures[idx].cube_info[face].height; |
1829 | 1830 | ||
1830 | if (compress_format) { |
1831 | if (compress_format) { |
1831 | size = r100_track_compress_size(compress_format, w, h); |
1832 | size = r100_track_compress_size(compress_format, w, h); |
1832 | } else |
1833 | } else |
1833 | size = w * h; |
1834 | size = w * h; |
1834 | size *= track->textures[idx].cpp; |
1835 | size *= track->textures[idx].cpp; |
1835 | 1836 | ||
1836 | size += track->textures[idx].cube_info[face].offset; |
1837 | size += track->textures[idx].cube_info[face].offset; |
1837 | 1838 | ||
1838 | if (size > radeon_bo_size(cube_robj)) { |
1839 | if (size > radeon_bo_size(cube_robj)) { |
1839 | DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", |
1840 | DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", |
1840 | size, radeon_bo_size(cube_robj)); |
1841 | size, radeon_bo_size(cube_robj)); |
1841 | r100_cs_track_texture_print(&track->textures[idx]); |
1842 | r100_cs_track_texture_print(&track->textures[idx]); |
1842 | return -1; |
1843 | return -1; |
1843 | } |
1844 | } |
1844 | } |
1845 | } |
1845 | return 0; |
1846 | return 0; |
1846 | } |
1847 | } |
1847 | 1848 | ||
1848 | static int r100_cs_track_texture_check(struct radeon_device *rdev, |
1849 | static int r100_cs_track_texture_check(struct radeon_device *rdev, |
1849 | struct r100_cs_track *track) |
1850 | struct r100_cs_track *track) |
1850 | { |
1851 | { |
1851 | struct radeon_bo *robj; |
1852 | struct radeon_bo *robj; |
1852 | unsigned long size; |
1853 | unsigned long size; |
1853 | unsigned u, i, w, h, d; |
1854 | unsigned u, i, w, h, d; |
1854 | int ret; |
1855 | int ret; |
1855 | 1856 | ||
1856 | for (u = 0; u < track->num_texture; u++) { |
1857 | for (u = 0; u < track->num_texture; u++) { |
1857 | if (!track->textures[u].enabled) |
1858 | if (!track->textures[u].enabled) |
1858 | continue; |
1859 | continue; |
1859 | if (track->textures[u].lookup_disable) |
1860 | if (track->textures[u].lookup_disable) |
1860 | continue; |
1861 | continue; |
1861 | robj = track->textures[u].robj; |
1862 | robj = track->textures[u].robj; |
1862 | if (robj == NULL) { |
1863 | if (robj == NULL) { |
1863 | DRM_ERROR("No texture bound to unit %u\n", u); |
1864 | DRM_ERROR("No texture bound to unit %u\n", u); |
1864 | return -EINVAL; |
1865 | return -EINVAL; |
1865 | } |
1866 | } |
1866 | size = 0; |
1867 | size = 0; |
1867 | for (i = 0; i <= track->textures[u].num_levels; i++) { |
1868 | for (i = 0; i <= track->textures[u].num_levels; i++) { |
1868 | if (track->textures[u].use_pitch) { |
1869 | if (track->textures[u].use_pitch) { |
1869 | if (rdev->family < CHIP_R300) |
1870 | if (rdev->family < CHIP_R300) |
1870 | w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); |
1871 | w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); |
1871 | else |
1872 | else |
1872 | w = track->textures[u].pitch / (1 << i); |
1873 | w = track->textures[u].pitch / (1 << i); |
1873 | } else { |
1874 | } else { |
1874 | w = track->textures[u].width; |
1875 | w = track->textures[u].width; |
1875 | if (rdev->family >= CHIP_RV515) |
1876 | if (rdev->family >= CHIP_RV515) |
1876 | w |= track->textures[u].width_11; |
1877 | w |= track->textures[u].width_11; |
1877 | w = w / (1 << i); |
1878 | w = w / (1 << i); |
1878 | if (track->textures[u].roundup_w) |
1879 | if (track->textures[u].roundup_w) |
1879 | w = roundup_pow_of_two(w); |
1880 | w = roundup_pow_of_two(w); |
1880 | } |
1881 | } |
1881 | h = track->textures[u].height; |
1882 | h = track->textures[u].height; |
1882 | if (rdev->family >= CHIP_RV515) |
1883 | if (rdev->family >= CHIP_RV515) |
1883 | h |= track->textures[u].height_11; |
1884 | h |= track->textures[u].height_11; |
1884 | h = h / (1 << i); |
1885 | h = h / (1 << i); |
1885 | if (track->textures[u].roundup_h) |
1886 | if (track->textures[u].roundup_h) |
1886 | h = roundup_pow_of_two(h); |
1887 | h = roundup_pow_of_two(h); |
1887 | if (track->textures[u].tex_coord_type == 1) { |
1888 | if (track->textures[u].tex_coord_type == 1) { |
1888 | d = (1 << track->textures[u].txdepth) / (1 << i); |
1889 | d = (1 << track->textures[u].txdepth) / (1 << i); |
1889 | if (!d) |
1890 | if (!d) |
1890 | d = 1; |
1891 | d = 1; |
1891 | } else { |
1892 | } else { |
1892 | d = 1; |
1893 | d = 1; |
1893 | } |
1894 | } |
1894 | if (track->textures[u].compress_format) { |
1895 | if (track->textures[u].compress_format) { |
1895 | 1896 | ||
1896 | size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; |
1897 | size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; |
1897 | /* compressed textures are block based */ |
1898 | /* compressed textures are block based */ |
1898 | } else |
1899 | } else |
1899 | size += w * h * d; |
1900 | size += w * h * d; |
1900 | } |
1901 | } |
1901 | size *= track->textures[u].cpp; |
1902 | size *= track->textures[u].cpp; |
1902 | 1903 | ||
1903 | switch (track->textures[u].tex_coord_type) { |
1904 | switch (track->textures[u].tex_coord_type) { |
1904 | case 0: |
1905 | case 0: |
1905 | case 1: |
1906 | case 1: |
1906 | break; |
1907 | break; |
1907 | case 2: |
1908 | case 2: |
1908 | if (track->separate_cube) { |
1909 | if (track->separate_cube) { |
1909 | ret = r100_cs_track_cube(rdev, track, u); |
1910 | ret = r100_cs_track_cube(rdev, track, u); |
1910 | if (ret) |
1911 | if (ret) |
1911 | return ret; |
1912 | return ret; |
1912 | } else |
1913 | } else |
1913 | size *= 6; |
1914 | size *= 6; |
1914 | break; |
1915 | break; |
1915 | default: |
1916 | default: |
1916 | DRM_ERROR("Invalid texture coordinate type %u for unit " |
1917 | DRM_ERROR("Invalid texture coordinate type %u for unit " |
1917 | "%u\n", track->textures[u].tex_coord_type, u); |
1918 | "%u\n", track->textures[u].tex_coord_type, u); |
1918 | return -EINVAL; |
1919 | return -EINVAL; |
1919 | } |
1920 | } |
1920 | if (size > radeon_bo_size(robj)) { |
1921 | if (size > radeon_bo_size(robj)) { |
1921 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " |
1922 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " |
1922 | "%lu\n", u, size, radeon_bo_size(robj)); |
1923 | "%lu\n", u, size, radeon_bo_size(robj)); |
1923 | r100_cs_track_texture_print(&track->textures[u]); |
1924 | r100_cs_track_texture_print(&track->textures[u]); |
1924 | return -EINVAL; |
1925 | return -EINVAL; |
1925 | } |
1926 | } |
1926 | } |
1927 | } |
1927 | return 0; |
1928 | return 0; |
1928 | } |
1929 | } |
1929 | 1930 | ||
1930 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) |
1931 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) |
1931 | { |
1932 | { |
1932 | unsigned i; |
1933 | unsigned i; |
1933 | unsigned long size; |
1934 | unsigned long size; |
1934 | unsigned prim_walk; |
1935 | unsigned prim_walk; |
1935 | unsigned nverts; |
1936 | unsigned nverts; |
1936 | unsigned num_cb = track->cb_dirty ? track->num_cb : 0; |
1937 | unsigned num_cb = track->cb_dirty ? track->num_cb : 0; |
1937 | 1938 | ||
1938 | if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && |
1939 | if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && |
1939 | !track->blend_read_enable) |
1940 | !track->blend_read_enable) |
1940 | num_cb = 0; |
1941 | num_cb = 0; |
1941 | 1942 | ||
1942 | for (i = 0; i < num_cb; i++) { |
1943 | for (i = 0; i < num_cb; i++) { |
1943 | if (track->cb[i].robj == NULL) { |
1944 | if (track->cb[i].robj == NULL) { |
1944 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); |
1945 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); |
1945 | return -EINVAL; |
1946 | return -EINVAL; |
1946 | } |
1947 | } |
1947 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; |
1948 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; |
1948 | size += track->cb[i].offset; |
1949 | size += track->cb[i].offset; |
1949 | if (size > radeon_bo_size(track->cb[i].robj)) { |
1950 | if (size > radeon_bo_size(track->cb[i].robj)) { |
1950 | DRM_ERROR("[drm] Buffer too small for color buffer %d " |
1951 | DRM_ERROR("[drm] Buffer too small for color buffer %d " |
1951 | "(need %lu have %lu) !\n", i, size, |
1952 | "(need %lu have %lu) !\n", i, size, |
1952 | radeon_bo_size(track->cb[i].robj)); |
1953 | radeon_bo_size(track->cb[i].robj)); |
1953 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", |
1954 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", |
1954 | i, track->cb[i].pitch, track->cb[i].cpp, |
1955 | i, track->cb[i].pitch, track->cb[i].cpp, |
1955 | track->cb[i].offset, track->maxy); |
1956 | track->cb[i].offset, track->maxy); |
1956 | return -EINVAL; |
1957 | return -EINVAL; |
1957 | } |
1958 | } |
1958 | } |
1959 | } |
1959 | track->cb_dirty = false; |
1960 | track->cb_dirty = false; |
1960 | 1961 | ||
1961 | if (track->zb_dirty && track->z_enabled) { |
1962 | if (track->zb_dirty && track->z_enabled) { |
1962 | if (track->zb.robj == NULL) { |
1963 | if (track->zb.robj == NULL) { |
1963 | DRM_ERROR("[drm] No buffer for z buffer !\n"); |
1964 | DRM_ERROR("[drm] No buffer for z buffer !\n"); |
1964 | return -EINVAL; |
1965 | return -EINVAL; |
1965 | } |
1966 | } |
1966 | size = track->zb.pitch * track->zb.cpp * track->maxy; |
1967 | size = track->zb.pitch * track->zb.cpp * track->maxy; |
1967 | size += track->zb.offset; |
1968 | size += track->zb.offset; |
1968 | if (size > radeon_bo_size(track->zb.robj)) { |
1969 | if (size > radeon_bo_size(track->zb.robj)) { |
1969 | DRM_ERROR("[drm] Buffer too small for z buffer " |
1970 | DRM_ERROR("[drm] Buffer too small for z buffer " |
1970 | "(need %lu have %lu) !\n", size, |
1971 | "(need %lu have %lu) !\n", size, |
1971 | radeon_bo_size(track->zb.robj)); |
1972 | radeon_bo_size(track->zb.robj)); |
1972 | DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", |
1973 | DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", |
1973 | track->zb.pitch, track->zb.cpp, |
1974 | track->zb.pitch, track->zb.cpp, |
1974 | track->zb.offset, track->maxy); |
1975 | track->zb.offset, track->maxy); |
1975 | return -EINVAL; |
1976 | return -EINVAL; |
1976 | } |
1977 | } |
1977 | } |
1978 | } |
1978 | track->zb_dirty = false; |
1979 | track->zb_dirty = false; |
1979 | 1980 | ||
1980 | if (track->aa_dirty && track->aaresolve) { |
1981 | if (track->aa_dirty && track->aaresolve) { |
1981 | if (track->aa.robj == NULL) { |
1982 | if (track->aa.robj == NULL) { |
1982 | DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); |
1983 | DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); |
1983 | return -EINVAL; |
1984 | return -EINVAL; |
1984 | } |
1985 | } |
1985 | /* I believe the format comes from colorbuffer0. */ |
1986 | /* I believe the format comes from colorbuffer0. */ |
1986 | size = track->aa.pitch * track->cb[0].cpp * track->maxy; |
1987 | size = track->aa.pitch * track->cb[0].cpp * track->maxy; |
1987 | size += track->aa.offset; |
1988 | size += track->aa.offset; |
1988 | if (size > radeon_bo_size(track->aa.robj)) { |
1989 | if (size > radeon_bo_size(track->aa.robj)) { |
1989 | DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " |
1990 | DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " |
1990 | "(need %lu have %lu) !\n", i, size, |
1991 | "(need %lu have %lu) !\n", i, size, |
1991 | radeon_bo_size(track->aa.robj)); |
1992 | radeon_bo_size(track->aa.robj)); |
1992 | DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", |
1993 | DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", |
1993 | i, track->aa.pitch, track->cb[0].cpp, |
1994 | i, track->aa.pitch, track->cb[0].cpp, |
1994 | track->aa.offset, track->maxy); |
1995 | track->aa.offset, track->maxy); |
1995 | return -EINVAL; |
1996 | return -EINVAL; |
1996 | } |
1997 | } |
1997 | } |
1998 | } |
1998 | track->aa_dirty = false; |
1999 | track->aa_dirty = false; |
1999 | 2000 | ||
2000 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; |
2001 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; |
2001 | if (track->vap_vf_cntl & (1 << 14)) { |
2002 | if (track->vap_vf_cntl & (1 << 14)) { |
2002 | nverts = track->vap_alt_nverts; |
2003 | nverts = track->vap_alt_nverts; |
2003 | } else { |
2004 | } else { |
2004 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; |
2005 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; |
2005 | } |
2006 | } |
2006 | switch (prim_walk) { |
2007 | switch (prim_walk) { |
2007 | case 1: |
2008 | case 1: |
2008 | for (i = 0; i < track->num_arrays; i++) { |
2009 | for (i = 0; i < track->num_arrays; i++) { |
2009 | size = track->arrays[i].esize * track->max_indx * 4; |
2010 | size = track->arrays[i].esize * track->max_indx * 4; |
2010 | if (track->arrays[i].robj == NULL) { |
2011 | if (track->arrays[i].robj == NULL) { |
2011 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
2012 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
2012 | "bound\n", prim_walk, i); |
2013 | "bound\n", prim_walk, i); |
2013 | return -EINVAL; |
2014 | return -EINVAL; |
2014 | } |
2015 | } |
2015 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
2016 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
2016 | dev_err(rdev->dev, "(PW %u) Vertex array %u " |
2017 | dev_err(rdev->dev, "(PW %u) Vertex array %u " |
2017 | "need %lu dwords have %lu dwords\n", |
2018 | "need %lu dwords have %lu dwords\n", |
2018 | prim_walk, i, size >> 2, |
2019 | prim_walk, i, size >> 2, |
2019 | radeon_bo_size(track->arrays[i].robj) |
2020 | radeon_bo_size(track->arrays[i].robj) |
2020 | >> 2); |
2021 | >> 2); |
2021 | DRM_ERROR("Max indices %u\n", track->max_indx); |
2022 | DRM_ERROR("Max indices %u\n", track->max_indx); |
2022 | return -EINVAL; |
2023 | return -EINVAL; |
2023 | } |
2024 | } |
2024 | } |
2025 | } |
2025 | break; |
2026 | break; |
2026 | case 2: |
2027 | case 2: |
2027 | for (i = 0; i < track->num_arrays; i++) { |
2028 | for (i = 0; i < track->num_arrays; i++) { |
2028 | size = track->arrays[i].esize * (nverts - 1) * 4; |
2029 | size = track->arrays[i].esize * (nverts - 1) * 4; |
2029 | if (track->arrays[i].robj == NULL) { |
2030 | if (track->arrays[i].robj == NULL) { |
2030 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
2031 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
2031 | "bound\n", prim_walk, i); |
2032 | "bound\n", prim_walk, i); |
2032 | return -EINVAL; |
2033 | return -EINVAL; |
2033 | } |
2034 | } |
2034 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
2035 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
2035 | dev_err(rdev->dev, "(PW %u) Vertex array %u " |
2036 | dev_err(rdev->dev, "(PW %u) Vertex array %u " |
2036 | "need %lu dwords have %lu dwords\n", |
2037 | "need %lu dwords have %lu dwords\n", |
2037 | prim_walk, i, size >> 2, |
2038 | prim_walk, i, size >> 2, |
2038 | radeon_bo_size(track->arrays[i].robj) |
2039 | radeon_bo_size(track->arrays[i].robj) |
2039 | >> 2); |
2040 | >> 2); |
2040 | return -EINVAL; |
2041 | return -EINVAL; |
2041 | } |
2042 | } |
2042 | } |
2043 | } |
2043 | break; |
2044 | break; |
2044 | case 3: |
2045 | case 3: |
2045 | size = track->vtx_size * nverts; |
2046 | size = track->vtx_size * nverts; |
2046 | if (size != track->immd_dwords) { |
2047 | if (size != track->immd_dwords) { |
2047 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", |
2048 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", |
2048 | track->immd_dwords, size); |
2049 | track->immd_dwords, size); |
2049 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", |
2050 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", |
2050 | nverts, track->vtx_size); |
2051 | nverts, track->vtx_size); |
2051 | return -EINVAL; |
2052 | return -EINVAL; |
2052 | } |
2053 | } |
2053 | break; |
2054 | break; |
2054 | default: |
2055 | default: |
2055 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", |
2056 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", |
2056 | prim_walk); |
2057 | prim_walk); |
2057 | return -EINVAL; |
2058 | return -EINVAL; |
2058 | } |
2059 | } |
2059 | 2060 | ||
2060 | if (track->tex_dirty) { |
2061 | if (track->tex_dirty) { |
2061 | track->tex_dirty = false; |
2062 | track->tex_dirty = false; |
2062 | return r100_cs_track_texture_check(rdev, track); |
2063 | return r100_cs_track_texture_check(rdev, track); |
2063 | } |
2064 | } |
2064 | return 0; |
2065 | return 0; |
2065 | } |
2066 | } |
2066 | 2067 | ||
2067 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) |
2068 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) |
2068 | { |
2069 | { |
2069 | unsigned i, face; |
2070 | unsigned i, face; |
2070 | 2071 | ||
2071 | track->cb_dirty = true; |
2072 | track->cb_dirty = true; |
2072 | track->zb_dirty = true; |
2073 | track->zb_dirty = true; |
2073 | track->tex_dirty = true; |
2074 | track->tex_dirty = true; |
2074 | track->aa_dirty = true; |
2075 | track->aa_dirty = true; |
2075 | 2076 | ||
2076 | if (rdev->family < CHIP_R300) { |
2077 | if (rdev->family < CHIP_R300) { |
2077 | track->num_cb = 1; |
2078 | track->num_cb = 1; |
2078 | if (rdev->family <= CHIP_RS200) |
2079 | if (rdev->family <= CHIP_RS200) |
2079 | track->num_texture = 3; |
2080 | track->num_texture = 3; |
2080 | else |
2081 | else |
2081 | track->num_texture = 6; |
2082 | track->num_texture = 6; |
2082 | track->maxy = 2048; |
2083 | track->maxy = 2048; |
2083 | track->separate_cube = 1; |
2084 | track->separate_cube = 1; |
2084 | } else { |
2085 | } else { |
2085 | track->num_cb = 4; |
2086 | track->num_cb = 4; |
2086 | track->num_texture = 16; |
2087 | track->num_texture = 16; |
2087 | track->maxy = 4096; |
2088 | track->maxy = 4096; |
2088 | track->separate_cube = 0; |
2089 | track->separate_cube = 0; |
2089 | track->aaresolve = false; |
2090 | track->aaresolve = false; |
2090 | track->aa.robj = NULL; |
2091 | track->aa.robj = NULL; |
2091 | } |
2092 | } |
2092 | 2093 | ||
2093 | for (i = 0; i < track->num_cb; i++) { |
2094 | for (i = 0; i < track->num_cb; i++) { |
2094 | track->cb[i].robj = NULL; |
2095 | track->cb[i].robj = NULL; |
2095 | track->cb[i].pitch = 8192; |
2096 | track->cb[i].pitch = 8192; |
2096 | track->cb[i].cpp = 16; |
2097 | track->cb[i].cpp = 16; |
2097 | track->cb[i].offset = 0; |
2098 | track->cb[i].offset = 0; |
2098 | } |
2099 | } |
2099 | track->z_enabled = true; |
2100 | track->z_enabled = true; |
2100 | track->zb.robj = NULL; |
2101 | track->zb.robj = NULL; |
2101 | track->zb.pitch = 8192; |
2102 | track->zb.pitch = 8192; |
2102 | track->zb.cpp = 4; |
2103 | track->zb.cpp = 4; |
2103 | track->zb.offset = 0; |
2104 | track->zb.offset = 0; |
2104 | track->vtx_size = 0x7F; |
2105 | track->vtx_size = 0x7F; |
2105 | track->immd_dwords = 0xFFFFFFFFUL; |
2106 | track->immd_dwords = 0xFFFFFFFFUL; |
2106 | track->num_arrays = 11; |
2107 | track->num_arrays = 11; |
2107 | track->max_indx = 0x00FFFFFFUL; |
2108 | track->max_indx = 0x00FFFFFFUL; |
2108 | for (i = 0; i < track->num_arrays; i++) { |
2109 | for (i = 0; i < track->num_arrays; i++) { |
2109 | track->arrays[i].robj = NULL; |
2110 | track->arrays[i].robj = NULL; |
2110 | track->arrays[i].esize = 0x7F; |
2111 | track->arrays[i].esize = 0x7F; |
2111 | } |
2112 | } |
2112 | for (i = 0; i < track->num_texture; i++) { |
2113 | for (i = 0; i < track->num_texture; i++) { |
2113 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
2114 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
2114 | track->textures[i].pitch = 16536; |
2115 | track->textures[i].pitch = 16536; |
2115 | track->textures[i].width = 16536; |
2116 | track->textures[i].width = 16536; |
2116 | track->textures[i].height = 16536; |
2117 | track->textures[i].height = 16536; |
2117 | track->textures[i].width_11 = 1 << 11; |
2118 | track->textures[i].width_11 = 1 << 11; |
2118 | track->textures[i].height_11 = 1 << 11; |
2119 | track->textures[i].height_11 = 1 << 11; |
2119 | track->textures[i].num_levels = 12; |
2120 | track->textures[i].num_levels = 12; |
2120 | if (rdev->family <= CHIP_RS200) { |
2121 | if (rdev->family <= CHIP_RS200) { |
2121 | track->textures[i].tex_coord_type = 0; |
2122 | track->textures[i].tex_coord_type = 0; |
2122 | track->textures[i].txdepth = 0; |
2123 | track->textures[i].txdepth = 0; |
2123 | } else { |
2124 | } else { |
2124 | track->textures[i].txdepth = 16; |
2125 | track->textures[i].txdepth = 16; |
2125 | track->textures[i].tex_coord_type = 1; |
2126 | track->textures[i].tex_coord_type = 1; |
2126 | } |
2127 | } |
2127 | track->textures[i].cpp = 64; |
2128 | track->textures[i].cpp = 64; |
2128 | track->textures[i].robj = NULL; |
2129 | track->textures[i].robj = NULL; |
2129 | /* CS IB emission code makes sure texture unit are disabled */ |
2130 | /* CS IB emission code makes sure texture unit are disabled */ |
2130 | track->textures[i].enabled = false; |
2131 | track->textures[i].enabled = false; |
2131 | track->textures[i].lookup_disable = false; |
2132 | track->textures[i].lookup_disable = false; |
2132 | track->textures[i].roundup_w = true; |
2133 | track->textures[i].roundup_w = true; |
2133 | track->textures[i].roundup_h = true; |
2134 | track->textures[i].roundup_h = true; |
2134 | if (track->separate_cube) |
2135 | if (track->separate_cube) |
2135 | for (face = 0; face < 5; face++) { |
2136 | for (face = 0; face < 5; face++) { |
2136 | track->textures[i].cube_info[face].robj = NULL; |
2137 | track->textures[i].cube_info[face].robj = NULL; |
2137 | track->textures[i].cube_info[face].width = 16536; |
2138 | track->textures[i].cube_info[face].width = 16536; |
2138 | track->textures[i].cube_info[face].height = 16536; |
2139 | track->textures[i].cube_info[face].height = 16536; |
2139 | track->textures[i].cube_info[face].offset = 0; |
2140 | track->textures[i].cube_info[face].offset = 0; |
2140 | } |
2141 | } |
2141 | } |
2142 | } |
2142 | } |
2143 | } |
2143 | #endif |
2144 | #endif |
2144 | 2145 | ||
2145 | /* |
2146 | /* |
2146 | * Global GPU functions |
2147 | * Global GPU functions |
2147 | */ |
2148 | */ |
2148 | static void r100_errata(struct radeon_device *rdev) |
2149 | static void r100_errata(struct radeon_device *rdev) |
2149 | { |
2150 | { |
2150 | rdev->pll_errata = 0; |
2151 | rdev->pll_errata = 0; |
2151 | 2152 | ||
2152 | if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { |
2153 | if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { |
2153 | rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; |
2154 | rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; |
2154 | } |
2155 | } |
2155 | 2156 | ||
2156 | if (rdev->family == CHIP_RV100 || |
2157 | if (rdev->family == CHIP_RV100 || |
2157 | rdev->family == CHIP_RS100 || |
2158 | rdev->family == CHIP_RS100 || |
2158 | rdev->family == CHIP_RS200) { |
2159 | rdev->family == CHIP_RS200) { |
2159 | rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; |
2160 | rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; |
2160 | } |
2161 | } |
2161 | } |
2162 | } |
2162 | 2163 | ||
2163 | static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) |
2164 | static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) |
2164 | { |
2165 | { |
2165 | unsigned i; |
2166 | unsigned i; |
2166 | uint32_t tmp; |
2167 | uint32_t tmp; |
2167 | 2168 | ||
2168 | for (i = 0; i < rdev->usec_timeout; i++) { |
2169 | for (i = 0; i < rdev->usec_timeout; i++) { |
2169 | tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; |
2170 | tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; |
2170 | if (tmp >= n) { |
2171 | if (tmp >= n) { |
2171 | return 0; |
2172 | return 0; |
2172 | } |
2173 | } |
2173 | DRM_UDELAY(1); |
2174 | DRM_UDELAY(1); |
2174 | } |
2175 | } |
2175 | return -1; |
2176 | return -1; |
2176 | } |
2177 | } |
2177 | 2178 | ||
2178 | int r100_gui_wait_for_idle(struct radeon_device *rdev) |
2179 | int r100_gui_wait_for_idle(struct radeon_device *rdev) |
2179 | { |
2180 | { |
2180 | unsigned i; |
2181 | unsigned i; |
2181 | uint32_t tmp; |
2182 | uint32_t tmp; |
2182 | 2183 | ||
2183 | if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { |
2184 | if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { |
2184 | printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" |
2185 | printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" |
2185 | " Bad things might happen.\n"); |
2186 | " Bad things might happen.\n"); |
2186 | } |
2187 | } |
2187 | for (i = 0; i < rdev->usec_timeout; i++) { |
2188 | for (i = 0; i < rdev->usec_timeout; i++) { |
2188 | tmp = RREG32(RADEON_RBBM_STATUS); |
2189 | tmp = RREG32(RADEON_RBBM_STATUS); |
2189 | if (!(tmp & RADEON_RBBM_ACTIVE)) { |
2190 | if (!(tmp & RADEON_RBBM_ACTIVE)) { |
2190 | return 0; |
2191 | return 0; |
2191 | } |
2192 | } |
2192 | DRM_UDELAY(1); |
2193 | DRM_UDELAY(1); |
2193 | } |
2194 | } |
2194 | return -1; |
2195 | return -1; |
2195 | } |
2196 | } |
2196 | 2197 | ||
2197 | int r100_mc_wait_for_idle(struct radeon_device *rdev) |
2198 | int r100_mc_wait_for_idle(struct radeon_device *rdev) |
2198 | { |
2199 | { |
2199 | unsigned i; |
2200 | unsigned i; |
2200 | uint32_t tmp; |
2201 | uint32_t tmp; |
2201 | 2202 | ||
2202 | for (i = 0; i < rdev->usec_timeout; i++) { |
2203 | for (i = 0; i < rdev->usec_timeout; i++) { |
2203 | /* read MC_STATUS */ |
2204 | /* read MC_STATUS */ |
2204 | tmp = RREG32(RADEON_MC_STATUS); |
2205 | tmp = RREG32(RADEON_MC_STATUS); |
2205 | if (tmp & RADEON_MC_IDLE) { |
2206 | if (tmp & RADEON_MC_IDLE) { |
2206 | return 0; |
2207 | return 0; |
2207 | } |
2208 | } |
2208 | DRM_UDELAY(1); |
2209 | DRM_UDELAY(1); |
2209 | } |
2210 | } |
2210 | return -1; |
2211 | return -1; |
2211 | } |
2212 | } |
2212 | 2213 | ||
2213 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
2214 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
2214 | { |
2215 | { |
2215 | u32 rbbm_status; |
2216 | u32 rbbm_status; |
2216 | 2217 | ||
2217 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
2218 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
2218 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { |
2219 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { |
2219 | radeon_ring_lockup_update(ring); |
2220 | radeon_ring_lockup_update(ring); |
2220 | return false; |
2221 | return false; |
2221 | } |
2222 | } |
2222 | /* force CP activities */ |
2223 | /* force CP activities */ |
2223 | radeon_ring_force_activity(rdev, ring); |
2224 | radeon_ring_force_activity(rdev, ring); |
2224 | return radeon_ring_test_lockup(rdev, ring); |
2225 | return radeon_ring_test_lockup(rdev, ring); |
2225 | } |
2226 | } |
2226 | 2227 | ||
2227 | /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
2228 | /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
2228 | void r100_enable_bm(struct radeon_device *rdev) |
2229 | void r100_enable_bm(struct radeon_device *rdev) |
2229 | { |
2230 | { |
2230 | uint32_t tmp; |
2231 | uint32_t tmp; |
2231 | /* Enable bus mastering */ |
2232 | /* Enable bus mastering */ |
2232 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
2233 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
2233 | WREG32(RADEON_BUS_CNTL, tmp); |
2234 | WREG32(RADEON_BUS_CNTL, tmp); |
2234 | } |
2235 | } |
2235 | 2236 | ||
2236 | void r100_bm_disable(struct radeon_device *rdev) |
2237 | void r100_bm_disable(struct radeon_device *rdev) |
2237 | { |
2238 | { |
2238 | u32 tmp; |
2239 | u32 tmp; |
2239 | 2240 | ||
2240 | /* disable bus mastering */ |
2241 | /* disable bus mastering */ |
2241 | tmp = RREG32(R_000030_BUS_CNTL); |
2242 | tmp = RREG32(R_000030_BUS_CNTL); |
2242 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); |
2243 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); |
2243 | mdelay(1); |
2244 | mdelay(1); |
2244 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); |
2245 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); |
2245 | mdelay(1); |
2246 | mdelay(1); |
2246 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); |
2247 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); |
2247 | tmp = RREG32(RADEON_BUS_CNTL); |
2248 | tmp = RREG32(RADEON_BUS_CNTL); |
2248 | mdelay(1); |
2249 | mdelay(1); |
2249 | pci_clear_master(rdev->pdev); |
2250 | pci_clear_master(rdev->pdev); |
2250 | mdelay(1); |
2251 | mdelay(1); |
2251 | } |
2252 | } |
2252 | 2253 | ||
2253 | int r100_asic_reset(struct radeon_device *rdev) |
2254 | int r100_asic_reset(struct radeon_device *rdev) |
2254 | { |
2255 | { |
2255 | struct r100_mc_save save; |
2256 | struct r100_mc_save save; |
2256 | u32 status, tmp; |
2257 | u32 status, tmp; |
2257 | int ret = 0; |
2258 | int ret = 0; |
2258 | 2259 | ||
2259 | status = RREG32(R_000E40_RBBM_STATUS); |
2260 | status = RREG32(R_000E40_RBBM_STATUS); |
2260 | if (!G_000E40_GUI_ACTIVE(status)) { |
2261 | if (!G_000E40_GUI_ACTIVE(status)) { |
2261 | return 0; |
2262 | return 0; |
2262 | } |
2263 | } |
2263 | r100_mc_stop(rdev, &save); |
2264 | r100_mc_stop(rdev, &save); |
2264 | status = RREG32(R_000E40_RBBM_STATUS); |
2265 | status = RREG32(R_000E40_RBBM_STATUS); |
2265 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
2266 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
2266 | /* stop CP */ |
2267 | /* stop CP */ |
2267 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
2268 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
2268 | tmp = RREG32(RADEON_CP_RB_CNTL); |
2269 | tmp = RREG32(RADEON_CP_RB_CNTL); |
2269 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
2270 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
2270 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
2271 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
2271 | WREG32(RADEON_CP_RB_WPTR, 0); |
2272 | WREG32(RADEON_CP_RB_WPTR, 0); |
2272 | WREG32(RADEON_CP_RB_CNTL, tmp); |
2273 | WREG32(RADEON_CP_RB_CNTL, tmp); |
2273 | /* save PCI state */ |
2274 | /* save PCI state */ |
2274 | // pci_save_state(rdev->pdev); |
2275 | // pci_save_state(rdev->pdev); |
2275 | /* disable bus mastering */ |
2276 | /* disable bus mastering */ |
2276 | r100_bm_disable(rdev); |
2277 | r100_bm_disable(rdev); |
2277 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | |
2278 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | |
2278 | S_0000F0_SOFT_RESET_RE(1) | |
2279 | S_0000F0_SOFT_RESET_RE(1) | |
2279 | S_0000F0_SOFT_RESET_PP(1) | |
2280 | S_0000F0_SOFT_RESET_PP(1) | |
2280 | S_0000F0_SOFT_RESET_RB(1)); |
2281 | S_0000F0_SOFT_RESET_RB(1)); |
2281 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
2282 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
2282 | mdelay(500); |
2283 | mdelay(500); |
2283 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
2284 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
2284 | mdelay(1); |
2285 | mdelay(1); |
2285 | status = RREG32(R_000E40_RBBM_STATUS); |
2286 | status = RREG32(R_000E40_RBBM_STATUS); |
2286 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
2287 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
2287 | /* reset CP */ |
2288 | /* reset CP */ |
2288 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
2289 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
2289 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
2290 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
2290 | mdelay(500); |
2291 | mdelay(500); |
2291 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
2292 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
2292 | mdelay(1); |
2293 | mdelay(1); |
2293 | status = RREG32(R_000E40_RBBM_STATUS); |
2294 | status = RREG32(R_000E40_RBBM_STATUS); |
2294 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
2295 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
2295 | /* restore PCI & busmastering */ |
2296 | /* restore PCI & busmastering */ |
2296 | // pci_restore_state(rdev->pdev); |
2297 | // pci_restore_state(rdev->pdev); |
2297 | r100_enable_bm(rdev); |
2298 | r100_enable_bm(rdev); |
2298 | /* Check if GPU is idle */ |
2299 | /* Check if GPU is idle */ |
2299 | if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || |
2300 | if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || |
2300 | G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { |
2301 | G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { |
2301 | dev_err(rdev->dev, "failed to reset GPU\n"); |
2302 | dev_err(rdev->dev, "failed to reset GPU\n"); |
2302 | ret = -1; |
2303 | ret = -1; |
2303 | } else |
2304 | } else |
2304 | dev_info(rdev->dev, "GPU reset succeed\n"); |
2305 | dev_info(rdev->dev, "GPU reset succeed\n"); |
2305 | r100_mc_resume(rdev, &save); |
2306 | r100_mc_resume(rdev, &save); |
2306 | return ret; |
2307 | return ret; |
2307 | } |
2308 | } |
2308 | 2309 | ||
2309 | void r100_set_common_regs(struct radeon_device *rdev) |
2310 | void r100_set_common_regs(struct radeon_device *rdev) |
2310 | { |
2311 | { |
2311 | struct drm_device *dev = rdev->ddev; |
2312 | struct drm_device *dev = rdev->ddev; |
2312 | bool force_dac2 = false; |
2313 | bool force_dac2 = false; |
2313 | u32 tmp; |
2314 | u32 tmp; |
2314 | 2315 | ||
2315 | /* set these so they don't interfere with anything */ |
2316 | /* set these so they don't interfere with anything */ |
2316 | WREG32(RADEON_OV0_SCALE_CNTL, 0); |
2317 | WREG32(RADEON_OV0_SCALE_CNTL, 0); |
2317 | WREG32(RADEON_SUBPIC_CNTL, 0); |
2318 | WREG32(RADEON_SUBPIC_CNTL, 0); |
2318 | WREG32(RADEON_VIPH_CONTROL, 0); |
2319 | WREG32(RADEON_VIPH_CONTROL, 0); |
2319 | WREG32(RADEON_I2C_CNTL_1, 0); |
2320 | WREG32(RADEON_I2C_CNTL_1, 0); |
2320 | WREG32(RADEON_DVI_I2C_CNTL_1, 0); |
2321 | WREG32(RADEON_DVI_I2C_CNTL_1, 0); |
2321 | WREG32(RADEON_CAP0_TRIG_CNTL, 0); |
2322 | WREG32(RADEON_CAP0_TRIG_CNTL, 0); |
2322 | WREG32(RADEON_CAP1_TRIG_CNTL, 0); |
2323 | WREG32(RADEON_CAP1_TRIG_CNTL, 0); |
2323 | 2324 | ||
2324 | /* always set up dac2 on rn50 and some rv100 as lots |
2325 | /* always set up dac2 on rn50 and some rv100 as lots |
2325 | * of servers seem to wire it up to a VGA port but |
2326 | * of servers seem to wire it up to a VGA port but |
2326 | * don't report it in the bios connector |
2327 | * don't report it in the bios connector |
2327 | * table. |
2328 | * table. |
2328 | */ |
2329 | */ |
2329 | switch (dev->pdev->device) { |
2330 | switch (dev->pdev->device) { |
2330 | /* RN50 */ |
2331 | /* RN50 */ |
2331 | case 0x515e: |
2332 | case 0x515e: |
2332 | case 0x5969: |
2333 | case 0x5969: |
2333 | force_dac2 = true; |
2334 | force_dac2 = true; |
2334 | break; |
2335 | break; |
2335 | /* RV100*/ |
2336 | /* RV100*/ |
2336 | case 0x5159: |
2337 | case 0x5159: |
2337 | case 0x515a: |
2338 | case 0x515a: |
2338 | /* DELL triple head servers */ |
2339 | /* DELL triple head servers */ |
2339 | if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && |
2340 | if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && |
2340 | ((dev->pdev->subsystem_device == 0x016c) || |
2341 | ((dev->pdev->subsystem_device == 0x016c) || |
2341 | (dev->pdev->subsystem_device == 0x016d) || |
2342 | (dev->pdev->subsystem_device == 0x016d) || |
2342 | (dev->pdev->subsystem_device == 0x016e) || |
2343 | (dev->pdev->subsystem_device == 0x016e) || |
2343 | (dev->pdev->subsystem_device == 0x016f) || |
2344 | (dev->pdev->subsystem_device == 0x016f) || |
2344 | (dev->pdev->subsystem_device == 0x0170) || |
2345 | (dev->pdev->subsystem_device == 0x0170) || |
2345 | (dev->pdev->subsystem_device == 0x017d) || |
2346 | (dev->pdev->subsystem_device == 0x017d) || |
2346 | (dev->pdev->subsystem_device == 0x017e) || |
2347 | (dev->pdev->subsystem_device == 0x017e) || |
2347 | (dev->pdev->subsystem_device == 0x0183) || |
2348 | (dev->pdev->subsystem_device == 0x0183) || |
2348 | (dev->pdev->subsystem_device == 0x018a) || |
2349 | (dev->pdev->subsystem_device == 0x018a) || |
2349 | (dev->pdev->subsystem_device == 0x019a))) |
2350 | (dev->pdev->subsystem_device == 0x019a))) |
2350 | force_dac2 = true; |
2351 | force_dac2 = true; |
2351 | break; |
2352 | break; |
2352 | } |
2353 | } |
2353 | 2354 | ||
2354 | if (force_dac2) { |
2355 | if (force_dac2) { |
2355 | u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
2356 | u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
2356 | u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
2357 | u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
2357 | u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
2358 | u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
2358 | 2359 | ||
2359 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
2360 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
2360 | enable it, even it's detected. |
2361 | enable it, even it's detected. |
2361 | */ |
2362 | */ |
2362 | 2363 | ||
2363 | /* force it to crtc0 */ |
2364 | /* force it to crtc0 */ |
2364 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; |
2365 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; |
2365 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; |
2366 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; |
2366 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
2367 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
2367 | 2368 | ||
2368 | /* set up the TV DAC */ |
2369 | /* set up the TV DAC */ |
2369 | tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | |
2370 | tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | |
2370 | RADEON_TV_DAC_STD_MASK | |
2371 | RADEON_TV_DAC_STD_MASK | |
2371 | RADEON_TV_DAC_RDACPD | |
2372 | RADEON_TV_DAC_RDACPD | |
2372 | RADEON_TV_DAC_GDACPD | |
2373 | RADEON_TV_DAC_GDACPD | |
2373 | RADEON_TV_DAC_BDACPD | |
2374 | RADEON_TV_DAC_BDACPD | |
2374 | RADEON_TV_DAC_BGADJ_MASK | |
2375 | RADEON_TV_DAC_BGADJ_MASK | |
2375 | RADEON_TV_DAC_DACADJ_MASK); |
2376 | RADEON_TV_DAC_DACADJ_MASK); |
2376 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | |
2377 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | |
2377 | RADEON_TV_DAC_NHOLD | |
2378 | RADEON_TV_DAC_NHOLD | |
2378 | RADEON_TV_DAC_STD_PS2 | |
2379 | RADEON_TV_DAC_STD_PS2 | |
2379 | (0x58 << 16)); |
2380 | (0x58 << 16)); |
2380 | 2381 | ||
2381 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
2382 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
2382 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
2383 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
2383 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
2384 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
2384 | } |
2385 | } |
2385 | 2386 | ||
2386 | /* switch PM block to ACPI mode */ |
2387 | /* switch PM block to ACPI mode */ |
2387 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); |
2388 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); |
2388 | tmp &= ~RADEON_PM_MODE_SEL; |
2389 | tmp &= ~RADEON_PM_MODE_SEL; |
2389 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); |
2390 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); |
2390 | 2391 | ||
2391 | } |
2392 | } |
2392 | 2393 | ||
2393 | /* |
2394 | /* |
2394 | * VRAM info |
2395 | * VRAM info |
2395 | */ |
2396 | */ |
2396 | static void r100_vram_get_type(struct radeon_device *rdev) |
2397 | static void r100_vram_get_type(struct radeon_device *rdev) |
2397 | { |
2398 | { |
2398 | uint32_t tmp; |
2399 | uint32_t tmp; |
2399 | 2400 | ||
2400 | rdev->mc.vram_is_ddr = false; |
2401 | rdev->mc.vram_is_ddr = false; |
2401 | if (rdev->flags & RADEON_IS_IGP) |
2402 | if (rdev->flags & RADEON_IS_IGP) |
2402 | rdev->mc.vram_is_ddr = true; |
2403 | rdev->mc.vram_is_ddr = true; |
2403 | else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) |
2404 | else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) |
2404 | rdev->mc.vram_is_ddr = true; |
2405 | rdev->mc.vram_is_ddr = true; |
2405 | if ((rdev->family == CHIP_RV100) || |
2406 | if ((rdev->family == CHIP_RV100) || |
2406 | (rdev->family == CHIP_RS100) || |
2407 | (rdev->family == CHIP_RS100) || |
2407 | (rdev->family == CHIP_RS200)) { |
2408 | (rdev->family == CHIP_RS200)) { |
2408 | tmp = RREG32(RADEON_MEM_CNTL); |
2409 | tmp = RREG32(RADEON_MEM_CNTL); |
2409 | if (tmp & RV100_HALF_MODE) { |
2410 | if (tmp & RV100_HALF_MODE) { |
2410 | rdev->mc.vram_width = 32; |
2411 | rdev->mc.vram_width = 32; |
2411 | } else { |
2412 | } else { |
2412 | rdev->mc.vram_width = 64; |
2413 | rdev->mc.vram_width = 64; |
2413 | } |
2414 | } |
2414 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
2415 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
2415 | rdev->mc.vram_width /= 4; |
2416 | rdev->mc.vram_width /= 4; |
2416 | rdev->mc.vram_is_ddr = true; |
2417 | rdev->mc.vram_is_ddr = true; |
2417 | } |
2418 | } |
2418 | } else if (rdev->family <= CHIP_RV280) { |
2419 | } else if (rdev->family <= CHIP_RV280) { |
2419 | tmp = RREG32(RADEON_MEM_CNTL); |
2420 | tmp = RREG32(RADEON_MEM_CNTL); |
2420 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { |
2421 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { |
2421 | rdev->mc.vram_width = 128; |
2422 | rdev->mc.vram_width = 128; |
2422 | } else { |
2423 | } else { |
2423 | rdev->mc.vram_width = 64; |
2424 | rdev->mc.vram_width = 64; |
2424 | } |
2425 | } |
2425 | } else { |
2426 | } else { |
2426 | /* newer IGPs */ |
2427 | /* newer IGPs */ |
2427 | rdev->mc.vram_width = 128; |
2428 | rdev->mc.vram_width = 128; |
2428 | } |
2429 | } |
2429 | } |
2430 | } |
2430 | 2431 | ||
2431 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
2432 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
2432 | { |
2433 | { |
2433 | u32 aper_size; |
2434 | u32 aper_size; |
2434 | u8 byte; |
2435 | u8 byte; |
2435 | 2436 | ||
2436 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
2437 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
2437 | 2438 | ||
2438 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, |
2439 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, |
2439 | * that is has the 2nd generation multifunction PCI interface |
2440 | * that is has the 2nd generation multifunction PCI interface |
2440 | */ |
2441 | */ |
2441 | if (rdev->family == CHIP_RV280 || |
2442 | if (rdev->family == CHIP_RV280 || |
2442 | rdev->family >= CHIP_RV350) { |
2443 | rdev->family >= CHIP_RV350) { |
2443 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, |
2444 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, |
2444 | ~RADEON_HDP_APER_CNTL); |
2445 | ~RADEON_HDP_APER_CNTL); |
2445 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); |
2446 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); |
2446 | return aper_size * 2; |
2447 | return aper_size * 2; |
2447 | } |
2448 | } |
2448 | 2449 | ||
2449 | /* Older cards have all sorts of funny issues to deal with. First |
2450 | /* Older cards have all sorts of funny issues to deal with. First |
2450 | * check if it's a multifunction card by reading the PCI config |
2451 | * check if it's a multifunction card by reading the PCI config |
2451 | * header type... Limit those to one aperture size |
2452 | * header type... Limit those to one aperture size |
2452 | */ |
2453 | */ |
2453 | // pci_read_config_byte(rdev->pdev, 0xe, &byte); |
2454 | // pci_read_config_byte(rdev->pdev, 0xe, &byte); |
2454 | // if (byte & 0x80) { |
2455 | // if (byte & 0x80) { |
2455 | // DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); |
2456 | // DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); |
2456 | // DRM_INFO("Limiting VRAM to one aperture\n"); |
2457 | // DRM_INFO("Limiting VRAM to one aperture\n"); |
2457 | // return aper_size; |
2458 | // return aper_size; |
2458 | // } |
2459 | // } |
2459 | 2460 | ||
2460 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
2461 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
2461 | * have set it up. We don't write this as it's broken on some ASICs but |
2462 | * have set it up. We don't write this as it's broken on some ASICs but |
2462 | * we expect the BIOS to have done the right thing (might be too optimistic...) |
2463 | * we expect the BIOS to have done the right thing (might be too optimistic...) |
2463 | */ |
2464 | */ |
2464 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) |
2465 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) |
2465 | return aper_size * 2; |
2466 | return aper_size * 2; |
2466 | return aper_size; |
2467 | return aper_size; |
2467 | } |
2468 | } |
2468 | 2469 | ||
2469 | void r100_vram_init_sizes(struct radeon_device *rdev) |
2470 | void r100_vram_init_sizes(struct radeon_device *rdev) |
2470 | { |
2471 | { |
2471 | u64 config_aper_size; |
2472 | u64 config_aper_size; |
2472 | 2473 | ||
2473 | /* work out accessible VRAM */ |
2474 | /* work out accessible VRAM */ |
2474 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
2475 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
2475 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
2476 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
2476 | rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); |
2477 | rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); |
2477 | /* FIXME we don't use the second aperture yet when we could use it */ |
2478 | /* FIXME we don't use the second aperture yet when we could use it */ |
2478 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) |
2479 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) |
2479 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
2480 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
2480 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
2481 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
2481 | if (rdev->flags & RADEON_IS_IGP) { |
2482 | if (rdev->flags & RADEON_IS_IGP) { |
2482 | uint32_t tom; |
2483 | uint32_t tom; |
2483 | /* read NB_TOM to get the amount of ram stolen for the GPU */ |
2484 | /* read NB_TOM to get the amount of ram stolen for the GPU */ |
2484 | tom = RREG32(RADEON_NB_TOM); |
2485 | tom = RREG32(RADEON_NB_TOM); |
2485 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
2486 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
2486 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
2487 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
2487 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
2488 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
2488 | } else { |
2489 | } else { |
2489 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
2490 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
2490 | /* Some production boards of m6 will report 0 |
2491 | /* Some production boards of m6 will report 0 |
2491 | * if it's 8 MB |
2492 | * if it's 8 MB |
2492 | */ |
2493 | */ |
2493 | if (rdev->mc.real_vram_size == 0) { |
2494 | if (rdev->mc.real_vram_size == 0) { |
2494 | rdev->mc.real_vram_size = 8192 * 1024; |
2495 | rdev->mc.real_vram_size = 8192 * 1024; |
2495 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
2496 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
2496 | } |
2497 | } |
2497 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
2498 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
2498 | * Novell bug 204882 + along with lots of ubuntu ones |
2499 | * Novell bug 204882 + along with lots of ubuntu ones |
2499 | */ |
2500 | */ |
2500 | if (rdev->mc.aper_size > config_aper_size) |
2501 | if (rdev->mc.aper_size > config_aper_size) |
2501 | config_aper_size = rdev->mc.aper_size; |
2502 | config_aper_size = rdev->mc.aper_size; |
2502 | 2503 | ||
2503 | if (config_aper_size > rdev->mc.real_vram_size) |
2504 | if (config_aper_size > rdev->mc.real_vram_size) |
2504 | rdev->mc.mc_vram_size = config_aper_size; |
2505 | rdev->mc.mc_vram_size = config_aper_size; |
2505 | else |
2506 | else |
2506 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
2507 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
2507 | } |
2508 | } |
2508 | } |
2509 | } |
2509 | 2510 | ||
2510 | void r100_vga_set_state(struct radeon_device *rdev, bool state) |
2511 | void r100_vga_set_state(struct radeon_device *rdev, bool state) |
2511 | { |
2512 | { |
2512 | uint32_t temp; |
2513 | uint32_t temp; |
2513 | 2514 | ||
2514 | temp = RREG32(RADEON_CONFIG_CNTL); |
2515 | temp = RREG32(RADEON_CONFIG_CNTL); |
2515 | if (state == false) { |
2516 | if (state == false) { |
2516 | temp &= ~RADEON_CFG_VGA_RAM_EN; |
2517 | temp &= ~RADEON_CFG_VGA_RAM_EN; |
2517 | temp |= RADEON_CFG_VGA_IO_DIS; |
2518 | temp |= RADEON_CFG_VGA_IO_DIS; |
2518 | } else { |
2519 | } else { |
2519 | temp &= ~RADEON_CFG_VGA_IO_DIS; |
2520 | temp &= ~RADEON_CFG_VGA_IO_DIS; |
2520 | } |
2521 | } |
2521 | WREG32(RADEON_CONFIG_CNTL, temp); |
2522 | WREG32(RADEON_CONFIG_CNTL, temp); |
2522 | } |
2523 | } |
2523 | 2524 | ||
2524 | static void r100_mc_init(struct radeon_device *rdev) |
2525 | static void r100_mc_init(struct radeon_device *rdev) |
2525 | { |
2526 | { |
2526 | u64 base; |
2527 | u64 base; |
2527 | 2528 | ||
2528 | r100_vram_get_type(rdev); |
2529 | r100_vram_get_type(rdev); |
2529 | r100_vram_init_sizes(rdev); |
2530 | r100_vram_init_sizes(rdev); |
2530 | base = rdev->mc.aper_base; |
2531 | base = rdev->mc.aper_base; |
2531 | if (rdev->flags & RADEON_IS_IGP) |
2532 | if (rdev->flags & RADEON_IS_IGP) |
2532 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
2533 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
2533 | radeon_vram_location(rdev, &rdev->mc, base); |
2534 | radeon_vram_location(rdev, &rdev->mc, base); |
2534 | rdev->mc.gtt_base_align = 0; |
2535 | rdev->mc.gtt_base_align = 0; |
2535 | if (!(rdev->flags & RADEON_IS_AGP)) |
2536 | if (!(rdev->flags & RADEON_IS_AGP)) |
2536 | radeon_gtt_location(rdev, &rdev->mc); |
2537 | radeon_gtt_location(rdev, &rdev->mc); |
2537 | radeon_update_bandwidth_info(rdev); |
2538 | radeon_update_bandwidth_info(rdev); |
2538 | } |
2539 | } |
2539 | 2540 | ||
2540 | 2541 | ||
2541 | /* |
2542 | /* |
2542 | * Indirect registers accessor |
2543 | * Indirect registers accessor |
2543 | */ |
2544 | */ |
2544 | void r100_pll_errata_after_index(struct radeon_device *rdev) |
2545 | void r100_pll_errata_after_index(struct radeon_device *rdev) |
2545 | { |
2546 | { |
2546 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { |
2547 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { |
2547 | (void)RREG32(RADEON_CLOCK_CNTL_DATA); |
2548 | (void)RREG32(RADEON_CLOCK_CNTL_DATA); |
2548 | (void)RREG32(RADEON_CRTC_GEN_CNTL); |
2549 | (void)RREG32(RADEON_CRTC_GEN_CNTL); |
2549 | } |
2550 | } |
2550 | } |
2551 | } |
2551 | 2552 | ||
2552 | static void r100_pll_errata_after_data(struct radeon_device *rdev) |
2553 | static void r100_pll_errata_after_data(struct radeon_device *rdev) |
2553 | { |
2554 | { |
2554 | /* This workarounds is necessary on RV100, RS100 and RS200 chips |
2555 | /* This workarounds is necessary on RV100, RS100 and RS200 chips |
2555 | * or the chip could hang on a subsequent access |
2556 | * or the chip could hang on a subsequent access |
2556 | */ |
2557 | */ |
2557 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { |
2558 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { |
2558 | mdelay(5); |
2559 | mdelay(5); |
2559 | } |
2560 | } |
2560 | 2561 | ||
2561 | /* This function is required to workaround a hardware bug in some (all?) |
2562 | /* This function is required to workaround a hardware bug in some (all?) |
2562 | * revisions of the R300. This workaround should be called after every |
2563 | * revisions of the R300. This workaround should be called after every |
2563 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
2564 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
2564 | * may not be correct. |
2565 | * may not be correct. |
2565 | */ |
2566 | */ |
2566 | if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { |
2567 | if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { |
2567 | uint32_t save, tmp; |
2568 | uint32_t save, tmp; |
2568 | 2569 | ||
2569 | save = RREG32(RADEON_CLOCK_CNTL_INDEX); |
2570 | save = RREG32(RADEON_CLOCK_CNTL_INDEX); |
2570 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
2571 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
2571 | WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); |
2572 | WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); |
2572 | tmp = RREG32(RADEON_CLOCK_CNTL_DATA); |
2573 | tmp = RREG32(RADEON_CLOCK_CNTL_DATA); |
2573 | WREG32(RADEON_CLOCK_CNTL_INDEX, save); |
2574 | WREG32(RADEON_CLOCK_CNTL_INDEX, save); |
2574 | } |
2575 | } |
2575 | } |
2576 | } |
2576 | 2577 | ||
2577 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) |
2578 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) |
2578 | { |
2579 | { |
2579 | uint32_t data; |
2580 | uint32_t data; |
2580 | 2581 | ||
2581 | WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); |
2582 | WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); |
2582 | r100_pll_errata_after_index(rdev); |
2583 | r100_pll_errata_after_index(rdev); |
2583 | data = RREG32(RADEON_CLOCK_CNTL_DATA); |
2584 | data = RREG32(RADEON_CLOCK_CNTL_DATA); |
2584 | r100_pll_errata_after_data(rdev); |
2585 | r100_pll_errata_after_data(rdev); |
2585 | return data; |
2586 | return data; |
2586 | } |
2587 | } |
2587 | 2588 | ||
2588 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
2589 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
2589 | { |
2590 | { |
2590 | WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); |
2591 | WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); |
2591 | r100_pll_errata_after_index(rdev); |
2592 | r100_pll_errata_after_index(rdev); |
2592 | WREG32(RADEON_CLOCK_CNTL_DATA, v); |
2593 | WREG32(RADEON_CLOCK_CNTL_DATA, v); |
2593 | r100_pll_errata_after_data(rdev); |
2594 | r100_pll_errata_after_data(rdev); |
2594 | } |
2595 | } |
2595 | 2596 | ||
2596 | static void r100_set_safe_registers(struct radeon_device *rdev) |
2597 | static void r100_set_safe_registers(struct radeon_device *rdev) |
2597 | { |
2598 | { |
2598 | if (ASIC_IS_RN50(rdev)) { |
2599 | if (ASIC_IS_RN50(rdev)) { |
2599 | rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; |
2600 | rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; |
2600 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); |
2601 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); |
2601 | } else if (rdev->family < CHIP_R200) { |
2602 | } else if (rdev->family < CHIP_R200) { |
2602 | rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; |
2603 | rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; |
2603 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); |
2604 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); |
2604 | } else { |
2605 | } else { |
2605 | r200_set_safe_registers(rdev); |
2606 | r200_set_safe_registers(rdev); |
2606 | } |
2607 | } |
2607 | } |
2608 | } |
2608 | 2609 | ||
2609 | /* |
2610 | /* |
2610 | * Debugfs info |
2611 | * Debugfs info |
2611 | */ |
2612 | */ |
2612 | #if defined(CONFIG_DEBUG_FS) |
2613 | #if defined(CONFIG_DEBUG_FS) |
2613 | static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) |
2614 | static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) |
2614 | { |
2615 | { |
2615 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2616 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2616 | struct drm_device *dev = node->minor->dev; |
2617 | struct drm_device *dev = node->minor->dev; |
2617 | struct radeon_device *rdev = dev->dev_private; |
2618 | struct radeon_device *rdev = dev->dev_private; |
2618 | uint32_t reg, value; |
2619 | uint32_t reg, value; |
2619 | unsigned i; |
2620 | unsigned i; |
2620 | 2621 | ||
2621 | seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); |
2622 | seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); |
2622 | seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); |
2623 | seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); |
2623 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
2624 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
2624 | for (i = 0; i < 64; i++) { |
2625 | for (i = 0; i < 64; i++) { |
2625 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); |
2626 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); |
2626 | reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; |
2627 | reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; |
2627 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); |
2628 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); |
2628 | value = RREG32(RADEON_RBBM_CMDFIFO_DATA); |
2629 | value = RREG32(RADEON_RBBM_CMDFIFO_DATA); |
2629 | seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); |
2630 | seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); |
2630 | } |
2631 | } |
2631 | return 0; |
2632 | return 0; |
2632 | } |
2633 | } |
2633 | 2634 | ||
2634 | static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) |
2635 | static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) |
2635 | { |
2636 | { |
2636 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2637 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2637 | struct drm_device *dev = node->minor->dev; |
2638 | struct drm_device *dev = node->minor->dev; |
2638 | struct radeon_device *rdev = dev->dev_private; |
2639 | struct radeon_device *rdev = dev->dev_private; |
2639 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2640 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2640 | uint32_t rdp, wdp; |
2641 | uint32_t rdp, wdp; |
2641 | unsigned count, i, j; |
2642 | unsigned count, i, j; |
2642 | 2643 | ||
2643 | radeon_ring_free_size(rdev, ring); |
2644 | radeon_ring_free_size(rdev, ring); |
2644 | rdp = RREG32(RADEON_CP_RB_RPTR); |
2645 | rdp = RREG32(RADEON_CP_RB_RPTR); |
2645 | wdp = RREG32(RADEON_CP_RB_WPTR); |
2646 | wdp = RREG32(RADEON_CP_RB_WPTR); |
2646 | count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; |
2647 | count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; |
2647 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
2648 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
2648 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); |
2649 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); |
2649 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); |
2650 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); |
2650 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
2651 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
2651 | seq_printf(m, "%u dwords in ring\n", count); |
2652 | seq_printf(m, "%u dwords in ring\n", count); |
2652 | for (j = 0; j <= count; j++) { |
2653 | for (j = 0; j <= count; j++) { |
2653 | i = (rdp + j) & ring->ptr_mask; |
2654 | i = (rdp + j) & ring->ptr_mask; |
2654 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); |
2655 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); |
2655 | } |
2656 | } |
2656 | return 0; |
2657 | return 0; |
2657 | } |
2658 | } |
2658 | 2659 | ||
2659 | 2660 | ||
2660 | static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) |
2661 | static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) |
2661 | { |
2662 | { |
2662 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2663 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2663 | struct drm_device *dev = node->minor->dev; |
2664 | struct drm_device *dev = node->minor->dev; |
2664 | struct radeon_device *rdev = dev->dev_private; |
2665 | struct radeon_device *rdev = dev->dev_private; |
2665 | uint32_t csq_stat, csq2_stat, tmp; |
2666 | uint32_t csq_stat, csq2_stat, tmp; |
2666 | unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; |
2667 | unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; |
2667 | unsigned i; |
2668 | unsigned i; |
2668 | 2669 | ||
2669 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
2670 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
2670 | seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); |
2671 | seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); |
2671 | csq_stat = RREG32(RADEON_CP_CSQ_STAT); |
2672 | csq_stat = RREG32(RADEON_CP_CSQ_STAT); |
2672 | csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); |
2673 | csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); |
2673 | r_rptr = (csq_stat >> 0) & 0x3ff; |
2674 | r_rptr = (csq_stat >> 0) & 0x3ff; |
2674 | r_wptr = (csq_stat >> 10) & 0x3ff; |
2675 | r_wptr = (csq_stat >> 10) & 0x3ff; |
2675 | ib1_rptr = (csq_stat >> 20) & 0x3ff; |
2676 | ib1_rptr = (csq_stat >> 20) & 0x3ff; |
2676 | ib1_wptr = (csq2_stat >> 0) & 0x3ff; |
2677 | ib1_wptr = (csq2_stat >> 0) & 0x3ff; |
2677 | ib2_rptr = (csq2_stat >> 10) & 0x3ff; |
2678 | ib2_rptr = (csq2_stat >> 10) & 0x3ff; |
2678 | ib2_wptr = (csq2_stat >> 20) & 0x3ff; |
2679 | ib2_wptr = (csq2_stat >> 20) & 0x3ff; |
2679 | seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); |
2680 | seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); |
2680 | seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); |
2681 | seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); |
2681 | seq_printf(m, "Ring rptr %u\n", r_rptr); |
2682 | seq_printf(m, "Ring rptr %u\n", r_rptr); |
2682 | seq_printf(m, "Ring wptr %u\n", r_wptr); |
2683 | seq_printf(m, "Ring wptr %u\n", r_wptr); |
2683 | seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); |
2684 | seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); |
2684 | seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); |
2685 | seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); |
2685 | seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); |
2686 | seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); |
2686 | seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); |
2687 | seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); |
2687 | /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms |
2688 | /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms |
2688 | * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ |
2689 | * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ |
2689 | seq_printf(m, "Ring fifo:\n"); |
2690 | seq_printf(m, "Ring fifo:\n"); |
2690 | for (i = 0; i < 256; i++) { |
2691 | for (i = 0; i < 256; i++) { |
2691 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
2692 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
2692 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
2693 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
2693 | seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); |
2694 | seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); |
2694 | } |
2695 | } |
2695 | seq_printf(m, "Indirect1 fifo:\n"); |
2696 | seq_printf(m, "Indirect1 fifo:\n"); |
2696 | for (i = 256; i <= 512; i++) { |
2697 | for (i = 256; i <= 512; i++) { |
2697 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
2698 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
2698 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
2699 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
2699 | seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); |
2700 | seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); |
2700 | } |
2701 | } |
2701 | seq_printf(m, "Indirect2 fifo:\n"); |
2702 | seq_printf(m, "Indirect2 fifo:\n"); |
2702 | for (i = 640; i < ib1_wptr; i++) { |
2703 | for (i = 640; i < ib1_wptr; i++) { |
2703 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
2704 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
2704 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
2705 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
2705 | seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); |
2706 | seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); |
2706 | } |
2707 | } |
2707 | return 0; |
2708 | return 0; |
2708 | } |
2709 | } |
2709 | 2710 | ||
2710 | static int r100_debugfs_mc_info(struct seq_file *m, void *data) |
2711 | static int r100_debugfs_mc_info(struct seq_file *m, void *data) |
2711 | { |
2712 | { |
2712 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2713 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2713 | struct drm_device *dev = node->minor->dev; |
2714 | struct drm_device *dev = node->minor->dev; |
2714 | struct radeon_device *rdev = dev->dev_private; |
2715 | struct radeon_device *rdev = dev->dev_private; |
2715 | uint32_t tmp; |
2716 | uint32_t tmp; |
2716 | 2717 | ||
2717 | tmp = RREG32(RADEON_CONFIG_MEMSIZE); |
2718 | tmp = RREG32(RADEON_CONFIG_MEMSIZE); |
2718 | seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); |
2719 | seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); |
2719 | tmp = RREG32(RADEON_MC_FB_LOCATION); |
2720 | tmp = RREG32(RADEON_MC_FB_LOCATION); |
2720 | seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); |
2721 | seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); |
2721 | tmp = RREG32(RADEON_BUS_CNTL); |
2722 | tmp = RREG32(RADEON_BUS_CNTL); |
2722 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
2723 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
2723 | tmp = RREG32(RADEON_MC_AGP_LOCATION); |
2724 | tmp = RREG32(RADEON_MC_AGP_LOCATION); |
2724 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
2725 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
2725 | tmp = RREG32(RADEON_AGP_BASE); |
2726 | tmp = RREG32(RADEON_AGP_BASE); |
2726 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
2727 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
2727 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
2728 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
2728 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
2729 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
2729 | tmp = RREG32(0x01D0); |
2730 | tmp = RREG32(0x01D0); |
2730 | seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); |
2731 | seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); |
2731 | tmp = RREG32(RADEON_AIC_LO_ADDR); |
2732 | tmp = RREG32(RADEON_AIC_LO_ADDR); |
2732 | seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); |
2733 | seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); |
2733 | tmp = RREG32(RADEON_AIC_HI_ADDR); |
2734 | tmp = RREG32(RADEON_AIC_HI_ADDR); |
2734 | seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); |
2735 | seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); |
2735 | tmp = RREG32(0x01E4); |
2736 | tmp = RREG32(0x01E4); |
2736 | seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); |
2737 | seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); |
2737 | return 0; |
2738 | return 0; |
2738 | } |
2739 | } |
2739 | 2740 | ||
2740 | static struct drm_info_list r100_debugfs_rbbm_list[] = { |
2741 | static struct drm_info_list r100_debugfs_rbbm_list[] = { |
2741 | {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, |
2742 | {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, |
2742 | }; |
2743 | }; |
2743 | 2744 | ||
2744 | static struct drm_info_list r100_debugfs_cp_list[] = { |
2745 | static struct drm_info_list r100_debugfs_cp_list[] = { |
2745 | {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, |
2746 | {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, |
2746 | {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, |
2747 | {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, |
2747 | }; |
2748 | }; |
2748 | 2749 | ||
2749 | static struct drm_info_list r100_debugfs_mc_info_list[] = { |
2750 | static struct drm_info_list r100_debugfs_mc_info_list[] = { |
2750 | {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, |
2751 | {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, |
2751 | }; |
2752 | }; |
2752 | #endif |
2753 | #endif |
2753 | 2754 | ||
2754 | int r100_debugfs_rbbm_init(struct radeon_device *rdev) |
2755 | int r100_debugfs_rbbm_init(struct radeon_device *rdev) |
2755 | { |
2756 | { |
2756 | #if defined(CONFIG_DEBUG_FS) |
2757 | #if defined(CONFIG_DEBUG_FS) |
2757 | return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); |
2758 | return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); |
2758 | #else |
2759 | #else |
2759 | return 0; |
2760 | return 0; |
2760 | #endif |
2761 | #endif |
2761 | } |
2762 | } |
2762 | 2763 | ||
2763 | int r100_debugfs_cp_init(struct radeon_device *rdev) |
2764 | int r100_debugfs_cp_init(struct radeon_device *rdev) |
2764 | { |
2765 | { |
2765 | #if defined(CONFIG_DEBUG_FS) |
2766 | #if defined(CONFIG_DEBUG_FS) |
2766 | return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); |
2767 | return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); |
2767 | #else |
2768 | #else |
2768 | return 0; |
2769 | return 0; |
2769 | #endif |
2770 | #endif |
2770 | } |
2771 | } |
2771 | 2772 | ||
2772 | int r100_debugfs_mc_info_init(struct radeon_device *rdev) |
2773 | int r100_debugfs_mc_info_init(struct radeon_device *rdev) |
2773 | { |
2774 | { |
2774 | #if defined(CONFIG_DEBUG_FS) |
2775 | #if defined(CONFIG_DEBUG_FS) |
2775 | return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); |
2776 | return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); |
2776 | #else |
2777 | #else |
2777 | return 0; |
2778 | return 0; |
2778 | #endif |
2779 | #endif |
2779 | } |
2780 | } |
2780 | 2781 | ||
2781 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
2782 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
2782 | uint32_t tiling_flags, uint32_t pitch, |
2783 | uint32_t tiling_flags, uint32_t pitch, |
2783 | uint32_t offset, uint32_t obj_size) |
2784 | uint32_t offset, uint32_t obj_size) |
2784 | { |
2785 | { |
2785 | int surf_index = reg * 16; |
2786 | int surf_index = reg * 16; |
2786 | int flags = 0; |
2787 | int flags = 0; |
2787 | 2788 | ||
2788 | if (rdev->family <= CHIP_RS200) { |
2789 | if (rdev->family <= CHIP_RS200) { |
2789 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
2790 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
2790 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
2791 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
2791 | flags |= RADEON_SURF_TILE_COLOR_BOTH; |
2792 | flags |= RADEON_SURF_TILE_COLOR_BOTH; |
2792 | if (tiling_flags & RADEON_TILING_MACRO) |
2793 | if (tiling_flags & RADEON_TILING_MACRO) |
2793 | flags |= RADEON_SURF_TILE_COLOR_MACRO; |
2794 | flags |= RADEON_SURF_TILE_COLOR_MACRO; |
2794 | } else if (rdev->family <= CHIP_RV280) { |
2795 | } else if (rdev->family <= CHIP_RV280) { |
2795 | if (tiling_flags & (RADEON_TILING_MACRO)) |
2796 | if (tiling_flags & (RADEON_TILING_MACRO)) |
2796 | flags |= R200_SURF_TILE_COLOR_MACRO; |
2797 | flags |= R200_SURF_TILE_COLOR_MACRO; |
2797 | if (tiling_flags & RADEON_TILING_MICRO) |
2798 | if (tiling_flags & RADEON_TILING_MICRO) |
2798 | flags |= R200_SURF_TILE_COLOR_MICRO; |
2799 | flags |= R200_SURF_TILE_COLOR_MICRO; |
2799 | } else { |
2800 | } else { |
2800 | if (tiling_flags & RADEON_TILING_MACRO) |
2801 | if (tiling_flags & RADEON_TILING_MACRO) |
2801 | flags |= R300_SURF_TILE_MACRO; |
2802 | flags |= R300_SURF_TILE_MACRO; |
2802 | if (tiling_flags & RADEON_TILING_MICRO) |
2803 | if (tiling_flags & RADEON_TILING_MICRO) |
2803 | flags |= R300_SURF_TILE_MICRO; |
2804 | flags |= R300_SURF_TILE_MICRO; |
2804 | } |
2805 | } |
2805 | 2806 | ||
2806 | if (tiling_flags & RADEON_TILING_SWAP_16BIT) |
2807 | if (tiling_flags & RADEON_TILING_SWAP_16BIT) |
2807 | flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; |
2808 | flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; |
2808 | if (tiling_flags & RADEON_TILING_SWAP_32BIT) |
2809 | if (tiling_flags & RADEON_TILING_SWAP_32BIT) |
2809 | flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; |
2810 | flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; |
2810 | 2811 | ||
2811 | /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */ |
2812 | /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */ |
2812 | if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) { |
2813 | if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) { |
2813 | if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) |
2814 | if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) |
2814 | if (ASIC_IS_RN50(rdev)) |
2815 | if (ASIC_IS_RN50(rdev)) |
2815 | pitch /= 16; |
2816 | pitch /= 16; |
2816 | } |
2817 | } |
2817 | 2818 | ||
2818 | /* r100/r200 divide by 16 */ |
2819 | /* r100/r200 divide by 16 */ |
2819 | if (rdev->family < CHIP_R300) |
2820 | if (rdev->family < CHIP_R300) |
2820 | flags |= pitch / 16; |
2821 | flags |= pitch / 16; |
2821 | else |
2822 | else |
2822 | flags |= pitch / 8; |
2823 | flags |= pitch / 8; |
2823 | 2824 | ||
2824 | 2825 | ||
2825 | DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
2826 | DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
2826 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); |
2827 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); |
2827 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); |
2828 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); |
2828 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); |
2829 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); |
2829 | return 0; |
2830 | return 0; |
2830 | } |
2831 | } |
2831 | 2832 | ||
2832 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) |
2833 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) |
2833 | { |
2834 | { |
2834 | int surf_index = reg * 16; |
2835 | int surf_index = reg * 16; |
2835 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); |
2836 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); |
2836 | } |
2837 | } |
2837 | 2838 | ||
2838 | void r100_bandwidth_update(struct radeon_device *rdev) |
2839 | void r100_bandwidth_update(struct radeon_device *rdev) |
2839 | { |
2840 | { |
2840 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; |
2841 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; |
2841 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; |
2842 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; |
2842 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; |
2843 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; |
2843 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; |
2844 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; |
2844 | fixed20_12 memtcas_ff[8] = { |
2845 | fixed20_12 memtcas_ff[8] = { |
2845 | dfixed_init(1), |
2846 | dfixed_init(1), |
2846 | dfixed_init(2), |
2847 | dfixed_init(2), |
2847 | dfixed_init(3), |
2848 | dfixed_init(3), |
2848 | dfixed_init(0), |
2849 | dfixed_init(0), |
2849 | dfixed_init_half(1), |
2850 | dfixed_init_half(1), |
2850 | dfixed_init_half(2), |
2851 | dfixed_init_half(2), |
2851 | dfixed_init(0), |
2852 | dfixed_init(0), |
2852 | }; |
2853 | }; |
2853 | fixed20_12 memtcas_rs480_ff[8] = { |
2854 | fixed20_12 memtcas_rs480_ff[8] = { |
2854 | dfixed_init(0), |
2855 | dfixed_init(0), |
2855 | dfixed_init(1), |
2856 | dfixed_init(1), |
2856 | dfixed_init(2), |
2857 | dfixed_init(2), |
2857 | dfixed_init(3), |
2858 | dfixed_init(3), |
2858 | dfixed_init(0), |
2859 | dfixed_init(0), |
2859 | dfixed_init_half(1), |
2860 | dfixed_init_half(1), |
2860 | dfixed_init_half(2), |
2861 | dfixed_init_half(2), |
2861 | dfixed_init_half(3), |
2862 | dfixed_init_half(3), |
2862 | }; |
2863 | }; |
2863 | fixed20_12 memtcas2_ff[8] = { |
2864 | fixed20_12 memtcas2_ff[8] = { |
2864 | dfixed_init(0), |
2865 | dfixed_init(0), |
2865 | dfixed_init(1), |
2866 | dfixed_init(1), |
2866 | dfixed_init(2), |
2867 | dfixed_init(2), |
2867 | dfixed_init(3), |
2868 | dfixed_init(3), |
2868 | dfixed_init(4), |
2869 | dfixed_init(4), |
2869 | dfixed_init(5), |
2870 | dfixed_init(5), |
2870 | dfixed_init(6), |
2871 | dfixed_init(6), |
2871 | dfixed_init(7), |
2872 | dfixed_init(7), |
2872 | }; |
2873 | }; |
2873 | fixed20_12 memtrbs[8] = { |
2874 | fixed20_12 memtrbs[8] = { |
2874 | dfixed_init(1), |
2875 | dfixed_init(1), |
2875 | dfixed_init_half(1), |
2876 | dfixed_init_half(1), |
2876 | dfixed_init(2), |
2877 | dfixed_init(2), |
2877 | dfixed_init_half(2), |
2878 | dfixed_init_half(2), |
2878 | dfixed_init(3), |
2879 | dfixed_init(3), |
2879 | dfixed_init_half(3), |
2880 | dfixed_init_half(3), |
2880 | dfixed_init(4), |
2881 | dfixed_init(4), |
2881 | dfixed_init_half(4) |
2882 | dfixed_init_half(4) |
2882 | }; |
2883 | }; |
2883 | fixed20_12 memtrbs_r4xx[8] = { |
2884 | fixed20_12 memtrbs_r4xx[8] = { |
2884 | dfixed_init(4), |
2885 | dfixed_init(4), |
2885 | dfixed_init(5), |
2886 | dfixed_init(5), |
2886 | dfixed_init(6), |
2887 | dfixed_init(6), |
2887 | dfixed_init(7), |
2888 | dfixed_init(7), |
2888 | dfixed_init(8), |
2889 | dfixed_init(8), |
2889 | dfixed_init(9), |
2890 | dfixed_init(9), |
2890 | dfixed_init(10), |
2891 | dfixed_init(10), |
2891 | dfixed_init(11) |
2892 | dfixed_init(11) |
2892 | }; |
2893 | }; |
2893 | fixed20_12 min_mem_eff; |
2894 | fixed20_12 min_mem_eff; |
2894 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; |
2895 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; |
2895 | fixed20_12 cur_latency_mclk, cur_latency_sclk; |
2896 | fixed20_12 cur_latency_mclk, cur_latency_sclk; |
2896 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, |
2897 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, |
2897 | disp_drain_rate2, read_return_rate; |
2898 | disp_drain_rate2, read_return_rate; |
2898 | fixed20_12 time_disp1_drop_priority; |
2899 | fixed20_12 time_disp1_drop_priority; |
2899 | int c; |
2900 | int c; |
2900 | int cur_size = 16; /* in octawords */ |
2901 | int cur_size = 16; /* in octawords */ |
2901 | int critical_point = 0, critical_point2; |
2902 | int critical_point = 0, critical_point2; |
2902 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ |
2903 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ |
2903 | int stop_req, max_stop_req; |
2904 | int stop_req, max_stop_req; |
2904 | struct drm_display_mode *mode1 = NULL; |
2905 | struct drm_display_mode *mode1 = NULL; |
2905 | struct drm_display_mode *mode2 = NULL; |
2906 | struct drm_display_mode *mode2 = NULL; |
2906 | uint32_t pixel_bytes1 = 0; |
2907 | uint32_t pixel_bytes1 = 0; |
2907 | uint32_t pixel_bytes2 = 0; |
2908 | uint32_t pixel_bytes2 = 0; |
2908 | 2909 | ||
2909 | radeon_update_display_priority(rdev); |
2910 | radeon_update_display_priority(rdev); |
2910 | 2911 | ||
2911 | if (rdev->mode_info.crtcs[0]->base.enabled) { |
2912 | if (rdev->mode_info.crtcs[0]->base.enabled) { |
2912 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; |
2913 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; |
2913 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; |
2914 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; |
2914 | } |
2915 | } |
2915 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
2916 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
2916 | if (rdev->mode_info.crtcs[1]->base.enabled) { |
2917 | if (rdev->mode_info.crtcs[1]->base.enabled) { |
2917 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; |
2918 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; |
2918 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; |
2919 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; |
2919 | } |
2920 | } |
2920 | } |
2921 | } |
2921 | 2922 | ||
2922 | min_mem_eff.full = dfixed_const_8(0); |
2923 | min_mem_eff.full = dfixed_const_8(0); |
2923 | /* get modes */ |
2924 | /* get modes */ |
2924 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { |
2925 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { |
2925 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); |
2926 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); |
2926 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); |
2927 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); |
2927 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); |
2928 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); |
2928 | /* check crtc enables */ |
2929 | /* check crtc enables */ |
2929 | if (mode2) |
2930 | if (mode2) |
2930 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); |
2931 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); |
2931 | if (mode1) |
2932 | if (mode1) |
2932 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); |
2933 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); |
2933 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); |
2934 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); |
2934 | } |
2935 | } |
2935 | 2936 | ||
2936 | /* |
2937 | /* |
2937 | * determine is there is enough bw for current mode |
2938 | * determine is there is enough bw for current mode |
2938 | */ |
2939 | */ |
2939 | sclk_ff = rdev->pm.sclk; |
2940 | sclk_ff = rdev->pm.sclk; |
2940 | mclk_ff = rdev->pm.mclk; |
2941 | mclk_ff = rdev->pm.mclk; |
2941 | 2942 | ||
2942 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
2943 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
2943 | temp_ff.full = dfixed_const(temp); |
2944 | temp_ff.full = dfixed_const(temp); |
2944 | mem_bw.full = dfixed_mul(mclk_ff, temp_ff); |
2945 | mem_bw.full = dfixed_mul(mclk_ff, temp_ff); |
2945 | 2946 | ||
2946 | pix_clk.full = 0; |
2947 | pix_clk.full = 0; |
2947 | pix_clk2.full = 0; |
2948 | pix_clk2.full = 0; |
2948 | peak_disp_bw.full = 0; |
2949 | peak_disp_bw.full = 0; |
2949 | if (mode1) { |
2950 | if (mode1) { |
2950 | temp_ff.full = dfixed_const(1000); |
2951 | temp_ff.full = dfixed_const(1000); |
2951 | pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ |
2952 | pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ |
2952 | pix_clk.full = dfixed_div(pix_clk, temp_ff); |
2953 | pix_clk.full = dfixed_div(pix_clk, temp_ff); |
2953 | temp_ff.full = dfixed_const(pixel_bytes1); |
2954 | temp_ff.full = dfixed_const(pixel_bytes1); |
2954 | peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); |
2955 | peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); |
2955 | } |
2956 | } |
2956 | if (mode2) { |
2957 | if (mode2) { |
2957 | temp_ff.full = dfixed_const(1000); |
2958 | temp_ff.full = dfixed_const(1000); |
2958 | pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ |
2959 | pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ |
2959 | pix_clk2.full = dfixed_div(pix_clk2, temp_ff); |
2960 | pix_clk2.full = dfixed_div(pix_clk2, temp_ff); |
2960 | temp_ff.full = dfixed_const(pixel_bytes2); |
2961 | temp_ff.full = dfixed_const(pixel_bytes2); |
2961 | peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); |
2962 | peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); |
2962 | } |
2963 | } |
2963 | 2964 | ||
2964 | mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); |
2965 | mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); |
2965 | if (peak_disp_bw.full >= mem_bw.full) { |
2966 | if (peak_disp_bw.full >= mem_bw.full) { |
2966 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" |
2967 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" |
2967 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); |
2968 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); |
2968 | } |
2969 | } |
2969 | 2970 | ||
2970 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ |
2971 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ |
2971 | temp = RREG32(RADEON_MEM_TIMING_CNTL); |
2972 | temp = RREG32(RADEON_MEM_TIMING_CNTL); |
2972 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ |
2973 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ |
2973 | mem_trcd = ((temp >> 2) & 0x3) + 1; |
2974 | mem_trcd = ((temp >> 2) & 0x3) + 1; |
2974 | mem_trp = ((temp & 0x3)) + 1; |
2975 | mem_trp = ((temp & 0x3)) + 1; |
2975 | mem_tras = ((temp & 0x70) >> 4) + 1; |
2976 | mem_tras = ((temp & 0x70) >> 4) + 1; |
2976 | } else if (rdev->family == CHIP_R300 || |
2977 | } else if (rdev->family == CHIP_R300 || |
2977 | rdev->family == CHIP_R350) { /* r300, r350 */ |
2978 | rdev->family == CHIP_R350) { /* r300, r350 */ |
2978 | mem_trcd = (temp & 0x7) + 1; |
2979 | mem_trcd = (temp & 0x7) + 1; |
2979 | mem_trp = ((temp >> 8) & 0x7) + 1; |
2980 | mem_trp = ((temp >> 8) & 0x7) + 1; |
2980 | mem_tras = ((temp >> 11) & 0xf) + 4; |
2981 | mem_tras = ((temp >> 11) & 0xf) + 4; |
2981 | } else if (rdev->family == CHIP_RV350 || |
2982 | } else if (rdev->family == CHIP_RV350 || |
2982 | rdev->family <= CHIP_RV380) { |
2983 | rdev->family <= CHIP_RV380) { |
2983 | /* rv3x0 */ |
2984 | /* rv3x0 */ |
2984 | mem_trcd = (temp & 0x7) + 3; |
2985 | mem_trcd = (temp & 0x7) + 3; |
2985 | mem_trp = ((temp >> 8) & 0x7) + 3; |
2986 | mem_trp = ((temp >> 8) & 0x7) + 3; |
2986 | mem_tras = ((temp >> 11) & 0xf) + 6; |
2987 | mem_tras = ((temp >> 11) & 0xf) + 6; |
2987 | } else if (rdev->family == CHIP_R420 || |
2988 | } else if (rdev->family == CHIP_R420 || |
2988 | rdev->family == CHIP_R423 || |
2989 | rdev->family == CHIP_R423 || |
2989 | rdev->family == CHIP_RV410) { |
2990 | rdev->family == CHIP_RV410) { |
2990 | /* r4xx */ |
2991 | /* r4xx */ |
2991 | mem_trcd = (temp & 0xf) + 3; |
2992 | mem_trcd = (temp & 0xf) + 3; |
2992 | if (mem_trcd > 15) |
2993 | if (mem_trcd > 15) |
2993 | mem_trcd = 15; |
2994 | mem_trcd = 15; |
2994 | mem_trp = ((temp >> 8) & 0xf) + 3; |
2995 | mem_trp = ((temp >> 8) & 0xf) + 3; |
2995 | if (mem_trp > 15) |
2996 | if (mem_trp > 15) |
2996 | mem_trp = 15; |
2997 | mem_trp = 15; |
2997 | mem_tras = ((temp >> 12) & 0x1f) + 6; |
2998 | mem_tras = ((temp >> 12) & 0x1f) + 6; |
2998 | if (mem_tras > 31) |
2999 | if (mem_tras > 31) |
2999 | mem_tras = 31; |
3000 | mem_tras = 31; |
3000 | } else { /* RV200, R200 */ |
3001 | } else { /* RV200, R200 */ |
3001 | mem_trcd = (temp & 0x7) + 1; |
3002 | mem_trcd = (temp & 0x7) + 1; |
3002 | mem_trp = ((temp >> 8) & 0x7) + 1; |
3003 | mem_trp = ((temp >> 8) & 0x7) + 1; |
3003 | mem_tras = ((temp >> 12) & 0xf) + 4; |
3004 | mem_tras = ((temp >> 12) & 0xf) + 4; |
3004 | } |
3005 | } |
3005 | /* convert to FF */ |
3006 | /* convert to FF */ |
3006 | trcd_ff.full = dfixed_const(mem_trcd); |
3007 | trcd_ff.full = dfixed_const(mem_trcd); |
3007 | trp_ff.full = dfixed_const(mem_trp); |
3008 | trp_ff.full = dfixed_const(mem_trp); |
3008 | tras_ff.full = dfixed_const(mem_tras); |
3009 | tras_ff.full = dfixed_const(mem_tras); |
3009 | 3010 | ||
3010 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
3011 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
3011 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
3012 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
3012 | data = (temp & (7 << 20)) >> 20; |
3013 | data = (temp & (7 << 20)) >> 20; |
3013 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { |
3014 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { |
3014 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ |
3015 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ |
3015 | tcas_ff = memtcas_rs480_ff[data]; |
3016 | tcas_ff = memtcas_rs480_ff[data]; |
3016 | else |
3017 | else |
3017 | tcas_ff = memtcas_ff[data]; |
3018 | tcas_ff = memtcas_ff[data]; |
3018 | } else |
3019 | } else |
3019 | tcas_ff = memtcas2_ff[data]; |
3020 | tcas_ff = memtcas2_ff[data]; |
3020 | 3021 | ||
3021 | if (rdev->family == CHIP_RS400 || |
3022 | if (rdev->family == CHIP_RS400 || |
3022 | rdev->family == CHIP_RS480) { |
3023 | rdev->family == CHIP_RS480) { |
3023 | /* extra cas latency stored in bits 23-25 0-4 clocks */ |
3024 | /* extra cas latency stored in bits 23-25 0-4 clocks */ |
3024 | data = (temp >> 23) & 0x7; |
3025 | data = (temp >> 23) & 0x7; |
3025 | if (data < 5) |
3026 | if (data < 5) |
3026 | tcas_ff.full += dfixed_const(data); |
3027 | tcas_ff.full += dfixed_const(data); |
3027 | } |
3028 | } |
3028 | 3029 | ||
3029 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
3030 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
3030 | /* on the R300, Tcas is included in Trbs. |
3031 | /* on the R300, Tcas is included in Trbs. |
3031 | */ |
3032 | */ |
3032 | temp = RREG32(RADEON_MEM_CNTL); |
3033 | temp = RREG32(RADEON_MEM_CNTL); |
3033 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); |
3034 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); |
3034 | if (data == 1) { |
3035 | if (data == 1) { |
3035 | if (R300_MEM_USE_CD_CH_ONLY & temp) { |
3036 | if (R300_MEM_USE_CD_CH_ONLY & temp) { |
3036 | temp = RREG32(R300_MC_IND_INDEX); |
3037 | temp = RREG32(R300_MC_IND_INDEX); |
3037 | temp &= ~R300_MC_IND_ADDR_MASK; |
3038 | temp &= ~R300_MC_IND_ADDR_MASK; |
3038 | temp |= R300_MC_READ_CNTL_CD_mcind; |
3039 | temp |= R300_MC_READ_CNTL_CD_mcind; |
3039 | WREG32(R300_MC_IND_INDEX, temp); |
3040 | WREG32(R300_MC_IND_INDEX, temp); |
3040 | temp = RREG32(R300_MC_IND_DATA); |
3041 | temp = RREG32(R300_MC_IND_DATA); |
3041 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); |
3042 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); |
3042 | } else { |
3043 | } else { |
3043 | temp = RREG32(R300_MC_READ_CNTL_AB); |
3044 | temp = RREG32(R300_MC_READ_CNTL_AB); |
3044 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
3045 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
3045 | } |
3046 | } |
3046 | } else { |
3047 | } else { |
3047 | temp = RREG32(R300_MC_READ_CNTL_AB); |
3048 | temp = RREG32(R300_MC_READ_CNTL_AB); |
3048 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
3049 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
3049 | } |
3050 | } |
3050 | if (rdev->family == CHIP_RV410 || |
3051 | if (rdev->family == CHIP_RV410 || |
3051 | rdev->family == CHIP_R420 || |
3052 | rdev->family == CHIP_R420 || |
3052 | rdev->family == CHIP_R423) |
3053 | rdev->family == CHIP_R423) |
3053 | trbs_ff = memtrbs_r4xx[data]; |
3054 | trbs_ff = memtrbs_r4xx[data]; |
3054 | else |
3055 | else |
3055 | trbs_ff = memtrbs[data]; |
3056 | trbs_ff = memtrbs[data]; |
3056 | tcas_ff.full += trbs_ff.full; |
3057 | tcas_ff.full += trbs_ff.full; |
3057 | } |
3058 | } |
3058 | 3059 | ||
3059 | sclk_eff_ff.full = sclk_ff.full; |
3060 | sclk_eff_ff.full = sclk_ff.full; |
3060 | 3061 | ||
3061 | if (rdev->flags & RADEON_IS_AGP) { |
3062 | if (rdev->flags & RADEON_IS_AGP) { |
3062 | fixed20_12 agpmode_ff; |
3063 | fixed20_12 agpmode_ff; |
3063 | agpmode_ff.full = dfixed_const(radeon_agpmode); |
3064 | agpmode_ff.full = dfixed_const(radeon_agpmode); |
3064 | temp_ff.full = dfixed_const_666(16); |
3065 | temp_ff.full = dfixed_const_666(16); |
3065 | sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); |
3066 | sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); |
3066 | } |
3067 | } |
3067 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ |
3068 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ |
3068 | 3069 | ||
3069 | if (ASIC_IS_R300(rdev)) { |
3070 | if (ASIC_IS_R300(rdev)) { |
3070 | sclk_delay_ff.full = dfixed_const(250); |
3071 | sclk_delay_ff.full = dfixed_const(250); |
3071 | } else { |
3072 | } else { |
3072 | if ((rdev->family == CHIP_RV100) || |
3073 | if ((rdev->family == CHIP_RV100) || |
3073 | rdev->flags & RADEON_IS_IGP) { |
3074 | rdev->flags & RADEON_IS_IGP) { |
3074 | if (rdev->mc.vram_is_ddr) |
3075 | if (rdev->mc.vram_is_ddr) |
3075 | sclk_delay_ff.full = dfixed_const(41); |
3076 | sclk_delay_ff.full = dfixed_const(41); |
3076 | else |
3077 | else |
3077 | sclk_delay_ff.full = dfixed_const(33); |
3078 | sclk_delay_ff.full = dfixed_const(33); |
3078 | } else { |
3079 | } else { |
3079 | if (rdev->mc.vram_width == 128) |
3080 | if (rdev->mc.vram_width == 128) |
3080 | sclk_delay_ff.full = dfixed_const(57); |
3081 | sclk_delay_ff.full = dfixed_const(57); |
3081 | else |
3082 | else |
3082 | sclk_delay_ff.full = dfixed_const(41); |
3083 | sclk_delay_ff.full = dfixed_const(41); |
3083 | } |
3084 | } |
3084 | } |
3085 | } |
3085 | 3086 | ||
3086 | mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); |
3087 | mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); |
3087 | 3088 | ||
3088 | if (rdev->mc.vram_is_ddr) { |
3089 | if (rdev->mc.vram_is_ddr) { |
3089 | if (rdev->mc.vram_width == 32) { |
3090 | if (rdev->mc.vram_width == 32) { |
3090 | k1.full = dfixed_const(40); |
3091 | k1.full = dfixed_const(40); |
3091 | c = 3; |
3092 | c = 3; |
3092 | } else { |
3093 | } else { |
3093 | k1.full = dfixed_const(20); |
3094 | k1.full = dfixed_const(20); |
3094 | c = 1; |
3095 | c = 1; |
3095 | } |
3096 | } |
3096 | } else { |
3097 | } else { |
3097 | k1.full = dfixed_const(40); |
3098 | k1.full = dfixed_const(40); |
3098 | c = 3; |
3099 | c = 3; |
3099 | } |
3100 | } |
3100 | 3101 | ||
3101 | temp_ff.full = dfixed_const(2); |
3102 | temp_ff.full = dfixed_const(2); |
3102 | mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); |
3103 | mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); |
3103 | temp_ff.full = dfixed_const(c); |
3104 | temp_ff.full = dfixed_const(c); |
3104 | mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); |
3105 | mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); |
3105 | temp_ff.full = dfixed_const(4); |
3106 | temp_ff.full = dfixed_const(4); |
3106 | mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); |
3107 | mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); |
3107 | mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); |
3108 | mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); |
3108 | mc_latency_mclk.full += k1.full; |
3109 | mc_latency_mclk.full += k1.full; |
3109 | 3110 | ||
3110 | mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); |
3111 | mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); |
3111 | mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); |
3112 | mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); |
3112 | 3113 | ||
3113 | /* |
3114 | /* |
3114 | HW cursor time assuming worst case of full size colour cursor. |
3115 | HW cursor time assuming worst case of full size colour cursor. |
3115 | */ |
3116 | */ |
3116 | temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); |
3117 | temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); |
3117 | temp_ff.full += trcd_ff.full; |
3118 | temp_ff.full += trcd_ff.full; |
3118 | if (temp_ff.full < tras_ff.full) |
3119 | if (temp_ff.full < tras_ff.full) |
3119 | temp_ff.full = tras_ff.full; |
3120 | temp_ff.full = tras_ff.full; |
3120 | cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); |
3121 | cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); |
3121 | 3122 | ||
3122 | temp_ff.full = dfixed_const(cur_size); |
3123 | temp_ff.full = dfixed_const(cur_size); |
3123 | cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); |
3124 | cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); |
3124 | /* |
3125 | /* |
3125 | Find the total latency for the display data. |
3126 | Find the total latency for the display data. |
3126 | */ |
3127 | */ |
3127 | disp_latency_overhead.full = dfixed_const(8); |
3128 | disp_latency_overhead.full = dfixed_const(8); |
3128 | disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); |
3129 | disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); |
3129 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; |
3130 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; |
3130 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; |
3131 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; |
3131 | 3132 | ||
3132 | if (mc_latency_mclk.full > mc_latency_sclk.full) |
3133 | if (mc_latency_mclk.full > mc_latency_sclk.full) |
3133 | disp_latency.full = mc_latency_mclk.full; |
3134 | disp_latency.full = mc_latency_mclk.full; |
3134 | else |
3135 | else |
3135 | disp_latency.full = mc_latency_sclk.full; |
3136 | disp_latency.full = mc_latency_sclk.full; |
3136 | 3137 | ||
3137 | /* setup Max GRPH_STOP_REQ default value */ |
3138 | /* setup Max GRPH_STOP_REQ default value */ |
3138 | if (ASIC_IS_RV100(rdev)) |
3139 | if (ASIC_IS_RV100(rdev)) |
3139 | max_stop_req = 0x5c; |
3140 | max_stop_req = 0x5c; |
3140 | else |
3141 | else |
3141 | max_stop_req = 0x7c; |
3142 | max_stop_req = 0x7c; |
3142 | 3143 | ||
3143 | if (mode1) { |
3144 | if (mode1) { |
3144 | /* CRTC1 |
3145 | /* CRTC1 |
3145 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. |
3146 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. |
3146 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] |
3147 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] |
3147 | */ |
3148 | */ |
3148 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; |
3149 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; |
3149 | 3150 | ||
3150 | if (stop_req > max_stop_req) |
3151 | if (stop_req > max_stop_req) |
3151 | stop_req = max_stop_req; |
3152 | stop_req = max_stop_req; |
3152 | 3153 | ||
3153 | /* |
3154 | /* |
3154 | Find the drain rate of the display buffer. |
3155 | Find the drain rate of the display buffer. |
3155 | */ |
3156 | */ |
3156 | temp_ff.full = dfixed_const((16/pixel_bytes1)); |
3157 | temp_ff.full = dfixed_const((16/pixel_bytes1)); |
3157 | disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); |
3158 | disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); |
3158 | 3159 | ||
3159 | /* |
3160 | /* |
3160 | Find the critical point of the display buffer. |
3161 | Find the critical point of the display buffer. |
3161 | */ |
3162 | */ |
3162 | crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); |
3163 | crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); |
3163 | crit_point_ff.full += dfixed_const_half(0); |
3164 | crit_point_ff.full += dfixed_const_half(0); |
3164 | 3165 | ||
3165 | critical_point = dfixed_trunc(crit_point_ff); |
3166 | critical_point = dfixed_trunc(crit_point_ff); |
3166 | 3167 | ||
3167 | if (rdev->disp_priority == 2) { |
3168 | if (rdev->disp_priority == 2) { |
3168 | critical_point = 0; |
3169 | critical_point = 0; |
3169 | } |
3170 | } |
3170 | 3171 | ||
3171 | /* |
3172 | /* |
3172 | The critical point should never be above max_stop_req-4. Setting |
3173 | The critical point should never be above max_stop_req-4. Setting |
3173 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. |
3174 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. |
3174 | */ |
3175 | */ |
3175 | if (max_stop_req - critical_point < 4) |
3176 | if (max_stop_req - critical_point < 4) |
3176 | critical_point = 0; |
3177 | critical_point = 0; |
3177 | 3178 | ||
3178 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { |
3179 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { |
3179 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ |
3180 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ |
3180 | critical_point = 0x10; |
3181 | critical_point = 0x10; |
3181 | } |
3182 | } |
3182 | 3183 | ||
3183 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); |
3184 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); |
3184 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); |
3185 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); |
3185 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
3186 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
3186 | temp &= ~(RADEON_GRPH_START_REQ_MASK); |
3187 | temp &= ~(RADEON_GRPH_START_REQ_MASK); |
3187 | if ((rdev->family == CHIP_R350) && |
3188 | if ((rdev->family == CHIP_R350) && |
3188 | (stop_req > 0x15)) { |
3189 | (stop_req > 0x15)) { |
3189 | stop_req -= 0x10; |
3190 | stop_req -= 0x10; |
3190 | } |
3191 | } |
3191 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
3192 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
3192 | temp |= RADEON_GRPH_BUFFER_SIZE; |
3193 | temp |= RADEON_GRPH_BUFFER_SIZE; |
3193 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | |
3194 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | |
3194 | RADEON_GRPH_CRITICAL_AT_SOF | |
3195 | RADEON_GRPH_CRITICAL_AT_SOF | |
3195 | RADEON_GRPH_STOP_CNTL); |
3196 | RADEON_GRPH_STOP_CNTL); |
3196 | /* |
3197 | /* |
3197 | Write the result into the register. |
3198 | Write the result into the register. |
3198 | */ |
3199 | */ |
3199 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
3200 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
3200 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
3201 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
3201 | 3202 | ||
3202 | #if 0 |
3203 | #if 0 |
3203 | if ((rdev->family == CHIP_RS400) || |
3204 | if ((rdev->family == CHIP_RS400) || |
3204 | (rdev->family == CHIP_RS480)) { |
3205 | (rdev->family == CHIP_RS480)) { |
3205 | /* attempt to program RS400 disp regs correctly ??? */ |
3206 | /* attempt to program RS400 disp regs correctly ??? */ |
3206 | temp = RREG32(RS400_DISP1_REG_CNTL); |
3207 | temp = RREG32(RS400_DISP1_REG_CNTL); |
3207 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | |
3208 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | |
3208 | RS400_DISP1_STOP_REQ_LEVEL_MASK); |
3209 | RS400_DISP1_STOP_REQ_LEVEL_MASK); |
3209 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | |
3210 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | |
3210 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
3211 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
3211 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
3212 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
3212 | temp = RREG32(RS400_DMIF_MEM_CNTL1); |
3213 | temp = RREG32(RS400_DMIF_MEM_CNTL1); |
3213 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | |
3214 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | |
3214 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); |
3215 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); |
3215 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | |
3216 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | |
3216 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | |
3217 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | |
3217 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); |
3218 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); |
3218 | } |
3219 | } |
3219 | #endif |
3220 | #endif |
3220 | 3221 | ||
3221 | DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", |
3222 | DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", |
3222 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ |
3223 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ |
3223 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); |
3224 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); |
3224 | } |
3225 | } |
3225 | 3226 | ||
3226 | if (mode2) { |
3227 | if (mode2) { |
3227 | u32 grph2_cntl; |
3228 | u32 grph2_cntl; |
3228 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; |
3229 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; |
3229 | 3230 | ||
3230 | if (stop_req > max_stop_req) |
3231 | if (stop_req > max_stop_req) |
3231 | stop_req = max_stop_req; |
3232 | stop_req = max_stop_req; |
3232 | 3233 | ||
3233 | /* |
3234 | /* |
3234 | Find the drain rate of the display buffer. |
3235 | Find the drain rate of the display buffer. |
3235 | */ |
3236 | */ |
3236 | temp_ff.full = dfixed_const((16/pixel_bytes2)); |
3237 | temp_ff.full = dfixed_const((16/pixel_bytes2)); |
3237 | disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); |
3238 | disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); |
3238 | 3239 | ||
3239 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); |
3240 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); |
3240 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); |
3241 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); |
3241 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
3242 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
3242 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); |
3243 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); |
3243 | if ((rdev->family == CHIP_R350) && |
3244 | if ((rdev->family == CHIP_R350) && |
3244 | (stop_req > 0x15)) { |
3245 | (stop_req > 0x15)) { |
3245 | stop_req -= 0x10; |
3246 | stop_req -= 0x10; |
3246 | } |
3247 | } |
3247 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
3248 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
3248 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; |
3249 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; |
3249 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | |
3250 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | |
3250 | RADEON_GRPH_CRITICAL_AT_SOF | |
3251 | RADEON_GRPH_CRITICAL_AT_SOF | |
3251 | RADEON_GRPH_STOP_CNTL); |
3252 | RADEON_GRPH_STOP_CNTL); |
3252 | 3253 | ||
3253 | if ((rdev->family == CHIP_RS100) || |
3254 | if ((rdev->family == CHIP_RS100) || |
3254 | (rdev->family == CHIP_RS200)) |
3255 | (rdev->family == CHIP_RS200)) |
3255 | critical_point2 = 0; |
3256 | critical_point2 = 0; |
3256 | else { |
3257 | else { |
3257 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; |
3258 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; |
3258 | temp_ff.full = dfixed_const(temp); |
3259 | temp_ff.full = dfixed_const(temp); |
3259 | temp_ff.full = dfixed_mul(mclk_ff, temp_ff); |
3260 | temp_ff.full = dfixed_mul(mclk_ff, temp_ff); |
3260 | if (sclk_ff.full < temp_ff.full) |
3261 | if (sclk_ff.full < temp_ff.full) |
3261 | temp_ff.full = sclk_ff.full; |
3262 | temp_ff.full = sclk_ff.full; |
3262 | 3263 | ||
3263 | read_return_rate.full = temp_ff.full; |
3264 | read_return_rate.full = temp_ff.full; |
3264 | 3265 | ||
3265 | if (mode1) { |
3266 | if (mode1) { |
3266 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; |
3267 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; |
3267 | time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); |
3268 | time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); |
3268 | } else { |
3269 | } else { |
3269 | time_disp1_drop_priority.full = 0; |
3270 | time_disp1_drop_priority.full = 0; |
3270 | } |
3271 | } |
3271 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
3272 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
3272 | crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); |
3273 | crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); |
3273 | crit_point_ff.full += dfixed_const_half(0); |
3274 | crit_point_ff.full += dfixed_const_half(0); |
3274 | 3275 | ||
3275 | critical_point2 = dfixed_trunc(crit_point_ff); |
3276 | critical_point2 = dfixed_trunc(crit_point_ff); |
3276 | 3277 | ||
3277 | if (rdev->disp_priority == 2) { |
3278 | if (rdev->disp_priority == 2) { |
3278 | critical_point2 = 0; |
3279 | critical_point2 = 0; |
3279 | } |
3280 | } |
3280 | 3281 | ||
3281 | if (max_stop_req - critical_point2 < 4) |
3282 | if (max_stop_req - critical_point2 < 4) |
3282 | critical_point2 = 0; |
3283 | critical_point2 = 0; |
3283 | 3284 | ||
3284 | } |
3285 | } |
3285 | 3286 | ||
3286 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { |
3287 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { |
3287 | /* some R300 cards have problem with this set to 0 */ |
3288 | /* some R300 cards have problem with this set to 0 */ |
3288 | critical_point2 = 0x10; |
3289 | critical_point2 = 0x10; |
3289 | } |
3290 | } |
3290 | 3291 | ||
3291 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
3292 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
3292 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
3293 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
3293 | 3294 | ||
3294 | if ((rdev->family == CHIP_RS400) || |
3295 | if ((rdev->family == CHIP_RS400) || |
3295 | (rdev->family == CHIP_RS480)) { |
3296 | (rdev->family == CHIP_RS480)) { |
3296 | #if 0 |
3297 | #if 0 |
3297 | /* attempt to program RS400 disp2 regs correctly ??? */ |
3298 | /* attempt to program RS400 disp2 regs correctly ??? */ |
3298 | temp = RREG32(RS400_DISP2_REQ_CNTL1); |
3299 | temp = RREG32(RS400_DISP2_REQ_CNTL1); |
3299 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | |
3300 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | |
3300 | RS400_DISP2_STOP_REQ_LEVEL_MASK); |
3301 | RS400_DISP2_STOP_REQ_LEVEL_MASK); |
3301 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | |
3302 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | |
3302 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
3303 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
3303 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
3304 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
3304 | temp = RREG32(RS400_DISP2_REQ_CNTL2); |
3305 | temp = RREG32(RS400_DISP2_REQ_CNTL2); |
3305 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | |
3306 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | |
3306 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); |
3307 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); |
3307 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | |
3308 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | |
3308 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | |
3309 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | |
3309 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); |
3310 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); |
3310 | #endif |
3311 | #endif |
3311 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); |
3312 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); |
3312 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); |
3313 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); |
3313 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); |
3314 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); |
3314 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); |
3315 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); |
3315 | } |
3316 | } |
3316 | 3317 | ||
3317 | DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", |
3318 | DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", |
3318 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); |
3319 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); |
3319 | } |
3320 | } |
3320 | } |
3321 | } |
3321 | 3322 | ||
3322 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3323 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3323 | { |
3324 | { |
3324 | uint32_t scratch; |
3325 | uint32_t scratch; |
3325 | uint32_t tmp = 0; |
3326 | uint32_t tmp = 0; |
3326 | unsigned i; |
3327 | unsigned i; |
3327 | int r; |
3328 | int r; |
3328 | 3329 | ||
3329 | r = radeon_scratch_get(rdev, &scratch); |
3330 | r = radeon_scratch_get(rdev, &scratch); |
3330 | if (r) { |
3331 | if (r) { |
3331 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
3332 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
3332 | return r; |
3333 | return r; |
3333 | } |
3334 | } |
3334 | WREG32(scratch, 0xCAFEDEAD); |
3335 | WREG32(scratch, 0xCAFEDEAD); |
3335 | r = radeon_ring_lock(rdev, ring, 2); |
3336 | r = radeon_ring_lock(rdev, ring, 2); |
3336 | if (r) { |
3337 | if (r) { |
3337 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
3338 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
3338 | radeon_scratch_free(rdev, scratch); |
3339 | radeon_scratch_free(rdev, scratch); |
3339 | return r; |
3340 | return r; |
3340 | } |
3341 | } |
3341 | radeon_ring_write(ring, PACKET0(scratch, 0)); |
3342 | radeon_ring_write(ring, PACKET0(scratch, 0)); |
3342 | radeon_ring_write(ring, 0xDEADBEEF); |
3343 | radeon_ring_write(ring, 0xDEADBEEF); |
3343 | radeon_ring_unlock_commit(rdev, ring); |
3344 | radeon_ring_unlock_commit(rdev, ring); |
3344 | for (i = 0; i < rdev->usec_timeout; i++) { |
3345 | for (i = 0; i < rdev->usec_timeout; i++) { |
3345 | tmp = RREG32(scratch); |
3346 | tmp = RREG32(scratch); |
3346 | if (tmp == 0xDEADBEEF) { |
3347 | if (tmp == 0xDEADBEEF) { |
3347 | break; |
3348 | break; |
3348 | } |
3349 | } |
3349 | DRM_UDELAY(1); |
3350 | DRM_UDELAY(1); |
3350 | } |
3351 | } |
3351 | if (i < rdev->usec_timeout) { |
3352 | if (i < rdev->usec_timeout) { |
3352 | DRM_INFO("ring test succeeded in %d usecs\n", i); |
3353 | DRM_INFO("ring test succeeded in %d usecs\n", i); |
3353 | } else { |
3354 | } else { |
3354 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", |
3355 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", |
3355 | scratch, tmp); |
3356 | scratch, tmp); |
3356 | r = -EINVAL; |
3357 | r = -EINVAL; |
3357 | } |
3358 | } |
3358 | radeon_scratch_free(rdev, scratch); |
3359 | radeon_scratch_free(rdev, scratch); |
3359 | return r; |
3360 | return r; |
3360 | } |
3361 | } |
3361 | 3362 | ||
3362 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
3363 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
3363 | { |
3364 | { |
3364 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3365 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3365 | 3366 | ||
3366 | if (ring->rptr_save_reg) { |
3367 | if (ring->rptr_save_reg) { |
3367 | u32 next_rptr = ring->wptr + 2 + 3; |
3368 | u32 next_rptr = ring->wptr + 2 + 3; |
3368 | radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); |
3369 | radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); |
3369 | radeon_ring_write(ring, next_rptr); |
3370 | radeon_ring_write(ring, next_rptr); |
3370 | } |
3371 | } |
3371 | 3372 | ||
3372 | radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); |
3373 | radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); |
3373 | radeon_ring_write(ring, ib->gpu_addr); |
3374 | radeon_ring_write(ring, ib->gpu_addr); |
3374 | radeon_ring_write(ring, ib->length_dw); |
3375 | radeon_ring_write(ring, ib->length_dw); |
3375 | } |
3376 | } |
3376 | 3377 | ||
3377 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3378 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3378 | { |
3379 | { |
3379 | struct radeon_ib ib; |
3380 | struct radeon_ib ib; |
3380 | uint32_t scratch; |
3381 | uint32_t scratch; |
3381 | uint32_t tmp = 0; |
3382 | uint32_t tmp = 0; |
3382 | unsigned i; |
3383 | unsigned i; |
3383 | int r; |
3384 | int r; |
3384 | 3385 | ||
3385 | r = radeon_scratch_get(rdev, &scratch); |
3386 | r = radeon_scratch_get(rdev, &scratch); |
3386 | if (r) { |
3387 | if (r) { |
3387 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); |
3388 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); |
3388 | return r; |
3389 | return r; |
3389 | } |
3390 | } |
3390 | WREG32(scratch, 0xCAFEDEAD); |
3391 | WREG32(scratch, 0xCAFEDEAD); |
3391 | r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); |
3392 | r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); |
3392 | if (r) { |
3393 | if (r) { |
3393 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
3394 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
3394 | goto free_scratch; |
3395 | goto free_scratch; |
3395 | } |
3396 | } |
3396 | ib.ptr[0] = PACKET0(scratch, 0); |
3397 | ib.ptr[0] = PACKET0(scratch, 0); |
3397 | ib.ptr[1] = 0xDEADBEEF; |
3398 | ib.ptr[1] = 0xDEADBEEF; |
3398 | ib.ptr[2] = PACKET2(0); |
3399 | ib.ptr[2] = PACKET2(0); |
3399 | ib.ptr[3] = PACKET2(0); |
3400 | ib.ptr[3] = PACKET2(0); |
3400 | ib.ptr[4] = PACKET2(0); |
3401 | ib.ptr[4] = PACKET2(0); |
3401 | ib.ptr[5] = PACKET2(0); |
3402 | ib.ptr[5] = PACKET2(0); |
3402 | ib.ptr[6] = PACKET2(0); |
3403 | ib.ptr[6] = PACKET2(0); |
3403 | ib.ptr[7] = PACKET2(0); |
3404 | ib.ptr[7] = PACKET2(0); |
3404 | ib.length_dw = 8; |
3405 | ib.length_dw = 8; |
3405 | r = radeon_ib_schedule(rdev, &ib, NULL); |
3406 | r = radeon_ib_schedule(rdev, &ib, NULL); |
3406 | if (r) { |
3407 | if (r) { |
3407 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
3408 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
3408 | goto free_ib; |
3409 | goto free_ib; |
3409 | } |
3410 | } |
3410 | r = radeon_fence_wait(ib.fence, false); |
3411 | r = radeon_fence_wait(ib.fence, false); |
3411 | if (r) { |
3412 | if (r) { |
3412 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
3413 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
3413 | goto free_ib; |
3414 | goto free_ib; |
3414 | } |
3415 | } |
3415 | for (i = 0; i < rdev->usec_timeout; i++) { |
3416 | for (i = 0; i < rdev->usec_timeout; i++) { |
3416 | tmp = RREG32(scratch); |
3417 | tmp = RREG32(scratch); |
3417 | if (tmp == 0xDEADBEEF) { |
3418 | if (tmp == 0xDEADBEEF) { |
3418 | break; |
3419 | break; |
3419 | } |
3420 | } |
3420 | DRM_UDELAY(1); |
3421 | DRM_UDELAY(1); |
3421 | } |
3422 | } |
3422 | if (i < rdev->usec_timeout) { |
3423 | if (i < rdev->usec_timeout) { |
3423 | DRM_INFO("ib test succeeded in %u usecs\n", i); |
3424 | DRM_INFO("ib test succeeded in %u usecs\n", i); |
3424 | } else { |
3425 | } else { |
3425 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
3426 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
3426 | scratch, tmp); |
3427 | scratch, tmp); |
3427 | r = -EINVAL; |
3428 | r = -EINVAL; |
3428 | } |
3429 | } |
3429 | free_ib: |
3430 | free_ib: |
3430 | radeon_ib_free(rdev, &ib); |
3431 | radeon_ib_free(rdev, &ib); |
3431 | free_scratch: |
3432 | free_scratch: |
3432 | radeon_scratch_free(rdev, scratch); |
3433 | radeon_scratch_free(rdev, scratch); |
3433 | return r; |
3434 | return r; |
3434 | } |
3435 | } |
3435 | 3436 | ||
3436 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
3437 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
3437 | { |
3438 | { |
3438 | /* Shutdown CP we shouldn't need to do that but better be safe than |
3439 | /* Shutdown CP we shouldn't need to do that but better be safe than |
3439 | * sorry |
3440 | * sorry |
3440 | */ |
3441 | */ |
3441 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
3442 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
3442 | WREG32(R_000740_CP_CSQ_CNTL, 0); |
3443 | WREG32(R_000740_CP_CSQ_CNTL, 0); |
3443 | 3444 | ||
3444 | /* Save few CRTC registers */ |
3445 | /* Save few CRTC registers */ |
3445 | save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
3446 | save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
3446 | save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
3447 | save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
3447 | save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); |
3448 | save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); |
3448 | save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); |
3449 | save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); |
3449 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
3450 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
3450 | save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); |
3451 | save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); |
3451 | save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); |
3452 | save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); |
3452 | } |
3453 | } |
3453 | 3454 | ||
3454 | /* Disable VGA aperture access */ |
3455 | /* Disable VGA aperture access */ |
3455 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
3456 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
3456 | /* Disable cursor, overlay, crtc */ |
3457 | /* Disable cursor, overlay, crtc */ |
3457 | WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); |
3458 | WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); |
3458 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | |
3459 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | |
3459 | S_000054_CRTC_DISPLAY_DIS(1)); |
3460 | S_000054_CRTC_DISPLAY_DIS(1)); |
3460 | WREG32(R_000050_CRTC_GEN_CNTL, |
3461 | WREG32(R_000050_CRTC_GEN_CNTL, |
3461 | (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | |
3462 | (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | |
3462 | S_000050_CRTC_DISP_REQ_EN_B(1)); |
3463 | S_000050_CRTC_DISP_REQ_EN_B(1)); |
3463 | WREG32(R_000420_OV0_SCALE_CNTL, |
3464 | WREG32(R_000420_OV0_SCALE_CNTL, |
3464 | C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); |
3465 | C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); |
3465 | WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); |
3466 | WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); |
3466 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
3467 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
3467 | WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | |
3468 | WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | |
3468 | S_000360_CUR2_LOCK(1)); |
3469 | S_000360_CUR2_LOCK(1)); |
3469 | WREG32(R_0003F8_CRTC2_GEN_CNTL, |
3470 | WREG32(R_0003F8_CRTC2_GEN_CNTL, |
3470 | (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | |
3471 | (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | |
3471 | S_0003F8_CRTC2_DISPLAY_DIS(1) | |
3472 | S_0003F8_CRTC2_DISPLAY_DIS(1) | |
3472 | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); |
3473 | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); |
3473 | WREG32(R_000360_CUR2_OFFSET, |
3474 | WREG32(R_000360_CUR2_OFFSET, |
3474 | C_000360_CUR2_LOCK & save->CUR2_OFFSET); |
3475 | C_000360_CUR2_LOCK & save->CUR2_OFFSET); |
3475 | } |
3476 | } |
3476 | } |
3477 | } |
3477 | 3478 | ||
3478 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) |
3479 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) |
3479 | { |
3480 | { |
3480 | /* Update base address for crtc */ |
3481 | /* Update base address for crtc */ |
3481 | WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
3482 | WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
3482 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
3483 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
3483 | WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
3484 | WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
3484 | } |
3485 | } |
3485 | /* Restore CRTC registers */ |
3486 | /* Restore CRTC registers */ |
3486 | WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
3487 | WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
3487 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
3488 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
3488 | WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); |
3489 | WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); |
3489 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
3490 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
3490 | WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); |
3491 | WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); |
3491 | } |
3492 | } |
3492 | } |
3493 | } |
3493 | 3494 | ||
3494 | void r100_vga_render_disable(struct radeon_device *rdev) |
3495 | void r100_vga_render_disable(struct radeon_device *rdev) |
3495 | { |
3496 | { |
3496 | u32 tmp; |
3497 | u32 tmp; |
3497 | 3498 | ||
3498 | tmp = RREG8(R_0003C2_GENMO_WT); |
3499 | tmp = RREG8(R_0003C2_GENMO_WT); |
3499 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
3500 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
3500 | } |
3501 | } |
3501 | 3502 | ||
3502 | static void r100_debugfs(struct radeon_device *rdev) |
3503 | static void r100_debugfs(struct radeon_device *rdev) |
3503 | { |
3504 | { |
3504 | int r; |
3505 | int r; |
3505 | 3506 | ||
3506 | r = r100_debugfs_mc_info_init(rdev); |
3507 | r = r100_debugfs_mc_info_init(rdev); |
3507 | if (r) |
3508 | if (r) |
3508 | dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
3509 | dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
3509 | } |
3510 | } |
3510 | 3511 | ||
3511 | static void r100_mc_program(struct radeon_device *rdev) |
3512 | static void r100_mc_program(struct radeon_device *rdev) |
3512 | { |
3513 | { |
3513 | struct r100_mc_save save; |
3514 | struct r100_mc_save save; |
3514 | 3515 | ||
3515 | /* Stops all mc clients */ |
3516 | /* Stops all mc clients */ |
3516 | r100_mc_stop(rdev, &save); |
3517 | r100_mc_stop(rdev, &save); |
3517 | if (rdev->flags & RADEON_IS_AGP) { |
3518 | if (rdev->flags & RADEON_IS_AGP) { |
3518 | WREG32(R_00014C_MC_AGP_LOCATION, |
3519 | WREG32(R_00014C_MC_AGP_LOCATION, |
3519 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
3520 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
3520 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
3521 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
3521 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
3522 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
3522 | if (rdev->family > CHIP_RV200) |
3523 | if (rdev->family > CHIP_RV200) |
3523 | WREG32(R_00015C_AGP_BASE_2, |
3524 | WREG32(R_00015C_AGP_BASE_2, |
3524 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
3525 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
3525 | } else { |
3526 | } else { |
3526 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
3527 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
3527 | WREG32(R_000170_AGP_BASE, 0); |
3528 | WREG32(R_000170_AGP_BASE, 0); |
3528 | if (rdev->family > CHIP_RV200) |
3529 | if (rdev->family > CHIP_RV200) |
3529 | WREG32(R_00015C_AGP_BASE_2, 0); |
3530 | WREG32(R_00015C_AGP_BASE_2, 0); |
3530 | } |
3531 | } |
3531 | /* Wait for mc idle */ |
3532 | /* Wait for mc idle */ |
3532 | if (r100_mc_wait_for_idle(rdev)) |
3533 | if (r100_mc_wait_for_idle(rdev)) |
3533 | dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); |
3534 | dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); |
3534 | /* Program MC, should be a 32bits limited address space */ |
3535 | /* Program MC, should be a 32bits limited address space */ |
3535 | WREG32(R_000148_MC_FB_LOCATION, |
3536 | WREG32(R_000148_MC_FB_LOCATION, |
3536 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
3537 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
3537 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
3538 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
3538 | r100_mc_resume(rdev, &save); |
3539 | r100_mc_resume(rdev, &save); |
3539 | } |
3540 | } |
3540 | 3541 | ||
3541 | static void r100_clock_startup(struct radeon_device *rdev) |
3542 | static void r100_clock_startup(struct radeon_device *rdev) |
3542 | { |
3543 | { |
3543 | u32 tmp; |
3544 | u32 tmp; |
3544 | 3545 | ||
3545 | if (radeon_dynclks != -1 && radeon_dynclks) |
3546 | if (radeon_dynclks != -1 && radeon_dynclks) |
3546 | radeon_legacy_set_clock_gating(rdev, 1); |
3547 | radeon_legacy_set_clock_gating(rdev, 1); |
3547 | /* We need to force on some of the block */ |
3548 | /* We need to force on some of the block */ |
3548 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
3549 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
3549 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
3550 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
3550 | if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) |
3551 | if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) |
3551 | tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); |
3552 | tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); |
3552 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
3553 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
3553 | } |
3554 | } |
3554 | 3555 | ||
3555 | static int r100_startup(struct radeon_device *rdev) |
3556 | static int r100_startup(struct radeon_device *rdev) |
3556 | { |
3557 | { |
3557 | int r; |
3558 | int r; |
3558 | 3559 | ||
3559 | /* set common regs */ |
3560 | /* set common regs */ |
3560 | r100_set_common_regs(rdev); |
3561 | r100_set_common_regs(rdev); |
3561 | /* program mc */ |
3562 | /* program mc */ |
3562 | r100_mc_program(rdev); |
3563 | r100_mc_program(rdev); |
3563 | /* Resume clock */ |
3564 | /* Resume clock */ |
3564 | r100_clock_startup(rdev); |
3565 | r100_clock_startup(rdev); |
3565 | /* Initialize GART (initialize after TTM so we can allocate |
3566 | /* Initialize GART (initialize after TTM so we can allocate |
3566 | * memory through TTM but finalize after TTM) */ |
3567 | * memory through TTM but finalize after TTM) */ |
3567 | r100_enable_bm(rdev); |
3568 | r100_enable_bm(rdev); |
3568 | if (rdev->flags & RADEON_IS_PCI) { |
3569 | if (rdev->flags & RADEON_IS_PCI) { |
3569 | r = r100_pci_gart_enable(rdev); |
3570 | r = r100_pci_gart_enable(rdev); |
3570 | if (r) |
3571 | if (r) |
3571 | return r; |
3572 | return r; |
3572 | } |
3573 | } |
3573 | 3574 | ||
3574 | /* allocate wb buffer */ |
3575 | /* allocate wb buffer */ |
3575 | r = radeon_wb_init(rdev); |
3576 | r = radeon_wb_init(rdev); |
3576 | if (r) |
3577 | if (r) |
3577 | return r; |
3578 | return r; |
- | 3579 | ||
- | 3580 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
|
- | 3581 | if (r) { |
|
- | 3582 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
|
- | 3583 | return r; |
|
- | 3584 | } |
|
3578 | 3585 | ||
3579 | /* Enable IRQ */ |
3586 | /* Enable IRQ */ |
3580 | r100_irq_set(rdev); |
3587 | r100_irq_set(rdev); |
3581 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
3588 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
3582 | /* 1M ring buffer */ |
3589 | /* 1M ring buffer */ |
3583 | r = r100_cp_init(rdev, 1024 * 1024); |
3590 | r = r100_cp_init(rdev, 1024 * 1024); |
3584 | if (r) { |
3591 | if (r) { |
3585 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
3592 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
3586 | return r; |
3593 | return r; |
3587 | } |
3594 | } |
3588 | 3595 | ||
3589 | r = radeon_ib_pool_init(rdev); |
3596 | r = radeon_ib_pool_init(rdev); |
3590 | if (r) { |
3597 | if (r) { |
3591 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
3598 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
3592 | return r; |
3599 | return r; |
3593 | } |
3600 | } |
- | 3601 | ||
3594 | return 0; |
3602 | return 0; |
3595 | } |
3603 | } |
3596 | 3604 | ||
3597 | /* |
3605 | /* |
3598 | * Due to how kexec works, it can leave the hw fully initialised when it |
3606 | * Due to how kexec works, it can leave the hw fully initialised when it |
3599 | * boots the new kernel. However doing our init sequence with the CP and |
3607 | * boots the new kernel. However doing our init sequence with the CP and |
3600 | * WB stuff setup causes GPU hangs on the RN50 at least. So at startup |
3608 | * WB stuff setup causes GPU hangs on the RN50 at least. So at startup |
3601 | * do some quick sanity checks and restore sane values to avoid this |
3609 | * do some quick sanity checks and restore sane values to avoid this |
3602 | * problem. |
3610 | * problem. |
3603 | */ |
3611 | */ |
3604 | void r100_restore_sanity(struct radeon_device *rdev) |
3612 | void r100_restore_sanity(struct radeon_device *rdev) |
3605 | { |
3613 | { |
3606 | u32 tmp; |
3614 | u32 tmp; |
3607 | 3615 | ||
3608 | tmp = RREG32(RADEON_CP_CSQ_CNTL); |
3616 | tmp = RREG32(RADEON_CP_CSQ_CNTL); |
3609 | if (tmp) { |
3617 | if (tmp) { |
3610 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
3618 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
3611 | } |
3619 | } |
3612 | tmp = RREG32(RADEON_CP_RB_CNTL); |
3620 | tmp = RREG32(RADEON_CP_RB_CNTL); |
3613 | if (tmp) { |
3621 | if (tmp) { |
3614 | WREG32(RADEON_CP_RB_CNTL, 0); |
3622 | WREG32(RADEON_CP_RB_CNTL, 0); |
3615 | } |
3623 | } |
3616 | tmp = RREG32(RADEON_SCRATCH_UMSK); |
3624 | tmp = RREG32(RADEON_SCRATCH_UMSK); |
3617 | if (tmp) { |
3625 | if (tmp) { |
3618 | WREG32(RADEON_SCRATCH_UMSK, 0); |
3626 | WREG32(RADEON_SCRATCH_UMSK, 0); |
3619 | } |
3627 | } |
3620 | } |
3628 | } |
3621 | 3629 | ||
3622 | int r100_init(struct radeon_device *rdev) |
3630 | int r100_init(struct radeon_device *rdev) |
3623 | { |
3631 | { |
3624 | int r; |
3632 | int r; |
3625 | 3633 | ||
3626 | /* Register debugfs file specific to this group of asics */ |
3634 | /* Register debugfs file specific to this group of asics */ |
3627 | r100_debugfs(rdev); |
3635 | r100_debugfs(rdev); |
3628 | /* Disable VGA */ |
3636 | /* Disable VGA */ |
3629 | r100_vga_render_disable(rdev); |
3637 | r100_vga_render_disable(rdev); |
3630 | /* Initialize scratch registers */ |
3638 | /* Initialize scratch registers */ |
3631 | radeon_scratch_init(rdev); |
3639 | radeon_scratch_init(rdev); |
3632 | /* Initialize surface registers */ |
3640 | /* Initialize surface registers */ |
3633 | radeon_surface_init(rdev); |
3641 | radeon_surface_init(rdev); |
3634 | /* sanity check some register to avoid hangs like after kexec */ |
3642 | /* sanity check some register to avoid hangs like after kexec */ |
3635 | r100_restore_sanity(rdev); |
3643 | r100_restore_sanity(rdev); |
3636 | /* TODO: disable VGA need to use VGA request */ |
3644 | /* TODO: disable VGA need to use VGA request */ |
3637 | /* BIOS*/ |
3645 | /* BIOS*/ |
3638 | if (!radeon_get_bios(rdev)) { |
3646 | if (!radeon_get_bios(rdev)) { |
3639 | if (ASIC_IS_AVIVO(rdev)) |
3647 | if (ASIC_IS_AVIVO(rdev)) |
3640 | return -EINVAL; |
3648 | return -EINVAL; |
3641 | } |
3649 | } |
3642 | if (rdev->is_atom_bios) { |
3650 | if (rdev->is_atom_bios) { |
3643 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
3651 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
3644 | return -EINVAL; |
3652 | return -EINVAL; |
3645 | } else { |
3653 | } else { |
3646 | r = radeon_combios_init(rdev); |
3654 | r = radeon_combios_init(rdev); |
3647 | if (r) |
3655 | if (r) |
3648 | return r; |
3656 | return r; |
3649 | } |
3657 | } |
3650 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
3658 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
3651 | if (radeon_asic_reset(rdev)) { |
3659 | if (radeon_asic_reset(rdev)) { |
3652 | dev_warn(rdev->dev, |
3660 | dev_warn(rdev->dev, |
3653 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
3661 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
3654 | RREG32(R_000E40_RBBM_STATUS), |
3662 | RREG32(R_000E40_RBBM_STATUS), |
3655 | RREG32(R_0007C0_CP_STAT)); |
3663 | RREG32(R_0007C0_CP_STAT)); |
3656 | } |
3664 | } |
3657 | /* check if cards are posted or not */ |
3665 | /* check if cards are posted or not */ |
3658 | if (radeon_boot_test_post_card(rdev) == false) |
3666 | if (radeon_boot_test_post_card(rdev) == false) |
3659 | return -EINVAL; |
3667 | return -EINVAL; |
3660 | /* Set asic errata */ |
3668 | /* Set asic errata */ |
3661 | r100_errata(rdev); |
3669 | r100_errata(rdev); |
3662 | /* Initialize clocks */ |
3670 | /* Initialize clocks */ |
3663 | radeon_get_clock_info(rdev->ddev); |
3671 | radeon_get_clock_info(rdev->ddev); |
3664 | /* initialize AGP */ |
3672 | /* initialize AGP */ |
3665 | if (rdev->flags & RADEON_IS_AGP) { |
3673 | if (rdev->flags & RADEON_IS_AGP) { |
3666 | r = radeon_agp_init(rdev); |
3674 | r = radeon_agp_init(rdev); |
3667 | if (r) { |
3675 | if (r) { |
3668 | radeon_agp_disable(rdev); |
3676 | radeon_agp_disable(rdev); |
3669 | } |
3677 | } |
3670 | } |
3678 | } |
3671 | /* initialize VRAM */ |
3679 | /* initialize VRAM */ |
3672 | r100_mc_init(rdev); |
3680 | r100_mc_init(rdev); |
3673 | /* Fence driver */ |
3681 | /* Fence driver */ |
3674 | r = radeon_fence_driver_init(rdev); |
3682 | r = radeon_fence_driver_init(rdev); |
3675 | if (r) |
3683 | if (r) |
3676 | return r; |
3684 | return r; |
3677 | r = radeon_irq_kms_init(rdev); |
3685 | r = radeon_irq_kms_init(rdev); |
3678 | if (r) |
3686 | if (r) |
3679 | return r; |
3687 | return r; |
3680 | /* Memory manager */ |
3688 | /* Memory manager */ |
3681 | r = radeon_bo_init(rdev); |
3689 | r = radeon_bo_init(rdev); |
3682 | if (r) |
3690 | if (r) |
3683 | return r; |
3691 | return r; |
3684 | if (rdev->flags & RADEON_IS_PCI) { |
3692 | if (rdev->flags & RADEON_IS_PCI) { |
3685 | r = r100_pci_gart_init(rdev); |
3693 | r = r100_pci_gart_init(rdev); |
3686 | if (r) |
3694 | if (r) |
3687 | return r; |
3695 | return r; |
3688 | } |
3696 | } |
3689 | r100_set_safe_registers(rdev); |
3697 | r100_set_safe_registers(rdev); |
3690 | 3698 | ||
3691 | rdev->accel_working = true; |
3699 | rdev->accel_working = true; |
3692 | r = r100_startup(rdev); |
3700 | r = r100_startup(rdev); |
3693 | if (r) { |
3701 | if (r) { |
3694 | /* Somethings want wront with the accel init stop accel */ |
3702 | /* Somethings want wront with the accel init stop accel */ |
3695 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
3703 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
3696 | if (rdev->flags & RADEON_IS_PCI) |
3704 | if (rdev->flags & RADEON_IS_PCI) |
3697 | r100_pci_gart_fini(rdev); |
3705 | r100_pci_gart_fini(rdev); |
3698 | rdev->accel_working = false; |
3706 | rdev->accel_working = false; |
3699 | } |
3707 | } |
3700 | return 0; |
3708 | return 0; |
3701 | } |
3709 | } |
3702 | 3710 | ||
3703 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
3711 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
3704 | { |
3712 | { |
3705 | if (reg < rdev->rmmio_size) |
3713 | if (reg < rdev->rmmio_size) |
3706 | return readl(((void __iomem *)rdev->rmmio) + reg); |
3714 | return readl(((void __iomem *)rdev->rmmio) + reg); |
3707 | else { |
3715 | else { |
3708 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
3716 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
3709 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
3717 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
3710 | } |
3718 | } |
3711 | } |
3719 | } |
3712 | 3720 | ||
3713 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
3721 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
3714 | { |
3722 | { |
3715 | if (reg < rdev->rmmio_size) |
3723 | if (reg < rdev->rmmio_size) |
3716 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
3724 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
3717 | else { |
3725 | else { |
3718 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
3726 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
3719 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
3727 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
3720 | } |
3728 | } |
3721 | } |
3729 | } |
3722 | 3730 | ||
3723 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) |
3731 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) |
3724 | { |
3732 | { |
3725 | if (reg < rdev->rio_mem_size) |
3733 | if (reg < rdev->rio_mem_size) |
3726 | return ioread32(rdev->rio_mem + reg); |
3734 | return ioread32(rdev->rio_mem + reg); |
3727 | else { |
3735 | else { |
3728 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
3736 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
3729 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); |
3737 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); |
3730 | } |
3738 | } |
3731 | } |
3739 | } |
3732 | 3740 | ||
3733 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
3741 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
3734 | { |
3742 | { |
3735 | if (reg < rdev->rio_mem_size) |
3743 | if (reg < rdev->rio_mem_size) |
3736 | iowrite32(v, rdev->rio_mem + reg); |
3744 | iowrite32(v, rdev->rio_mem + reg); |
3737 | else { |
3745 | else { |
3738 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
3746 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
3739 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); |
3747 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); |
3740 | } |
3748 | } |
3741 | }>>>>>>>>><>><>><>><>><>>>><>><>><>><>><>><>><>><>><>>=>>>><>=>><>><>><>><>>=>=>><>>><>=>><>>=>>>><>><>=>><>>>>>=>><>><>>>>=>>>>><>>><>><>><>><>><>><>>=>>>>>><>><>>><>><>><>><>><>>><>><>><>=>><>=>><>>><>><>>>><>><>><>><>><>><>>><>><>>>>>> |
3749 | }>>>>>>>>><>><>><>><>><>>>><>><>><>><>><>><>><>><>><>>=>>>><>=>><>><>><>><>>=>=>><>>><>=>><>>=>>>><>><>=>><>>>>>=>><>><>>>>=>>>>><>>><>><>><>><>><>><>>=>>>>>><>><>>><>><>><>><>><>>><>><>><>=>><>=>><>>><>><>>>><>><>><>><>><>><>>><>><>>>>>> |