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Rev 2997 | Rev 3120 | ||
---|---|---|---|
Line 389... | Line 389... | ||
389 | int r100_irq_process(struct radeon_device *rdev) |
389 | int r100_irq_process(struct radeon_device *rdev) |
390 | { |
390 | { |
391 | uint32_t status, msi_rearm; |
391 | uint32_t status, msi_rearm; |
392 | bool queue_hotplug = false; |
392 | bool queue_hotplug = false; |
Line -... | Line 393... | ||
- | 393 | ||
393 | 394 | ||
394 | status = r100_irq_ack(rdev); |
395 | status = r100_irq_ack(rdev); |
395 | if (!status) { |
396 | if (!status) { |
396 | return IRQ_NONE; |
397 | return IRQ_NONE; |
397 | } |
398 | } |
Line 3574... | Line 3575... | ||
3574 | /* allocate wb buffer */ |
3575 | /* allocate wb buffer */ |
3575 | r = radeon_wb_init(rdev); |
3576 | r = radeon_wb_init(rdev); |
3576 | if (r) |
3577 | if (r) |
3577 | return r; |
3578 | return r; |
Line -... | Line 3579... | ||
- | 3579 | ||
- | 3580 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
|
- | 3581 | if (r) { |
|
- | 3582 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
|
- | 3583 | return r; |
|
- | 3584 | } |
|
3578 | 3585 | ||
3579 | /* Enable IRQ */ |
3586 | /* Enable IRQ */ |
3580 | r100_irq_set(rdev); |
3587 | r100_irq_set(rdev); |
3581 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
3588 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
3582 | /* 1M ring buffer */ |
3589 | /* 1M ring buffer */ |
Line 3589... | Line 3596... | ||
3589 | r = radeon_ib_pool_init(rdev); |
3596 | r = radeon_ib_pool_init(rdev); |
3590 | if (r) { |
3597 | if (r) { |
3591 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
3598 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
3592 | return r; |
3599 | return r; |
3593 | } |
3600 | } |
- | 3601 | ||
3594 | return 0; |
3602 | return 0; |
3595 | } |
3603 | } |
Line 3596... | Line 3604... | ||
3596 | 3604 | ||
3597 | /* |
3605 | /* |