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Rev 2004 | Rev 2005 | ||
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Line 149... | Line 149... | ||
149 | 149 | ||
150 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
150 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
151 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
151 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
152 | switch (radeon_connector->hpd.hpd) { |
152 | switch (radeon_connector->hpd.hpd) { |
153 | case RADEON_HPD_1: |
153 | case RADEON_HPD_1: |
154 | // rdev->irq.hpd[0] = true; |
154 | rdev->irq.hpd[0] = true; |
155 | break; |
155 | break; |
156 | case RADEON_HPD_2: |
156 | case RADEON_HPD_2: |
157 | // rdev->irq.hpd[1] = true; |
157 | rdev->irq.hpd[1] = true; |
158 | break; |
158 | break; |
159 | default: |
159 | default: |
160 | break; |
160 | break; |
161 | } |
161 | } |
162 | } |
162 | } |
163 | // if (rdev->irq.installed) |
163 | if (rdev->irq.installed) |
164 | // r100_irq_set(rdev); |
164 | r100_irq_set(rdev); |
Line 165... | Line 165... | ||
165 | } |
165 | } |
166 | 166 | ||
167 | void r100_hpd_fini(struct radeon_device *rdev) |
167 | void r100_hpd_fini(struct radeon_device *rdev) |
Line 171... | Line 171... | ||
171 | 171 | ||
172 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
172 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
173 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
173 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
174 | switch (radeon_connector->hpd.hpd) { |
174 | switch (radeon_connector->hpd.hpd) { |
175 | case RADEON_HPD_1: |
175 | case RADEON_HPD_1: |
176 | // rdev->irq.hpd[0] = false; |
176 | rdev->irq.hpd[0] = false; |
177 | break; |
177 | break; |
178 | case RADEON_HPD_2: |
178 | case RADEON_HPD_2: |
179 | // rdev->irq.hpd[1] = false; |
179 | rdev->irq.hpd[1] = false; |
180 | break; |
180 | break; |
181 | default: |
181 | default: |
182 | break; |
182 | break; |
183 | } |
183 | } |
Line 267... | Line 267... | ||
267 | radeon_gart_fini(rdev); |
267 | radeon_gart_fini(rdev); |
268 | r100_pci_gart_disable(rdev); |
268 | r100_pci_gart_disable(rdev); |
269 | radeon_gart_table_ram_free(rdev); |
269 | radeon_gart_table_ram_free(rdev); |
270 | } |
270 | } |
Line -... | Line 271... | ||
- | 271 | ||
- | 272 | int r100_irq_set(struct radeon_device *rdev) |
|
- | 273 | { |
|
- | 274 | uint32_t tmp = 0; |
|
- | 275 | ||
- | 276 | if (!rdev->irq.installed) { |
|
- | 277 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
|
- | 278 | WREG32(R_000040_GEN_INT_CNTL, 0); |
|
- | 279 | return -EINVAL; |
|
- | 280 | } |
|
- | 281 | if (rdev->irq.sw_int) { |
|
- | 282 | tmp |= RADEON_SW_INT_ENABLE; |
|
- | 283 | } |
|
- | 284 | if (rdev->irq.gui_idle) { |
|
- | 285 | tmp |= RADEON_GUI_IDLE_MASK; |
|
- | 286 | } |
|
- | 287 | if (rdev->irq.crtc_vblank_int[0] || |
|
- | 288 | rdev->irq.pflip[0]) { |
|
- | 289 | tmp |= RADEON_CRTC_VBLANK_MASK; |
|
- | 290 | } |
|
- | 291 | if (rdev->irq.crtc_vblank_int[1] || |
|
- | 292 | rdev->irq.pflip[1]) { |
|
- | 293 | tmp |= RADEON_CRTC2_VBLANK_MASK; |
|
- | 294 | } |
|
- | 295 | if (rdev->irq.hpd[0]) { |
|
- | 296 | tmp |= RADEON_FP_DETECT_MASK; |
|
- | 297 | } |
|
- | 298 | if (rdev->irq.hpd[1]) { |
|
- | 299 | tmp |= RADEON_FP2_DETECT_MASK; |
|
- | 300 | } |
|
- | 301 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
|
- | 302 | return 0; |
|
Line 271... | Line 303... | ||
271 | 303 | } |
|
272 | 304 | ||
273 | void r100_irq_disable(struct radeon_device *rdev) |
305 | void r100_irq_disable(struct radeon_device *rdev) |
Line 279... | Line 311... | ||
279 | mdelay(1); |
311 | mdelay(1); |
280 | tmp = RREG32(R_000044_GEN_INT_STATUS); |
312 | tmp = RREG32(R_000044_GEN_INT_STATUS); |
281 | WREG32(R_000044_GEN_INT_STATUS, tmp); |
313 | WREG32(R_000044_GEN_INT_STATUS, tmp); |
282 | } |
314 | } |
Line 283... | Line -... | ||
283 | - | ||
284 | #if 0 |
315 | |
285 | static inline uint32_t r100_irq_ack(struct radeon_device *rdev) |
316 | static inline uint32_t r100_irq_ack(struct radeon_device *rdev) |
286 | { |
317 | { |
287 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
318 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
288 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
319 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
Line 299... | Line 330... | ||
299 | WREG32(RADEON_GEN_INT_STATUS, irqs); |
330 | WREG32(RADEON_GEN_INT_STATUS, irqs); |
300 | } |
331 | } |
301 | return irqs & irq_mask; |
332 | return irqs & irq_mask; |
302 | } |
333 | } |
Line -... | Line 334... | ||
- | 334 | ||
303 | 335 | int r100_irq_process(struct radeon_device *rdev) |
|
- | 336 | { |
|
- | 337 | uint32_t status, msi_rearm; |
|
- | 338 | bool queue_hotplug = false; |
|
- | 339 | ||
- | 340 | /* reset gui idle ack. the status bit is broken */ |
|
Line -... | Line 341... | ||
- | 341 | rdev->irq.gui_idle_acked = false; |
|
- | 342 | ||
- | 343 | status = r100_irq_ack(rdev); |
|
- | 344 | if (!status) { |
|
- | 345 | return IRQ_NONE; |
|
- | 346 | } |
|
- | 347 | if (rdev->shutdown) { |
|
- | 348 | return IRQ_NONE; |
|
- | 349 | } |
|
- | 350 | while (status) { |
|
- | 351 | /* SW interrupt */ |
|
- | 352 | if (status & RADEON_SW_INT_TEST) { |
|
- | 353 | radeon_fence_process(rdev); |
|
- | 354 | } |
|
- | 355 | /* gui idle interrupt */ |
|
- | 356 | if (status & RADEON_GUI_IDLE_STAT) { |
|
- | 357 | rdev->irq.gui_idle_acked = true; |
|
- | 358 | rdev->pm.gui_idle = true; |
|
- | 359 | // wake_up(&rdev->irq.idle_queue); |
|
- | 360 | } |
|
- | 361 | /* Vertical blank interrupts */ |
|
- | 362 | if (status & RADEON_CRTC_VBLANK_STAT) { |
|
- | 363 | if (rdev->irq.crtc_vblank_int[0]) { |
|
- | 364 | // drm_handle_vblank(rdev->ddev, 0); |
|
- | 365 | rdev->pm.vblank_sync = true; |
|
- | 366 | // wake_up(&rdev->irq.vblank_queue); |
|
- | 367 | } |
|
- | 368 | // if (rdev->irq.pflip[0]) |
|
- | 369 | // radeon_crtc_handle_flip(rdev, 0); |
|
- | 370 | } |
|
- | 371 | if (status & RADEON_CRTC2_VBLANK_STAT) { |
|
- | 372 | if (rdev->irq.crtc_vblank_int[1]) { |
|
- | 373 | // drm_handle_vblank(rdev->ddev, 1); |
|
- | 374 | rdev->pm.vblank_sync = true; |
|
- | 375 | // wake_up(&rdev->irq.vblank_queue); |
|
- | 376 | } |
|
- | 377 | // if (rdev->irq.pflip[1]) |
|
- | 378 | // radeon_crtc_handle_flip(rdev, 1); |
|
- | 379 | } |
|
- | 380 | if (status & RADEON_FP_DETECT_STAT) { |
|
- | 381 | queue_hotplug = true; |
|
- | 382 | DRM_DEBUG("HPD1\n"); |
|
- | 383 | } |
|
- | 384 | if (status & RADEON_FP2_DETECT_STAT) { |
|
- | 385 | queue_hotplug = true; |
|
- | 386 | DRM_DEBUG("HPD2\n"); |
|
- | 387 | } |
|
- | 388 | status = r100_irq_ack(rdev); |
|
- | 389 | } |
|
- | 390 | /* reset gui idle ack. the status bit is broken */ |
|
- | 391 | rdev->irq.gui_idle_acked = false; |
|
- | 392 | // if (queue_hotplug) |
|
- | 393 | // schedule_work(&rdev->hotplug_work); |
|
- | 394 | if (rdev->msi_enabled) { |
|
- | 395 | switch (rdev->family) { |
|
- | 396 | case CHIP_RS400: |
|
- | 397 | case CHIP_RS480: |
|
- | 398 | msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; |
|
- | 399 | WREG32(RADEON_AIC_CNTL, msi_rearm); |
|
- | 400 | WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); |
|
- | 401 | break; |
|
- | 402 | default: |
|
- | 403 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; |
|
- | 404 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); |
|
- | 405 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); |
|
- | 406 | break; |
|
- | 407 | } |
|
- | 408 | } |
|
Line 304... | Line 409... | ||
304 | #endif |
409 | return IRQ_HANDLED; |
305 | 410 | } |
|
306 | 411 | ||
307 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) |
412 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) |
Line 336... | Line 441... | ||
336 | radeon_ring_write(rdev, fence->seq); |
441 | radeon_ring_write(rdev, fence->seq); |
337 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
442 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
338 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
443 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
339 | } |
444 | } |
Line 340... | Line -... | ||
340 | - | ||
341 | #if 0 |
- | |
342 | 445 | ||
343 | int r100_copy_blit(struct radeon_device *rdev, |
446 | int r100_copy_blit(struct radeon_device *rdev, |
344 | uint64_t src_offset, |
447 | uint64_t src_offset, |
345 | uint64_t dst_offset, |
448 | uint64_t dst_offset, |
346 | unsigned num_pages, |
449 | unsigned num_pages, |
Line 411... | Line 514... | ||
411 | } |
514 | } |
412 | radeon_ring_unlock_commit(rdev); |
515 | radeon_ring_unlock_commit(rdev); |
413 | return r; |
516 | return r; |
414 | } |
517 | } |
Line 415... | Line -... | ||
415 | - | ||
416 | #endif |
- | |
417 | - | ||
418 | 518 | ||
419 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
519 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
420 | { |
520 | { |
421 | unsigned i; |
521 | unsigned i; |
Line 1615... | Line 1715... | ||
1615 | } |
1715 | } |
Line 1616... | Line 1716... | ||
1616 | 1716 | ||
1617 | void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp) |
1717 | void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp) |
1618 | { |
1718 | { |
1619 | lockup->last_cp_rptr = cp->rptr; |
1719 | lockup->last_cp_rptr = cp->rptr; |
1620 | lockup->last_jiffies = 0; //jiffies; |
1720 | lockup->last_jiffies = GetTimerTicks(); |
Line 1621... | Line 1721... | ||
1621 | } |
1721 | } |
1622 | 1722 | ||
1623 | /** |
1723 | /** |
Line 1643... | Line 1743... | ||
1643 | **/ |
1743 | **/ |
1644 | bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp) |
1744 | bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp) |
1645 | { |
1745 | { |
1646 | unsigned long cjiffies, elapsed; |
1746 | unsigned long cjiffies, elapsed; |
Line 1647... | Line -... | ||
1647 | - | ||
1648 | #if 0 |
1747 | |
1649 | cjiffies = jiffies; |
1748 | cjiffies = GetTimerTicks(); |
1650 | if (!time_after(cjiffies, lockup->last_jiffies)) { |
1749 | if (!time_after(cjiffies, lockup->last_jiffies)) { |
1651 | /* likely a wrap around */ |
1750 | /* likely a wrap around */ |
1652 | lockup->last_cp_rptr = cp->rptr; |
1751 | lockup->last_cp_rptr = cp->rptr; |
1653 | lockup->last_jiffies = jiffies; |
1752 | lockup->last_jiffies = GetTimerTicks(); |
1654 | return false; |
1753 | return false; |
1655 | } |
1754 | } |
1656 | if (cp->rptr != lockup->last_cp_rptr) { |
1755 | if (cp->rptr != lockup->last_cp_rptr) { |
1657 | /* CP is still working no lockup */ |
1756 | /* CP is still working no lockup */ |
1658 | lockup->last_cp_rptr = cp->rptr; |
1757 | lockup->last_cp_rptr = cp->rptr; |
1659 | lockup->last_jiffies = jiffies; |
1758 | lockup->last_jiffies = GetTimerTicks(); |
1660 | return false; |
1759 | return false; |
1661 | } |
1760 | } |
1662 | elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); |
1761 | elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); |
1663 | if (elapsed >= 10000) { |
1762 | if (elapsed >= 10000) { |
1664 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
1763 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
1665 | return true; |
1764 | return true; |
1666 | } |
- | |
1667 | #endif |
- | |
1668 | 1765 | } |
|
1669 | /* give a chance to the GPU ... */ |
1766 | /* give a chance to the GPU ... */ |
1670 | return false; |
1767 | return false; |
Line 1671... | Line 1768... | ||
1671 | } |
1768 | } |
Line 3193... | Line 3290... | ||
3193 | } |
3290 | } |
3194 | radeon_scratch_free(rdev, scratch); |
3291 | radeon_scratch_free(rdev, scratch); |
3195 | return r; |
3292 | return r; |
3196 | } |
3293 | } |
Line 3197... | Line -... | ||
3197 | - | ||
3198 | #if 0 |
- | |
3199 | 3294 | ||
3200 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
3295 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
3201 | { |
3296 | { |
3202 | radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); |
3297 | radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); |
3203 | radeon_ring_write(rdev, ib->gpu_addr); |
3298 | radeon_ring_write(rdev, ib->gpu_addr); |
Line 3281... | Line 3376... | ||
3281 | r100_ib_fini(rdev); |
3376 | r100_ib_fini(rdev); |
3282 | return r; |
3377 | return r; |
3283 | } |
3378 | } |
3284 | return 0; |
3379 | return 0; |
3285 | } |
3380 | } |
3286 | #endif |
- | |
Line 3287... | Line 3381... | ||
3287 | 3381 | ||
3288 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
3382 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
3289 | { |
3383 | { |
3290 | /* Shutdown CP we shouldn't need to do that but better be safe than |
3384 | /* Shutdown CP we shouldn't need to do that but better be safe than |
Line 3434... | Line 3528... | ||
3434 | if (rdev->flags & RADEON_IS_PCI) { |
3528 | if (rdev->flags & RADEON_IS_PCI) { |
3435 | r = r100_pci_gart_enable(rdev); |
3529 | r = r100_pci_gart_enable(rdev); |
3436 | if (r) |
3530 | if (r) |
3437 | return r; |
3531 | return r; |
3438 | } |
3532 | } |
- | 3533 | ||
- | 3534 | /* allocate wb buffer */ |
|
- | 3535 | r = radeon_wb_init(rdev); |
|
- | 3536 | if (r) |
|
- | 3537 | return r; |
|
- | 3538 | ||
3439 | /* Enable IRQ */ |
3539 | /* Enable IRQ */ |
3440 | // r100_irq_set(rdev); |
3540 | r100_irq_set(rdev); |
3441 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
3541 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
3442 | /* 1M ring buffer */ |
3542 | /* 1M ring buffer */ |
3443 | r = r100_cp_init(rdev, 1024 * 1024); |
3543 | r = r100_cp_init(rdev, 1024 * 1024); |
3444 | if (r) { |
3544 | if (r) { |
3445 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
3545 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
3446 | return r; |
3546 | return r; |
3447 | } |
3547 | } |
3448 | // r = r100_ib_init(rdev); |
3548 | r = r100_ib_init(rdev); |
3449 | // if (r) { |
3549 | if (r) { |
3450 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
3550 | dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
3451 | // return r; |
3551 | return r; |
3452 | // } |
3552 | } |
3453 | return 0; |
3553 | return 0; |
3454 | } |
3554 | } |
Line 3455... | Line 3555... | ||
3455 | 3555 | ||
3456 | /* |
3556 | /* |
Line 3528... | Line 3628... | ||
3528 | } |
3628 | } |
3529 | } |
3629 | } |
3530 | /* initialize VRAM */ |
3630 | /* initialize VRAM */ |
3531 | r100_mc_init(rdev); |
3631 | r100_mc_init(rdev); |
3532 | /* Fence driver */ |
3632 | /* Fence driver */ |
3533 | // r = radeon_fence_driver_init(rdev); |
3633 | r = radeon_fence_driver_init(rdev); |
3534 | // if (r) |
3634 | if (r) |
3535 | // return r; |
3635 | return r; |
3536 | // r = radeon_irq_kms_init(rdev); |
3636 | r = radeon_irq_kms_init(rdev); |
3537 | // if (r) |
3637 | if (r) |
3538 | // return r; |
3638 | return r; |
3539 | /* Memory manager */ |
3639 | /* Memory manager */ |
3540 | r = radeon_bo_init(rdev); |
3640 | r = radeon_bo_init(rdev); |
3541 | if (r) |
3641 | if (r) |
3542 | return r; |
3642 | return r; |
3543 | if (rdev->flags & RADEON_IS_PCI) { |
3643 | if (rdev->flags & RADEON_IS_PCI) { |