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Rev 1246 Rev 1268
Line 190... Line 190...
190 
int r100_wb_init(struct radeon_device *rdev)
 190 
int r100_wb_init(struct radeon_device *rdev)
191 
{
 191 
{
192 
	int r;
 192 
	int r;
Line 193... Line 193...
193 
 
 193 
 
194 
	if (rdev->wb.wb_obj == NULL) {
 194 
	if (rdev->wb.wb_obj == NULL) {
195 
		r = radeon_object_create(rdev, NULL, 4096,
 195 
		r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
196 
					 true,
 196 
					 true,
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					 RADEON_GEM_DOMAIN_GTT,
 197 
					 RADEON_GEM_DOMAIN_GTT,
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					 false, &rdev->wb.wb_obj);
 198 
					 false, &rdev->wb.wb_obj);
199 
		if (r) {
 199 
		if (r) {
Line 530... Line 530...
530 
	 */
 530 
	 */
531 
	indirect2_start = 80;
 531 
	indirect2_start = 80;
532 
	indirect1_start = 16;
 532 
	indirect1_start = 16;
533 
	/* cp setup */
 533 
	/* cp setup */
534 
	WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 534 
	WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
535 
	WREG32(RADEON_CP_RB_CNTL,
 - 
 
536 
#ifdef __BIG_ENDIAN
 - 
 
537 
	       RADEON_BUF_SWAP_32BIT |
 - 
 
538 
#endif
 - 
 
539 
	       REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 535 
	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
540 
	       REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 536 
	       REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
541 
	       REG_SET(RADEON_MAX_FETCH, max_fetch) |
 537 
	       REG_SET(RADEON_MAX_FETCH, max_fetch) |
542 
	       RADEON_RB_NO_UPDATE);
 538 
	       RADEON_RB_NO_UPDATE);
- 
 
 539 
#ifdef __BIG_ENDIAN
- 
 
 540 
	tmp |= RADEON_BUF_SWAP_32BIT;
- 
 
 541 
#endif
- 
 
 542 
	WREG32(RADEON_CP_RB_CNTL, tmp);
- 
 
 543 
 
543 
	/* Set ring address */
 544 
	/* Set ring address */
544 
	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 545 
	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
545 
	WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 546 
	WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
546 
	/* Force read & write ptr to 0 */
 547 
	/* Force read & write ptr to 0 */
547 
	tmp = RREG32(RADEON_CP_RB_CNTL);
 - 
 
548 
	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 548 
	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
549 
	WREG32(RADEON_CP_RB_RPTR_WR, 0);
 549 
	WREG32(RADEON_CP_RB_RPTR_WR, 0);
550 
	WREG32(RADEON_CP_RB_WPTR, 0);
 550 
	WREG32(RADEON_CP_RB_WPTR, 0);
551 
	WREG32(RADEON_CP_RB_CNTL, tmp);
 551 
	WREG32(RADEON_CP_RB_CNTL, tmp);
552 
	udelay(10);
 552 
	udelay(10);
Line 2339... Line 2339...
2339 
	temp_ff.full = rfixed_const(cur_size);
 2339 
	temp_ff.full = rfixed_const(cur_size);
2340 
	cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
 2340 
	cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2341 
	/*
 2341 
	/*
2342 
	  Find the total latency for the display data.
 2342 
	  Find the total latency for the display data.
2343 
	*/
 2343 
	*/
2344 
	disp_latency_overhead.full = rfixed_const(80);
 2344 
	disp_latency_overhead.full = rfixed_const(8);
2345 
	disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
 2345 
	disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2346 
	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
 2346 
	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2347 
	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
 2347 
	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
Line 2348... Line 2348...
2348 
 
 2348