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Rev 1128 Rev 1129
Line 166... Line 166...
166 
void r100_mc_setup(struct radeon_device *rdev)
 166 
void r100_mc_setup(struct radeon_device *rdev)
167 
{
 167 
{
168 
	uint32_t tmp;
 168 
	uint32_t tmp;
169 
	int r;
 169 
	int r;
Line 170... Line 170...
170 
 
 170 
 
171 
//   r = r100_debugfs_mc_info_init(rdev);
 171 
	r = r100_debugfs_mc_info_init(rdev);
172 
//   if (r) {
 172 
	if (r) {
173 
//       DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
 173 
		DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
174 
//   }
 174 
	}
175 
	/* Write VRAM size in case we are limiting it */
 175 
	/* Write VRAM size in case we are limiting it */
176 
	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
 176 
	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
177 
	tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
 177 
	tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
178 
	tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
 178 
	tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
Line 204... Line 204...
204 
 
 204 
 
205 
int r100_mc_init(struct radeon_device *rdev)
 205 
int r100_mc_init(struct radeon_device *rdev)
206 
{
 206 
{
Line 207... Line 207...
207 
	int r;
 207 
	int r;
208 
 
 208 
 
209 
//   if (r100_debugfs_rbbm_init(rdev)) {
 209 
	if (r100_debugfs_rbbm_init(rdev)) {
Line 210... Line 210...
210 
//       DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 210 
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
211 
//   }
 211 
	}
212 
 
 212 
 
Line 493... Line 493...
493 
	unsigned indirect2_start;
 493 
	unsigned indirect2_start;
494 
	unsigned indirect1_start;
 494 
	unsigned indirect1_start;
495 
	uint32_t tmp;
 495 
	uint32_t tmp;
496 
	int r;
 496 
	int r;
Line 497... Line -...
497 
 
 - 
 
498 
    dbgprintf("%s\n",__FUNCTION__);
 - 
 
499 
 
 497 
 
500 
//   if (r100_debugfs_cp_init(rdev)) {
 498 
	if (r100_debugfs_cp_init(rdev)) {
501 
//       DRM_ERROR("Failed to register debugfs file for CP !\n");
 499 
		DRM_ERROR("Failed to register debugfs file for CP !\n");
502 
//   }
 500 
	}
503 
	/* Reset CP */
 501 
	/* Reset CP */
504 
	tmp = RREG32(RADEON_CP_CSQ_STAT);
 502 
	tmp = RREG32(RADEON_CP_CSQ_STAT);
505 
	if ((tmp & (1 << 31))) {
 503 
	if ((tmp & (1 << 31))) {
506 
		DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
 504 
		DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
Line 1375... Line 1373...
1375 
int r100_init(struct radeon_device *rdev)
 1373 
int r100_init(struct radeon_device *rdev)
1376 
{
 1374 
{
1377 
	return 0;
 1375 
	return 0;
1378 
}
 1376 
}
Line -... Line 1377...
- 
 
 1377 
 
- 
 
 1378 
/*
- 
 
 1379 
 * Debugfs info
- 
 
 1380 
 */
- 
 
 1381 
#if defined(CONFIG_DEBUG_FS)
- 
 
 1382 
static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
- 
 
 1383 
{
- 
 
 1384 
	struct drm_info_node *node = (struct drm_info_node *) m->private;
- 
 
 1385 
	struct drm_device *dev = node->minor->dev;
- 
 
 1386 
	struct radeon_device *rdev = dev->dev_private;
- 
 
 1387 
	uint32_t reg, value;
- 
 
 1388 
	unsigned i;
- 
 
 1389 
 
- 
 
 1390 
	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
- 
 
 1391 
	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
- 
 
 1392 
	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
- 
 
 1393 
	for (i = 0; i < 64; i++) {
- 
 
 1394 
		WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
- 
 
 1395 
		reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
- 
 
 1396 
		WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
- 
 
 1397 
		value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
- 
 
 1398 
		seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
- 
 
 1399 
	}
- 
 
 1400 
	return 0;
- 
 
 1401 
}
- 
 
 1402 
 
- 
 
 1403 
static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
- 
 
 1404 
{
- 
 
 1405 
	struct drm_info_node *node = (struct drm_info_node *) m->private;
- 
 
 1406 
	struct drm_device *dev = node->minor->dev;
- 
 
 1407 
	struct radeon_device *rdev = dev->dev_private;
- 
 
 1408 
	uint32_t rdp, wdp;
- 
 
 1409 
	unsigned count, i, j;
- 
 
 1410 
 
- 
 
 1411 
	radeon_ring_free_size(rdev);
- 
 
 1412 
	rdp = RREG32(RADEON_CP_RB_RPTR);
- 
 
 1413 
	wdp = RREG32(RADEON_CP_RB_WPTR);
- 
 
 1414 
	count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
- 
 
 1415 
	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
- 
 
 1416 
	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
- 
 
 1417 
	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
- 
 
 1418 
	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
- 
 
 1419 
	seq_printf(m, "%u dwords in ring\n", count);
- 
 
 1420 
	for (j = 0; j <= count; j++) {
- 
 
 1421 
		i = (rdp + j) & rdev->cp.ptr_mask;
- 
 
 1422 
		seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
- 
 
 1423 
	}
- 
 
 1424 
	return 0;
- 
 
 1425 
}
- 
 
 1426 
 
- 
 
 1427 
 
- 
 
 1428 
static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
- 
 
 1429 
{
- 
 
 1430 
	struct drm_info_node *node = (struct drm_info_node *) m->private;
- 
 
 1431 
	struct drm_device *dev = node->minor->dev;
- 
 
 1432 
	struct radeon_device *rdev = dev->dev_private;
- 
 
 1433 
	uint32_t csq_stat, csq2_stat, tmp;
- 
 
 1434 
	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
- 
 
 1435 
	unsigned i;
- 
 
 1436 
 
- 
 
 1437 
	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
- 
 
 1438 
	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
- 
 
 1439 
	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
- 
 
 1440 
	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
- 
 
 1441 
	r_rptr = (csq_stat >> 0) & 0x3ff;
- 
 
 1442 
	r_wptr = (csq_stat >> 10) & 0x3ff;
- 
 
 1443 
	ib1_rptr = (csq_stat >> 20) & 0x3ff;
- 
 
 1444 
	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
- 
 
 1445 
	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
- 
 
 1446 
	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
- 
 
 1447 
	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
- 
 
 1448 
	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
- 
 
 1449 
	seq_printf(m, "Ring rptr %u\n", r_rptr);
- 
 
 1450 
	seq_printf(m, "Ring wptr %u\n", r_wptr);
- 
 
 1451 
	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
- 
 
 1452 
	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
- 
 
 1453 
	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
- 
 
 1454 
	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
- 
 
 1455 
	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
- 
 
 1456 
	 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
- 
 
 1457 
	seq_printf(m, "Ring fifo:\n");
- 
 
 1458 
	for (i = 0; i < 256; i++) {
- 
 
 1459 
		WREG32(RADEON_CP_CSQ_ADDR, i << 2);
- 
 
 1460 
		tmp = RREG32(RADEON_CP_CSQ_DATA);
- 
 
 1461 
		seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
- 
 
 1462 
	}
- 
 
 1463 
	seq_printf(m, "Indirect1 fifo:\n");
- 
 
 1464 
	for (i = 256; i <= 512; i++) {
- 
 
 1465 
		WREG32(RADEON_CP_CSQ_ADDR, i << 2);
- 
 
 1466 
		tmp = RREG32(RADEON_CP_CSQ_DATA);
- 
 
 1467 
		seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
- 
 
 1468 
	}
- 
 
 1469 
	seq_printf(m, "Indirect2 fifo:\n");
- 
 
 1470 
	for (i = 640; i < ib1_wptr; i++) {
- 
 
 1471 
		WREG32(RADEON_CP_CSQ_ADDR, i << 2);
- 
 
 1472 
		tmp = RREG32(RADEON_CP_CSQ_DATA);
- 
 
 1473 
		seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
- 
 
 1474 
	}
- 
 
 1475 
	return 0;
- 
 
 1476 
}
- 
 
 1477 
 
- 
 
 1478 
static int r100_debugfs_mc_info(struct seq_file *m, void *data)
- 
 
 1479 
{
- 
 
 1480 
	struct drm_info_node *node = (struct drm_info_node *) m->private;
- 
 
 1481 
	struct drm_device *dev = node->minor->dev;
- 
 
 1482 
	struct radeon_device *rdev = dev->dev_private;
- 
 
 1483 
	uint32_t tmp;
- 
 
 1484 
 
- 
 
 1485 
	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
- 
 
 1486 
	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
- 
 
 1487 
	tmp = RREG32(RADEON_MC_FB_LOCATION);
- 
 
 1488 
	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
- 
 
 1489 
	tmp = RREG32(RADEON_BUS_CNTL);
- 
 
 1490 
	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
- 
 
 1491 
	tmp = RREG32(RADEON_MC_AGP_LOCATION);
- 
 
 1492 
	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
- 
 
 1493 
	tmp = RREG32(RADEON_AGP_BASE);
- 
 
 1494 
	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
- 
 
 1495 
	tmp = RREG32(RADEON_HOST_PATH_CNTL);
- 
 
 1496 
	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
- 
 
 1497 
	tmp = RREG32(0x01D0);
- 
 
 1498 
	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
- 
 
 1499 
	tmp = RREG32(RADEON_AIC_LO_ADDR);
- 
 
 1500 
	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
- 
 
 1501 
	tmp = RREG32(RADEON_AIC_HI_ADDR);
- 
 
 1502 
	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
- 
 
 1503 
	tmp = RREG32(0x01E4);
- 
 
 1504 
	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
- 
 
 1505 
	return 0;
- 
 
 1506 
}
- 
 
 1507 
 
- 
 
 1508 
static struct drm_info_list r100_debugfs_rbbm_list[] = {
- 
 
 1509 
	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
- 
 
 1510 
};
- 
 
 1511 
 
- 
 
 1512 
static struct drm_info_list r100_debugfs_cp_list[] = {
- 
 
 1513 
	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
- 
 
 1514 
	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
- 
 
 1515 
};
- 
 
 1516 
 
- 
 
 1517 
static struct drm_info_list r100_debugfs_mc_info_list[] = {
- 
 
 1518 
	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
- 
 
 1519 
};
- 
 
 1520 
#endif
- 
 
 1521 
 
- 
 
 1522 
int r100_debugfs_rbbm_init(struct radeon_device *rdev)
- 
 
 1523 
{
- 
 
 1524 
#if defined(CONFIG_DEBUG_FS)
- 
 
 1525 
	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
- 
 
 1526 
#else
- 
 
 1527 
	return 0;
- 
 
 1528 
#endif
- 
 
 1529 
}
- 
 
 1530 
 
- 
 
 1531 
int r100_debugfs_cp_init(struct radeon_device *rdev)
- 
 
 1532 
{
- 
 
 1533 
#if defined(CONFIG_DEBUG_FS)
- 
 
 1534 
	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
- 
 
 1535 
#else
- 
 
 1536 
	return 0;
- 
 
 1537 
#endif
- 
 
 1538 
}
- 
 
 1539 
 
- 
 
 1540 
int r100_debugfs_mc_info_init(struct radeon_device *rdev)
- 
 
 1541 
{
- 
 
 1542 
#if defined(CONFIG_DEBUG_FS)
- 
 
 1543 
	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
- 
 
 1544 
#else
- 
 
 1545 
	return 0;
- 
 
 1546 
#endif