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Line 28... Line 28...
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//#include 
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//#include 
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//#include "drmP.h"
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//#include "drmP.h"
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//#include "drm.h"
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//#include "drm.h"
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#include "radeon_drm.h"
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#include "radeon_drm.h"
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#include "radeon_microcode.h"
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#include "radeon_microcode.h"
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-
 
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#include "radeon_reg.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "radeon.h"
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/* This files gather functions specifics to:
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/* This files gather functions specifics to:
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			WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
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			WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
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		}
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		}
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	}
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	}
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}
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}
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-
 
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int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
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int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
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{
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{
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	unsigned rb_bufsz;
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	unsigned rb_bufsz;
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	unsigned rb_blksz;
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	unsigned rb_blksz;
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{
1164
{
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	/* TODO: anythings to do here ? pipes ? */
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	/* TODO: anythings to do here ? pipes ? */
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	r100_hdp_reset(rdev);
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	r100_hdp_reset(rdev);
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}
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}
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void r100_hdp_reset(struct radeon_device *rdev)
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void r100_hdp_reset(struct radeon_device *rdev)
1173
{
1170
{
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	uint32_t tmp;
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	uint32_t tmp;
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	WREG32(RADEON_RBBM_SOFT_RESET, 0);
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	WREG32(RADEON_RBBM_SOFT_RESET, 0);
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	WREG32(RADEON_HOST_PATH_CNTL, tmp);
1181
	WREG32(RADEON_HOST_PATH_CNTL, tmp);
1185
	(void)RREG32(RADEON_HOST_PATH_CNTL);
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	(void)RREG32(RADEON_HOST_PATH_CNTL);
1186
}
1183
}
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1187
 
-
 
1188
 
1184
 
1189
int r100_rb2d_reset(struct radeon_device *rdev)
1185
int r100_rb2d_reset(struct radeon_device *rdev)
1190
{
1186
{
1191
	uint32_t tmp;
1187
	uint32_t tmp;
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1301
 
1306
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1302
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1307
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1303
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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-
 
1304
}
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}
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1309
 
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#endif
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1311
/*
1308
/*
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	r100_pll_errata_after_index(rdev);
1359
	r100_pll_errata_after_index(rdev);
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	WREG32(RADEON_CLOCK_CNTL_DATA, v);
1360
	WREG32(RADEON_CLOCK_CNTL_DATA, v);
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	r100_pll_errata_after_data(rdev);
1361
	r100_pll_errata_after_data(rdev);
1365
}
1362
}
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-
 
1367
#endif
-
 
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1369
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1364
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1370
{
1365
{
1371
	if (reg < 0x10000)
1366
	if (reg < 0x10000)
1372
		return readl(((void __iomem *)rdev->rmmio) + reg);
1367
		return readl(((void __iomem *)rdev->rmmio) + reg);
1373
	else {
1368
	else {
1374
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1369
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1375
		return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1370
		return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1376
	}
1371
	}
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}
-
 
1378
 
1372
}
1379
 
1373
 
1380
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1374
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1381
{
1375
{
1382
	if (reg < 0x10000)
1376
	if (reg < 0x10000)