WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/pci.c


 
 
#include 
 
#include 
#include 
#include 
#include 
#include 
 
#include 
 
 
extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);
 
static LIST_HEAD(devices);
 
/* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
#define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */
 
#define LEGACY_IO_RESOURCE      (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 
/*
 * Translate the low bits of the PCI base
 * to the resource type
 */
static inline unsigned int pci_calc_resource_flags(unsigned int flags)
{
    if (flags & PCI_BASE_ADDRESS_SPACE_IO)
        return IORESOURCE_IO;
 
    if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
        return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 
    return IORESOURCE_MEM;
}
 
 
static u32 pci_size(u32 base, u32 maxbase, u32 mask)
{
    u32 size = mask & maxbase;      /* Find the significant bits */
 
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
{
    u64 size = mask & maxbase;      /* Find the significant bits */
 
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static inline int is_64bit_memory(u32 mask)
{
    if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
        (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
        return 1;
    return 0;
}
 
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
{
    u32  pos, reg, next;
    u32  l, sz;
    struct resource *res;
 
    for(pos=0; pos < howmany; pos = next)
    {
        u64  l64;
        u64  sz64;
        u32  raw_sz;
 
        next = pos + 1;
 
        res  = &dev->resource[pos];
 
        reg = PCI_BASE_ADDRESS_0 + (pos << 2);
        l = PciRead32(dev->busnr, dev->devfn, reg);
        PciWrite32(dev->busnr, dev->devfn, reg, ~0);
        sz = PciRead32(dev->busnr, dev->devfn, reg);
        PciWrite32(dev->busnr, dev->devfn, reg, l);
 
        if (!sz || sz == 0xffffffff)
            continue;
 
        if (l == 0xffffffff)
            l = 0;
 
        raw_sz = sz;
        if ((l & PCI_BASE_ADDRESS_SPACE) ==
                        PCI_BASE_ADDRESS_SPACE_MEMORY)
        {
            sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
            /*
             * For 64bit prefetchable memory sz could be 0, if the
             * real size is bigger than 4G, so we need to check
             * szhi for that.
             */
            if (!is_64bit_memory(l) && !sz)
                    continue;
            res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
            res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
        }
        else {
            sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
            if (!sz)
                continue;
            res->start = l & PCI_BASE_ADDRESS_IO_MASK;
            res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
        }
        res->end = res->start + (unsigned long) sz;
        res->flags |= pci_calc_resource_flags(l);
        if (is_64bit_memory(l))
        {
            u32 szhi, lhi;
 
            lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
            PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
            szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
            PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
            sz64 = ((u64)szhi << 32) | raw_sz;
            l64 = ((u64)lhi << 32) | l;
            sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
            next++;
 
#if BITS_PER_LONG == 64
            if (!sz64) {
                res->start = 0;
                res->end = 0;
                res->flags = 0;
                continue;
            }
            res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
            res->end = res->start + sz64;
#else
            if (sz64 > 0x100000000ULL) {
                printk(KERN_ERR "PCI: Unable to handle 64-bit "
                                "BAR for device %s\n", pci_name(dev));
                res->start = 0;
                res->flags = 0;
            }
            else if (lhi)
            {
                /* 64-bit wide address, treat as disabled */
                PciWrite32(dev->busnr, dev->devfn, reg,
                        l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
                PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
                res->start = 0;
                res->end = sz;
            }
#endif
        }
    }
 
    if ( rom )
    {
        dev->rom_base_reg = rom;
        res = &dev->resource[PCI_ROM_RESOURCE];
 
        l = PciRead32(dev->busnr, dev->devfn, rom);
        PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
        sz = PciRead32(dev->busnr, dev->devfn, rom);
        PciWrite32(dev->busnr, dev->devfn, rom, l);
 
        if (l == 0xffffffff)
            l = 0;
 
        if (sz && sz != 0xffffffff)
        {
            sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
 
            if (sz)
            {
                res->flags = (l & IORESOURCE_ROM_ENABLE) |
                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |
                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
                res->start = l & PCI_ROM_ADDRESS_MASK;
                res->end = res->start + (unsigned long) sz;
            }
        }
    }
}
 
static void pci_read_irq(struct pci_dev *dev)
{
    u8 irq;
 
    irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
    dev->pin = irq;
    if (irq)
        irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
    dev->irq = irq;
};
 
 
int pci_setup_device(struct pci_dev *dev)
{
    u32  class;
 
    class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
    dev->revision = class & 0xff;
    class >>= 8;                                /* upper 3 bytes */
    dev->class = class;
 
    /* "Unknown power state" */
//    dev->current_state = PCI_UNKNOWN;
 
    /* Early fixups, before probing the BARs */
 //   pci_fixup_device(pci_fixup_early, dev);
    class = dev->class >> 8;
 
    switch (dev->hdr_type)
    {
        case PCI_HEADER_TYPE_NORMAL:                /* standard header */
            if (class == PCI_CLASS_BRIDGE_PCI)
                goto bad;
            pci_read_irq(dev);
            pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
            dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
            dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
 
            /*
             *      Do the ugly legacy mode stuff here rather than broken chip
             *      quirk code. Legacy mode ATA controllers have fixed
             *      addresses. These are not always echoed in BAR0-3, and
             *      BAR0-3 in a few cases contain junk!
             */
            if (class == PCI_CLASS_STORAGE_IDE)
            {
                u8 progif;
 
                progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
                if ((progif & 1) == 0)
                {
                    dev->resource[0].start = 0x1F0;
                    dev->resource[0].end = 0x1F7;
                    dev->resource[0].flags = LEGACY_IO_RESOURCE;
                    dev->resource[1].start = 0x3F6;
                    dev->resource[1].end = 0x3F6;
                    dev->resource[1].flags = LEGACY_IO_RESOURCE;
                }
                if ((progif & 4) == 0)
                {
                    dev->resource[2].start = 0x170;
                    dev->resource[2].end = 0x177;
                    dev->resource[2].flags = LEGACY_IO_RESOURCE;
                    dev->resource[3].start = 0x376;
                    dev->resource[3].end = 0x376;
                    dev->resource[3].flags = LEGACY_IO_RESOURCE;
                };
            }
            break;
 
        case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
                if (class != PCI_CLASS_BRIDGE_PCI)
                        goto bad;
                /* The PCI-to-PCI bridge spec requires that subtractive
                   decoding (i.e. transparent) bridge must have programming
                   interface code of 0x01. */
                pci_read_irq(dev);
                dev->transparent = ((dev->class & 0xff) == 1);
                pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
                break;
 
        case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
                if (class != PCI_CLASS_BRIDGE_CARDBUS)
                        goto bad;
                pci_read_irq(dev);
                pci_read_bases(dev, 1, 0);
                dev->subsystem_vendor = PciRead16(dev->busnr,
                                                  dev->devfn,
                                                  PCI_CB_SUBSYSTEM_VENDOR_ID);
 
                dev->subsystem_device = PciRead16(dev->busnr,
                                                  dev->devfn,
                                                  PCI_CB_SUBSYSTEM_ID);
                break;
 
        default:                                    /* unknown header */
                printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
                        pci_name(dev), dev->hdr_type);
                return -1;
 
        bad:
                printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
                       pci_name(dev), class, dev->hdr_type);
                dev->class = PCI_CLASS_NOT_DEFINED;
    }
 
    /* We found a fine healthy device, go go go... */
 
    return 0;
};
 
static pci_dev_t* pci_scan_device(u32 busnr, int devfn)
{
    pci_dev_t  *dev;
 
    u32   id;
    u8    hdr;
 
    int     timeout = 10;
 
    id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
 
    /* some broken boards return 0 or ~0 if a slot is empty: */
    if (id == 0xffffffff || id == 0x00000000 ||
        id == 0x0000ffff || id == 0xffff0000)
        return NULL;
 
    while (id == 0xffff0001)
    {
 
        delay(timeout/10);
        timeout *= 2;
 
        id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
 
        /* Card hasn't responded in 60 seconds?  Must be stuck. */
        if (timeout > 60 * 100)
        {
            printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
                   "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
            return NULL;
        }
    };
 
    if( pci_scan_filter(id, busnr, devfn) == 0)
        return NULL;
 
    hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
 
    dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
    if(unlikely(dev == NULL))
        return NULL;
 
    INIT_LIST_HEAD(&dev->link);
 
 
    dev->pci_dev.busnr    = busnr;
    dev->pci_dev.devfn    = devfn;
    dev->pci_dev.hdr_type = hdr & 0x7f;
    dev->pci_dev.multifunction    = !!(hdr & 0x80);
    dev->pci_dev.vendor   = id & 0xffff;
    dev->pci_dev.device   = (id >> 16) & 0xffff;
 
    pci_setup_device(&dev->pci_dev);
 
    return dev;
 
};
 
 
 
 
int _pci_scan_slot(u32 bus, int devfn)
{
    int  func, nr = 0;
 
    for (func = 0; func < 8; func++, devfn++)
    {
        pci_dev_t  *dev;
 
        dev = pci_scan_device(bus, devfn);
        if( dev )
        {
            list_add(&dev->link, &devices);
 
            nr++;
 
            /*
             * If this is a single function device,
             * don't scan past the first function.
             */
            if (!dev->pci_dev.multifunction)
            {
                if (func > 0) {
                    dev->pci_dev.multifunction = 1;
                }
                else {
                    break;
                }
             }
        }
        else {
            if (func == 0)
                break;
        }
    };
 
    return nr;
};
 
#define PCI_FIND_CAP_TTL    48
 
static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
                   u8 pos, int cap, int *ttl)
{
    u8 id;
 
    while ((*ttl)--) {
        pos = PciRead8(bus, devfn, pos);
        if (pos < 0x40)
            break;
        pos &= ~3;
        id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
        if (id == 0xff)
            break;
        if (id == cap)
            return pos;
        pos += PCI_CAP_LIST_NEXT;
    }
    return 0;
}
 
static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
                   u8 pos, int cap)
{
    int ttl = PCI_FIND_CAP_TTL;
 
    return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
}
 
static int __pci_bus_find_cap_start(unsigned int bus,
                    unsigned int devfn, u8 hdr_type)
{
    u16 status;
 
    status = PciRead16(bus, devfn, PCI_STATUS);
    if (!(status & PCI_STATUS_CAP_LIST))
        return 0;
 
    switch (hdr_type) {
    case PCI_HEADER_TYPE_NORMAL:
    case PCI_HEADER_TYPE_BRIDGE:
        return PCI_CAPABILITY_LIST;
    case PCI_HEADER_TYPE_CARDBUS:
        return PCI_CB_CAPABILITY_LIST;
    default:
        return 0;
    }
 
    return 0;
}
 
 
int pci_find_capability(struct pci_dev *dev, int cap)
{
    int pos;
 
    pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
    if (pos)
        pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
 
    return pos;
}
 
 
 
 
int enum_pci_devices()
{
    pci_dev_t  *dev;
    u32       last_bus;
    u32       bus = 0 , devfn = 0;
 
 
    last_bus = PciApi(1);
 
 
    if( unlikely(last_bus == -1))
        return -1;
 
    for(;bus <= last_bus; bus++)
    {
        for (devfn = 0; devfn < 0x100; devfn += 8)
            _pci_scan_slot(bus, devfn);
 
 
    }
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",
                dev->pci_dev.vendor,
                dev->pci_dev.device,
                dev->pci_dev.busnr,
                dev->pci_dev.devfn);
 
    }
    return 0;
}
 
const struct pci_device_id* find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist)
{
    pci_dev_t *dev;
    const struct pci_device_id *ent;
 
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.vendor != idlist->vendor )
            continue;
 
        for(ent = idlist; ent->vendor != 0; ent++)
        {
            if(unlikely(ent->device == dev->pci_dev.device))
            {
                pdev->pci_dev = dev->pci_dev;
                return  ent;
            }
        };
    }
 
    return NULL;
};
 
struct pci_dev *
pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
{
    pci_dev_t *dev;
 
    dev = (pci_dev_t*)devices.next;
 
    if(from != NULL)
    {
        for(; &dev->link != &devices;
            dev = (pci_dev_t*)dev->link.next)
        {
            if( &dev->pci_dev == from)
            {
                dev = (pci_dev_t*)dev->link.next;
                break;
            };
        }
    };
 
    for(; &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.vendor != vendor )
                continue;
 
        if(dev->pci_dev.device == device)
        {
            return &dev->pci_dev;
        }
    }
    return NULL;
};
 
 
struct pci_dev * _pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
{
    pci_dev_t *dev;
 
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn)
            return &dev->pci_dev;
    }
    return NULL;
}
 
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
{
    pci_dev_t *dev;
 
    dev = (pci_dev_t*)devices.next;
 
    if(from != NULL)
    {
        for(; &dev->link != &devices;
            dev = (pci_dev_t*)dev->link.next)
        {
            if( &dev->pci_dev == from)
            {
                dev = (pci_dev_t*)dev->link.next;
                break;
            };
        }
    };
 
    for(; &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.class == class)
        {
            return &dev->pci_dev;
        }
    }
 
   return NULL;
}
 
 
#define PIO_OFFSET      0x10000UL
#define PIO_MASK        0x0ffffUL
#define PIO_RESERVED    0x40000UL
 
#define IO_COND(addr, is_pio, is_mmio) do {            \
    unsigned long port = (unsigned long __force)addr;  \
    if (port >= PIO_RESERVED) {                        \
        is_mmio;                                       \
    } else if (port > PIO_OFFSET) {                    \
        port &= PIO_MASK;                              \
        is_pio;                                        \
    };                                                 \
} while (0)
 
/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
    if (port > PIO_MASK)
        return NULL;
    return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
}
 
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
    resource_size_t start = pci_resource_start(dev, bar);
    resource_size_t len = pci_resource_len(dev, bar);
    unsigned long flags = pci_resource_flags(dev, bar);
 
    if (!len || !start)
        return NULL;
    if (maxlen && len > maxlen)
        len = maxlen;
    if (flags & IORESOURCE_IO)
        return ioport_map(start, len);
    if (flags & IORESOURCE_MEM) {
        return ioremap(start, len);
    }
    /* What? */
    return NULL;
}
 
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
    IO_COND(addr, /* nothing */, iounmap(addr));
}
 
 
 
 
 
 
 
 
 
 
 
int pci_enable_rom(struct pci_dev *pdev)
{
    struct resource *res = pdev->resource + PCI_ROM_RESOURCE;
    struct pci_bus_region region;
    u32 rom_addr;
 
    if (!res->flags)
            return -1;
 
    _pcibios_resource_to_bus(pdev, ®ion, res);
    pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
    rom_addr &= ~PCI_ROM_ADDRESS_MASK;
    rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;
    pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
    return 0;
}
 
void pci_disable_rom(struct pci_dev *pdev)
{
    u32 rom_addr;
    pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
    rom_addr &= ~PCI_ROM_ADDRESS_ENABLE;
    pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
}
 
/**
 * pci_get_rom_size - obtain the actual size of the ROM image
 * @pdev: target PCI device
 * @rom: kernel virtual pointer to image of ROM
 * @size: size of PCI window
 *  return: size of actual ROM image
 *
 * Determine the actual length of the ROM image.
 * The PCI window size could be much larger than the
 * actual image size.
 */
size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
{
        void __iomem *image;
        int last_image;
 
        image = rom;
        do {
                void __iomem *pds;
                /* Standard PCI ROMs start out with these bytes 55 AA */
                if (readb(image) != 0x55) {
                        dev_err(&pdev->dev, "Invalid ROM contents\n");
                        break;
            }
                if (readb(image + 1) != 0xAA)
                        break;
                /* get the PCI data structure and check its signature */
                pds = image + readw(image + 24);
                if (readb(pds) != 'P')
                        break;
                if (readb(pds + 1) != 'C')
                        break;
                if (readb(pds + 2) != 'I')
                        break;
                if (readb(pds + 3) != 'R')
                        break;
                last_image = readb(pds + 21) & 0x80;
                /* this length is reliable */
                image += readw(pds + 16) * 512;
        } while (!last_image);
 
        /* never return a size larger than the PCI resource window */
        /* there are known ROMs that get the size wrong */
        return min((size_t)(image - rom), size);
}
 
 
/**
 * pci_map_rom - map a PCI ROM to kernel space
 * @pdev: pointer to pci device struct
 * @size: pointer to receive size of pci window over ROM
 *
 * Return: kernel virtual pointer to image of ROM
 *
 * Map a PCI ROM into kernel space. If ROM is boot video ROM,
 * the shadow BIOS copy will be returned instead of the
 * actual ROM.
 */
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
{
    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
    loff_t start;
    void __iomem *rom;
 
    /*
     * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
     * memory map if the VGA enable bit of the Bridge Control register is
     * set for embedded VGA.
     */
    if (res->flags & IORESOURCE_ROM_SHADOW) {
        /* primary video rom always starts here */
        start = (loff_t)0xC0000;
        *size = 0x20000; /* cover C000:0 through E000:0 */
    } else {
                if (res->flags &
                        (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
            *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
             return (void __iomem *)(unsigned long)
             pci_resource_start(pdev, PCI_ROM_RESOURCE);
        } else {
    				start = (loff_t)0xC0000;
    				*size = 0x20000; /* cover C000:0 through E000:0 */
 
        }
    }
 
    rom = ioremap(start, *size);
    if (!rom) {
            /* restore enable if ioremap fails */
            if (!(res->flags & (IORESOURCE_ROM_ENABLE |
                                IORESOURCE_ROM_SHADOW |
                                IORESOURCE_ROM_COPY)))
                    pci_disable_rom(pdev);
            return NULL;
    }
 
    /*
     * Try to find the true size of the ROM since sometimes the PCI window
     * size is much larger than the actual size of the ROM.
     * True size is important if the ROM is going to be copied.
     */
    *size = pci_get_rom_size(pdev, rom, *size);
    return rom;
}
 
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
{
    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
 
    if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY))
            return;
 
    iounmap(rom);
 
    /* Disable again before continuing, leave enabled if pci=rom */
    if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW)))
            pci_disable_rom(pdev);
}
 
static void __pci_set_master(struct pci_dev *dev, bool enable)
{
    u16 old_cmd, cmd;
 
    pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
    if (enable)
        cmd = old_cmd | PCI_COMMAND_MASTER;
    else
        cmd = old_cmd & ~PCI_COMMAND_MASTER;
    if (cmd != old_cmd) {
            dbgprintf("%s bus mastering\n",
                    enable ? "enabling" : "disabling");
        pci_write_config_word(dev, PCI_COMMAND, cmd);
        }
    dev->is_busmaster = enable;
}
 
 
/* pci_set_master - enables bus-mastering for device dev
 * @dev: the PCI device to enable
 *
 * Enables bus-mastering on the device and calls pcibios_set_master()
 * to do the needed arch specific settings.
 */
void pci_set_master(struct pci_dev *dev)
{
        __pci_set_master(dev, true);
//        pcibios_set_master(dev);
}
 
/**
 * pci_clear_master - disables bus-mastering for device dev
 * @dev: the PCI device to disable
 */
void pci_clear_master(struct pci_dev *dev)
{
        __pci_set_master(dev, false);
}
 
 
static inline int pcie_cap_version(const struct pci_dev *dev)
{
    return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS;
}
 
static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
{
    return true;
}
 
static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           type == PCI_EXP_TYPE_ENDPOINT ||
           type == PCI_EXP_TYPE_LEG_END;
}
 
static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           (type == PCI_EXP_TYPE_DOWNSTREAM &&
        dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);
}
 
static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           type == PCI_EXP_TYPE_RC_EC;
}
 
static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
{
    if (!pci_is_pcie(dev))
        return false;
 
    switch (pos) {
    case PCI_EXP_FLAGS_TYPE:
        return true;
    case PCI_EXP_DEVCAP:
    case PCI_EXP_DEVCTL:
    case PCI_EXP_DEVSTA:
        return pcie_cap_has_devctl(dev);
    case PCI_EXP_LNKCAP:
    case PCI_EXP_LNKCTL:
    case PCI_EXP_LNKSTA:
        return pcie_cap_has_lnkctl(dev);
    case PCI_EXP_SLTCAP:
    case PCI_EXP_SLTCTL:
    case PCI_EXP_SLTSTA:
        return pcie_cap_has_sltctl(dev);
    case PCI_EXP_RTCTL:
    case PCI_EXP_RTCAP:
    case PCI_EXP_RTSTA:
        return pcie_cap_has_rtctl(dev);
    case PCI_EXP_DEVCAP2:
    case PCI_EXP_DEVCTL2:
    case PCI_EXP_LNKCAP2:
    case PCI_EXP_LNKCTL2:
    case PCI_EXP_LNKSTA2:
        return pcie_cap_version(dev) > 1;
    default:
        return false;
    }
}
 
/*
 * Note that these accessor functions are only for the "PCI Express
 * Capability" (see PCIe spec r3.0, sec 7.8).  They do not apply to the
 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
 */
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
{
    int ret;
 
    *val = 0;
    if (pos & 1)
        return -EINVAL;
 
    if (pcie_capability_reg_implemented(dev, pos)) {
        ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
        /*
         * Reset *val to 0 if pci_read_config_word() fails, it may
         * have been written as 0xFFFF if hardware error happens
         * during pci_read_config_word().
         */
        if (ret)
            *val = 0;
        return ret;
    }
 
    /*
     * For Functions that do not implement the Slot Capabilities,
     * Slot Status, and Slot Control registers, these spaces must
     * be hardwired to 0b, with the exception of the Presence Detect
     * State bit in the Slot Status register of Downstream Ports,
     * which must be hardwired to 1b.  (PCIe Base Spec 3.0, sec 7.8)
     */
    if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
         pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
        *val = PCI_EXP_SLTSTA_PDS;
    }
 
    return 0;
}
EXPORT_SYMBOL(pcie_capability_read_word);
 
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
{
    int ret;
 
    *val = 0;
    if (pos & 3)
        return -EINVAL;
 
    if (pcie_capability_reg_implemented(dev, pos)) {
        ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
        /*
         * Reset *val to 0 if pci_read_config_dword() fails, it may
         * have been written as 0xFFFFFFFF if hardware error happens
         * during pci_read_config_dword().
         */
        if (ret)
            *val = 0;
        return ret;
    }
 
    if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
         pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
        *val = PCI_EXP_SLTSTA_PDS;
    }
 
    return 0;
}
EXPORT_SYMBOL(pcie_capability_read_dword);
 
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
{
    if (pos & 1)
        return -EINVAL;
 
    if (!pcie_capability_reg_implemented(dev, pos))
        return 0;
 
    return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_word);
 
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
{
    if (pos & 3)
        return -EINVAL;
 
    if (!pcie_capability_reg_implemented(dev, pos))
        return 0;
 
    return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_dword);
 
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
                                       u16 clear, u16 set)
{
        int ret;
        u16 val;
 
        ret = pcie_capability_read_word(dev, pos, &val);
        if (!ret) {
                val &= ~clear;
                val |= set;
                ret = pcie_capability_write_word(dev, pos, val);
        }
 
        return ret;
}
 
 
 
int pcie_get_readrq(struct pci_dev *dev)
{
        u16 ctl;
 
        pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
 
        return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
}
EXPORT_SYMBOL(pcie_get_readrq);
 
/**
 * pcie_set_readrq - set PCI Express maximum memory read request
 * @dev: PCI device to query
 * @rq: maximum memory read count in bytes
 *    valid values are 128, 256, 512, 1024, 2048, 4096
 *
 * If possible sets maximum memory read request in bytes
 */
int pcie_set_readrq(struct pci_dev *dev, int rq)
{
        u16 v;
 
        if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
                return -EINVAL;
 
        v = (ffs(rq) - 8) << 12;
 
        return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
                                                  PCI_EXP_DEVCTL_READRQ, v);
}

Rev 6104	Rev 6321
1	#define CONFIG_PCI	-
2		-
3	#include	1	#include
4		2
5	#include	3	#include
6	#include	4	#include
7	#include	5	#include
8	#include	6	#include
9	#include	7	#include
10		8
11	#include	9	#include
12		-
13		10
14	extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);	11	extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);
15		12
16	static LIST_HEAD(devices);	13	static LIST_HEAD(devices);
17		14
18	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */	15	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
19	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */	16	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
20		17
21	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)	18	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)
22		19
23	/*	20	/*
24	* Translate the low bits of the PCI base	21	* Translate the low bits of the PCI base
25	* to the resource type	22	* to the resource type
26	*/	23	*/
27	static inline unsigned int pci_calc_resource_flags(unsigned int flags)	24	static inline unsigned int pci_calc_resource_flags(unsigned int flags)
28	{	25	{
29	if (flags & PCI_BASE_ADDRESS_SPACE_IO)	26	if (flags & PCI_BASE_ADDRESS_SPACE_IO)
30	return IORESOURCE_IO;	27	return IORESOURCE_IO;
31		28
32	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)	29	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
33	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;	30	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;
34		31
35	return IORESOURCE_MEM;	32	return IORESOURCE_MEM;
36	}	33	}
37		34
38		35
39	static u32 pci_size(u32 base, u32 maxbase, u32 mask)	36	static u32 pci_size(u32 base, u32 maxbase, u32 mask)
40	{	37	{
41	u32 size = mask & maxbase; /* Find the significant bits */	38	u32 size = mask & maxbase; /* Find the significant bits */
42		39
43	if (!size)	40	if (!size)
44	return 0;	41	return 0;
45		42
46	/* Get the lowest of them to find the decode size, and	43	/* Get the lowest of them to find the decode size, and
47	from that the extent. */	44	from that the extent. */
48	size = (size & ~(size-1)) - 1;	45	size = (size & ~(size-1)) - 1;
49		46
50	/* base == maxbase can be valid only if the BAR has	47	/* base == maxbase can be valid only if the BAR has
51	already been programmed with all 1s. */	48	already been programmed with all 1s. */
52	if (base == maxbase && ((base \| size) & mask) != mask)	49	if (base == maxbase && ((base \| size) & mask) != mask)
53	return 0;	50	return 0;
54		51
55	return size;	52	return size;
56	}	53	}
57		54
58	static u64 pci_size64(u64 base, u64 maxbase, u64 mask)	55	static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
59	{	56	{
60	u64 size = mask & maxbase; /* Find the significant bits */	57	u64 size = mask & maxbase; /* Find the significant bits */
61		58
62	if (!size)	59	if (!size)
63	return 0;	60	return 0;
64		61
65	/* Get the lowest of them to find the decode size, and	62	/* Get the lowest of them to find the decode size, and
66	from that the extent. */	63	from that the extent. */
67	size = (size & ~(size-1)) - 1;	64	size = (size & ~(size-1)) - 1;
68		65
69	/* base == maxbase can be valid only if the BAR has	66	/* base == maxbase can be valid only if the BAR has
70	already been programmed with all 1s. */	67	already been programmed with all 1s. */
71	if (base == maxbase && ((base \| size) & mask) != mask)	68	if (base == maxbase && ((base \| size) & mask) != mask)
72	return 0;	69	return 0;
73		70
74	return size;	71	return size;
75	}	72	}
76		73
77	static inline int is_64bit_memory(u32 mask)	74	static inline int is_64bit_memory(u32 mask)
78	{	75	{
79	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==	76	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
80	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))	77	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))
81	return 1;	78	return 1;
82	return 0;	79	return 0;
83	}	80	}
84		81
85	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)	82	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
86	{	83	{
87	u32 pos, reg, next;	84	u32 pos, reg, next;
88	u32 l, sz;	85	u32 l, sz;
89	struct resource *res;	86	struct resource *res;
90		87
91	for(pos=0; pos < howmany; pos = next)	88	for(pos=0; pos < howmany; pos = next)
92	{	89	{
93	u64 l64;	90	u64 l64;
94	u64 sz64;	91	u64 sz64;
95	u32 raw_sz;	92	u32 raw_sz;
96		93
97	next = pos + 1;	94	next = pos + 1;
98		95
99	res = &dev->resource[pos];	96	res = &dev->resource[pos];
100		97
101	reg = PCI_BASE_ADDRESS_0 + (pos << 2);	98	reg = PCI_BASE_ADDRESS_0 + (pos << 2);
102	l = PciRead32(dev->busnr, dev->devfn, reg);	99	l = PciRead32(dev->busnr, dev->devfn, reg);
103	PciWrite32(dev->busnr, dev->devfn, reg, ~0);	100	PciWrite32(dev->busnr, dev->devfn, reg, ~0);
104	sz = PciRead32(dev->busnr, dev->devfn, reg);	101	sz = PciRead32(dev->busnr, dev->devfn, reg);
105	PciWrite32(dev->busnr, dev->devfn, reg, l);	102	PciWrite32(dev->busnr, dev->devfn, reg, l);
106		103
107	if (!sz \|\| sz == 0xffffffff)	104	if (!sz \|\| sz == 0xffffffff)
108	continue;	105	continue;
109		106
110	if (l == 0xffffffff)	107	if (l == 0xffffffff)
111	l = 0;	108	l = 0;
112		109
113	raw_sz = sz;	110	raw_sz = sz;
114	if ((l & PCI_BASE_ADDRESS_SPACE) ==	111	if ((l & PCI_BASE_ADDRESS_SPACE) ==
115	PCI_BASE_ADDRESS_SPACE_MEMORY)	112	PCI_BASE_ADDRESS_SPACE_MEMORY)
116	{	113	{
117	sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);	114	sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
118	/*	115	/*
119	* For 64bit prefetchable memory sz could be 0, if the	116	* For 64bit prefetchable memory sz could be 0, if the
120	* real size is bigger than 4G, so we need to check	117	* real size is bigger than 4G, so we need to check
121	* szhi for that.	118	* szhi for that.
122	*/	119	*/
123	if (!is_64bit_memory(l) && !sz)	120	if (!is_64bit_memory(l) && !sz)
124	continue;	121	continue;
125	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;	122	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
126	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;	123	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;
127	}	124	}
128	else {	125	else {
129	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);	126	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
130	if (!sz)	127	if (!sz)
131	continue;	128	continue;
132	res->start = l & PCI_BASE_ADDRESS_IO_MASK;	129	res->start = l & PCI_BASE_ADDRESS_IO_MASK;
133	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;	130	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;
134	}	131	}
135	res->end = res->start + (unsigned long) sz;	132	res->end = res->start + (unsigned long) sz;
136	res->flags \|= pci_calc_resource_flags(l);	133	res->flags \|= pci_calc_resource_flags(l);
137	if (is_64bit_memory(l))	134	if (is_64bit_memory(l))
138	{	135	{
139	u32 szhi, lhi;	136	u32 szhi, lhi;
140		137
141	lhi = PciRead32(dev->busnr, dev->devfn, reg+4);	138	lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
142	PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);	139	PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
143	szhi = PciRead32(dev->busnr, dev->devfn, reg+4);	140	szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
144	PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);	141	PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
145	sz64 = ((u64)szhi << 32) \| raw_sz;	142	sz64 = ((u64)szhi << 32) \| raw_sz;
146	l64 = ((u64)lhi << 32) \| l;	143	l64 = ((u64)lhi << 32) \| l;
147	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);	144	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
148	next++;	145	next++;
149		146
150	#if BITS_PER_LONG == 64	147	#if BITS_PER_LONG == 64
151	if (!sz64) {	148	if (!sz64) {
152	res->start = 0;	149	res->start = 0;
153	res->end = 0;	150	res->end = 0;
154	res->flags = 0;	151	res->flags = 0;
155	continue;	152	continue;
156	}	153	}
157	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;	154	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
158	res->end = res->start + sz64;	155	res->end = res->start + sz64;
159	#else	156	#else
160	if (sz64 > 0x100000000ULL) {	157	if (sz64 > 0x100000000ULL) {
161	printk(KERN_ERR "PCI: Unable to handle 64-bit "	158	printk(KERN_ERR "PCI: Unable to handle 64-bit "
162	"BAR for device %s\n", pci_name(dev));	159	"BAR for device %s\n", pci_name(dev));
163	res->start = 0;	160	res->start = 0;
164	res->flags = 0;	161	res->flags = 0;
165	}	162	}
166	else if (lhi)	163	else if (lhi)
167	{	164	{
168	/* 64-bit wide address, treat as disabled */	165	/* 64-bit wide address, treat as disabled */
169	PciWrite32(dev->busnr, dev->devfn, reg,	166	PciWrite32(dev->busnr, dev->devfn, reg,
170	l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);	167	l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
171	PciWrite32(dev->busnr, dev->devfn, reg+4, 0);	168	PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
172	res->start = 0;	169	res->start = 0;
173	res->end = sz;	170	res->end = sz;
174	}	171	}
175	#endif	172	#endif
176	}	173	}
177	}	174	}
178		175
179	if ( rom )	176	if ( rom )
180	{	177	{
181	dev->rom_base_reg = rom;	178	dev->rom_base_reg = rom;
182	res = &dev->resource[PCI_ROM_RESOURCE];	179	res = &dev->resource[PCI_ROM_RESOURCE];
183		180
184	l = PciRead32(dev->busnr, dev->devfn, rom);	181	l = PciRead32(dev->busnr, dev->devfn, rom);
185	PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);	182	PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
186	sz = PciRead32(dev->busnr, dev->devfn, rom);	183	sz = PciRead32(dev->busnr, dev->devfn, rom);
187	PciWrite32(dev->busnr, dev->devfn, rom, l);	184	PciWrite32(dev->busnr, dev->devfn, rom, l);
188		185
189	if (l == 0xffffffff)	186	if (l == 0xffffffff)
190	l = 0;	187	l = 0;
191		188
192	if (sz && sz != 0xffffffff)	189	if (sz && sz != 0xffffffff)
193	{	190	{
194	sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);	191	sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
195		192
196	if (sz)	193	if (sz)
197	{	194	{
198	res->flags = (l & IORESOURCE_ROM_ENABLE) \|	195	res->flags = (l & IORESOURCE_ROM_ENABLE) \|
199	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|	196	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|
200	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;	197	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;
201	res->start = l & PCI_ROM_ADDRESS_MASK;	198	res->start = l & PCI_ROM_ADDRESS_MASK;
202	res->end = res->start + (unsigned long) sz;	199	res->end = res->start + (unsigned long) sz;
203	}	200	}
204	}	201	}
205	}	202	}
206	}	203	}
207		204
208	static void pci_read_irq(struct pci_dev *dev)	205	static void pci_read_irq(struct pci_dev *dev)
209	{	206	{
210	u8 irq;	207	u8 irq;
211		208
212	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);	209	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
213	dev->pin = irq;	210	dev->pin = irq;
214	if (irq)	211	if (irq)
215	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);	212	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
216	dev->irq = irq;	213	dev->irq = irq;
217	};	214	};
218		215
219		216
220	int pci_setup_device(struct pci_dev *dev)	217	int pci_setup_device(struct pci_dev *dev)
221	{	218	{
222	u32 class;	219	u32 class;
223		220
224	class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);	221	class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
225	dev->revision = class & 0xff;	222	dev->revision = class & 0xff;
226	class >>= 8; /* upper 3 bytes */	223	class >>= 8; /* upper 3 bytes */
227	dev->class = class;	224	dev->class = class;
228		225
229	/* "Unknown power state" */	226	/* "Unknown power state" */
230	// dev->current_state = PCI_UNKNOWN;	227	// dev->current_state = PCI_UNKNOWN;
231		228
232	/* Early fixups, before probing the BARs */	229	/* Early fixups, before probing the BARs */
233	// pci_fixup_device(pci_fixup_early, dev);	230	// pci_fixup_device(pci_fixup_early, dev);
234	class = dev->class >> 8;	231	class = dev->class >> 8;
235		232
236	switch (dev->hdr_type)	233	switch (dev->hdr_type)
237	{	234	{
238	case PCI_HEADER_TYPE_NORMAL: /* standard header */	235	case PCI_HEADER_TYPE_NORMAL: /* standard header */
239	if (class == PCI_CLASS_BRIDGE_PCI)	236	if (class == PCI_CLASS_BRIDGE_PCI)
240	goto bad;	237	goto bad;
241	pci_read_irq(dev);	238	pci_read_irq(dev);
242	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);	239	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
243	dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);	240	dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
244	dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);	241	dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
245		242
246	/*	243	/*
247	* Do the ugly legacy mode stuff here rather than broken chip	244	* Do the ugly legacy mode stuff here rather than broken chip
248	* quirk code. Legacy mode ATA controllers have fixed	245	* quirk code. Legacy mode ATA controllers have fixed
249	* addresses. These are not always echoed in BAR0-3, and	246	* addresses. These are not always echoed in BAR0-3, and
250	* BAR0-3 in a few cases contain junk!	247	* BAR0-3 in a few cases contain junk!
251	*/	248	*/
252	if (class == PCI_CLASS_STORAGE_IDE)	249	if (class == PCI_CLASS_STORAGE_IDE)
253	{	250	{
254	u8 progif;	251	u8 progif;
255		252
256	progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);	253	progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
257	if ((progif & 1) == 0)	254	if ((progif & 1) == 0)
258	{	255	{
259	dev->resource[0].start = 0x1F0;	256	dev->resource[0].start = 0x1F0;
260	dev->resource[0].end = 0x1F7;	257	dev->resource[0].end = 0x1F7;
261	dev->resource[0].flags = LEGACY_IO_RESOURCE;	258	dev->resource[0].flags = LEGACY_IO_RESOURCE;
262	dev->resource[1].start = 0x3F6;	259	dev->resource[1].start = 0x3F6;
263	dev->resource[1].end = 0x3F6;	260	dev->resource[1].end = 0x3F6;
264	dev->resource[1].flags = LEGACY_IO_RESOURCE;	261	dev->resource[1].flags = LEGACY_IO_RESOURCE;
265	}	262	}
266	if ((progif & 4) == 0)	263	if ((progif & 4) == 0)
267	{	264	{
268	dev->resource[2].start = 0x170;	265	dev->resource[2].start = 0x170;
269	dev->resource[2].end = 0x177;	266	dev->resource[2].end = 0x177;
270	dev->resource[2].flags = LEGACY_IO_RESOURCE;	267	dev->resource[2].flags = LEGACY_IO_RESOURCE;
271	dev->resource[3].start = 0x376;	268	dev->resource[3].start = 0x376;
272	dev->resource[3].end = 0x376;	269	dev->resource[3].end = 0x376;
273	dev->resource[3].flags = LEGACY_IO_RESOURCE;	270	dev->resource[3].flags = LEGACY_IO_RESOURCE;
274	};	271	};
275	}	272	}
276	break;	273	break;
277		274
278	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */	275	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
279	if (class != PCI_CLASS_BRIDGE_PCI)	276	if (class != PCI_CLASS_BRIDGE_PCI)
280	goto bad;	277	goto bad;
281	/* The PCI-to-PCI bridge spec requires that subtractive	278	/* The PCI-to-PCI bridge spec requires that subtractive
282	decoding (i.e. transparent) bridge must have programming	279	decoding (i.e. transparent) bridge must have programming
283	interface code of 0x01. */	280	interface code of 0x01. */
284	pci_read_irq(dev);	281	pci_read_irq(dev);
285	dev->transparent = ((dev->class & 0xff) == 1);	282	dev->transparent = ((dev->class & 0xff) == 1);
286	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);	283	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
287	break;	284	break;
288		285
289	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */	286	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
290	if (class != PCI_CLASS_BRIDGE_CARDBUS)	287	if (class != PCI_CLASS_BRIDGE_CARDBUS)
291	goto bad;	288	goto bad;
292	pci_read_irq(dev);	289	pci_read_irq(dev);
293	pci_read_bases(dev, 1, 0);	290	pci_read_bases(dev, 1, 0);
294	dev->subsystem_vendor = PciRead16(dev->busnr,	291	dev->subsystem_vendor = PciRead16(dev->busnr,
295	dev->devfn,	292	dev->devfn,
296	PCI_CB_SUBSYSTEM_VENDOR_ID);	293	PCI_CB_SUBSYSTEM_VENDOR_ID);
297		294
298	dev->subsystem_device = PciRead16(dev->busnr,	295	dev->subsystem_device = PciRead16(dev->busnr,
299	dev->devfn,	296	dev->devfn,
300	PCI_CB_SUBSYSTEM_ID);	297	PCI_CB_SUBSYSTEM_ID);
301	break;	298	break;
302		299
303	default: /* unknown header */	300	default: /* unknown header */
304	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",	301	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
305	pci_name(dev), dev->hdr_type);	302	pci_name(dev), dev->hdr_type);
306	return -1;	303	return -1;
307		304
308	bad:	305	bad:
309	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",	306	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
310	pci_name(dev), class, dev->hdr_type);	307	pci_name(dev), class, dev->hdr_type);
311	dev->class = PCI_CLASS_NOT_DEFINED;	308	dev->class = PCI_CLASS_NOT_DEFINED;
312	}	309	}
313		310
314	/* We found a fine healthy device, go go go... */	311	/* We found a fine healthy device, go go go... */
315		312
316	return 0;	313	return 0;
317	};	314	};
318		315
319	static pci_dev_t* pci_scan_device(u32 busnr, int devfn)	316	static pci_dev_t* pci_scan_device(u32 busnr, int devfn)
320	{	317	{
321	pci_dev_t *dev;	318	pci_dev_t *dev;
322		319
323	u32 id;	320	u32 id;
324	u8 hdr;	321	u8 hdr;
325		322
326	int timeout = 10;	323	int timeout = 10;
327		324
328	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);	325	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
329		326
330	/* some broken boards return 0 or ~0 if a slot is empty: */	327	/* some broken boards return 0 or ~0 if a slot is empty: */
331	if (id == 0xffffffff \|\| id == 0x00000000 \|\|	328	if (id == 0xffffffff \|\| id == 0x00000000 \|\|
332	id == 0x0000ffff \|\| id == 0xffff0000)	329	id == 0x0000ffff \|\| id == 0xffff0000)
333	return NULL;	330	return NULL;
334		331
335	while (id == 0xffff0001)	332	while (id == 0xffff0001)
336	{	333	{
337		334
338	delay(timeout/10);	335	delay(timeout/10);
339	timeout *= 2;	336	timeout *= 2;
340		337
341	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);	338	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
342		339
343	/* Card hasn't responded in 60 seconds? Must be stuck. */	340	/* Card hasn't responded in 60 seconds? Must be stuck. */
344	if (timeout > 60 * 100)	341	if (timeout > 60 * 100)
345	{	342	{
346	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "	343	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
347	"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));	344	"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
348	return NULL;	345	return NULL;
349	}	346	}
350	};	347	};
351		348
352	if( pci_scan_filter(id, busnr, devfn) == 0)	349	if( pci_scan_filter(id, busnr, devfn) == 0)
353	return NULL;	350	return NULL;
354		351
355	hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);	352	hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
356		353
357	dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);	354	dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
358	if(unlikely(dev == NULL))	355	if(unlikely(dev == NULL))
359	return NULL;	356	return NULL;
360		357
361	INIT_LIST_HEAD(&dev->link);	358	INIT_LIST_HEAD(&dev->link);
362		359
363		360
364	dev->pci_dev.busnr = busnr;	361	dev->pci_dev.busnr = busnr;
365	dev->pci_dev.devfn = devfn;	362	dev->pci_dev.devfn = devfn;
366	dev->pci_dev.hdr_type = hdr & 0x7f;	363	dev->pci_dev.hdr_type = hdr & 0x7f;
367	dev->pci_dev.multifunction = !!(hdr & 0x80);	364	dev->pci_dev.multifunction = !!(hdr & 0x80);
368	dev->pci_dev.vendor = id & 0xffff;	365	dev->pci_dev.vendor = id & 0xffff;
369	dev->pci_dev.device = (id >> 16) & 0xffff;	366	dev->pci_dev.device = (id >> 16) & 0xffff;
370		367
371	pci_setup_device(&dev->pci_dev);	368	pci_setup_device(&dev->pci_dev);
372		369
373	return dev;	370	return dev;
374		371
375	};	372	};
376		373
377		374
378		375
379		376
380	int _pci_scan_slot(u32 bus, int devfn)	377	int _pci_scan_slot(u32 bus, int devfn)
381	{	378	{
382	int func, nr = 0;	379	int func, nr = 0;
383		380
384	for (func = 0; func < 8; func++, devfn++)	381	for (func = 0; func < 8; func++, devfn++)
385	{	382	{
386	pci_dev_t *dev;	383	pci_dev_t *dev;
387		384
388	dev = pci_scan_device(bus, devfn);	385	dev = pci_scan_device(bus, devfn);
389	if( dev )	386	if( dev )
390	{	387	{
391	list_add(&dev->link, &devices);	388	list_add(&dev->link, &devices);
392		389
393	nr++;	390	nr++;
394		391
395	/*	392	/*
396	* If this is a single function device,	393	* If this is a single function device,
397	* don't scan past the first function.	394	* don't scan past the first function.
398	*/	395	*/
399	if (!dev->pci_dev.multifunction)	396	if (!dev->pci_dev.multifunction)
400	{	397	{
401	if (func > 0) {	398	if (func > 0) {
402	dev->pci_dev.multifunction = 1;	399	dev->pci_dev.multifunction = 1;
403	}	400	}
404	else {	401	else {
405	break;	402	break;
406	}	403	}
407	}	404	}
408	}	405	}
409	else {	406	else {
410	if (func == 0)	407	if (func == 0)
411	break;	408	break;
412	}	409	}
413	};	410	};
414		411
415	return nr;	412	return nr;
416	};	413	};
417		414
418	#define PCI_FIND_CAP_TTL 48	415	#define PCI_FIND_CAP_TTL 48
419		416
420	static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,	417	static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
421	u8 pos, int cap, int *ttl)	418	u8 pos, int cap, int *ttl)
422	{	419	{
423	u8 id;	420	u8 id;
424		421
425	while ((*ttl)--) {	422	while ((*ttl)--) {
426	pos = PciRead8(bus, devfn, pos);	423	pos = PciRead8(bus, devfn, pos);
427	if (pos < 0x40)	424	if (pos < 0x40)
428	break;	425	break;
429	pos &= ~3;	426	pos &= ~3;
430	id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);	427	id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
431	if (id == 0xff)	428	if (id == 0xff)
432	break;	429	break;
433	if (id == cap)	430	if (id == cap)
434	return pos;	431	return pos;
435	pos += PCI_CAP_LIST_NEXT;	432	pos += PCI_CAP_LIST_NEXT;
436	}	433	}
437	return 0;	434	return 0;
438	}	435	}
439		436
440	static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,	437	static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
441	u8 pos, int cap)	438	u8 pos, int cap)
442	{	439	{
443	int ttl = PCI_FIND_CAP_TTL;	440	int ttl = PCI_FIND_CAP_TTL;
444		441
445	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);	442	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
446	}	443	}
447		444
448	static int __pci_bus_find_cap_start(unsigned int bus,	445	static int __pci_bus_find_cap_start(unsigned int bus,
449	unsigned int devfn, u8 hdr_type)	446	unsigned int devfn, u8 hdr_type)
450	{	447	{
451	u16 status;	448	u16 status;
452		449
453	status = PciRead16(bus, devfn, PCI_STATUS);	450	status = PciRead16(bus, devfn, PCI_STATUS);
454	if (!(status & PCI_STATUS_CAP_LIST))	451	if (!(status & PCI_STATUS_CAP_LIST))
455	return 0;	452	return 0;
456		453
457	switch (hdr_type) {	454	switch (hdr_type) {
458	case PCI_HEADER_TYPE_NORMAL:	455	case PCI_HEADER_TYPE_NORMAL:
459	case PCI_HEADER_TYPE_BRIDGE:	456	case PCI_HEADER_TYPE_BRIDGE:
460	return PCI_CAPABILITY_LIST;	457	return PCI_CAPABILITY_LIST;
461	case PCI_HEADER_TYPE_CARDBUS:	458	case PCI_HEADER_TYPE_CARDBUS:
462	return PCI_CB_CAPABILITY_LIST;	459	return PCI_CB_CAPABILITY_LIST;
463	default:	460	default:
464	return 0;	461	return 0;
465	}	462	}
466		463
467	return 0;	464	return 0;
468	}	465	}
469		466
470		467
471	int pci_find_capability(struct pci_dev *dev, int cap)	468	int pci_find_capability(struct pci_dev *dev, int cap)
472	{	469	{
473	int pos;	470	int pos;
474		471
475	pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);	472	pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
476	if (pos)	473	if (pos)
477	pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);	474	pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
478		475
479	return pos;	476	return pos;
480	}	477	}
481		478
482		479
483		480
484		481
485	int enum_pci_devices()	482	int enum_pci_devices()
486	{	483	{
487	pci_dev_t *dev;	484	pci_dev_t *dev;
488	u32 last_bus;	485	u32 last_bus;
489	u32 bus = 0 , devfn = 0;	486	u32 bus = 0 , devfn = 0;
490		487
491		488
492	last_bus = PciApi(1);	489	last_bus = PciApi(1);
493		490
494		491
495	if( unlikely(last_bus == -1))	492	if( unlikely(last_bus == -1))
496	return -1;	493	return -1;
497		494
498	for(;bus <= last_bus; bus++)	495	for(;bus <= last_bus; bus++)
499	{	496	{
500	for (devfn = 0; devfn < 0x100; devfn += 8)	497	for (devfn = 0; devfn < 0x100; devfn += 8)

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(root)/drivers/video/drm/radeon/pci.c – Rev 6104 → 6321