WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/pci.c


#define CONFIG_PCI
 
#include 
 
#include 
#include 
#include 
#include 
#include 
 
#include 
 
 
 
extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);
 
static LIST_HEAD(devices);
 
/* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
#define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */
 
#define LEGACY_IO_RESOURCE      (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 
/*
 * Translate the low bits of the PCI base
 * to the resource type
 */
static inline unsigned int pci_calc_resource_flags(unsigned int flags)
{
    if (flags & PCI_BASE_ADDRESS_SPACE_IO)
        return IORESOURCE_IO;
 
    if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
        return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 
    return IORESOURCE_MEM;
}
 
 
static u32 pci_size(u32 base, u32 maxbase, u32 mask)
{
    u32 size = mask & maxbase;      /* Find the significant bits */
 
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
{
    u64 size = mask & maxbase;      /* Find the significant bits */
 
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static inline int is_64bit_memory(u32 mask)
{
    if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
        (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
        return 1;
    return 0;
}
 
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
{
    u32  pos, reg, next;
    u32  l, sz;
    struct resource *res;
 
    for(pos=0; pos < howmany; pos = next)
    {
        u64  l64;
        u64  sz64;
        u32  raw_sz;
 
        next = pos + 1;
 
        res  = &dev->resource[pos];
 
        reg = PCI_BASE_ADDRESS_0 + (pos << 2);
        l = PciRead32(dev->busnr, dev->devfn, reg);
        PciWrite32(dev->busnr, dev->devfn, reg, ~0);
        sz = PciRead32(dev->busnr, dev->devfn, reg);
        PciWrite32(dev->busnr, dev->devfn, reg, l);
 
        if (!sz || sz == 0xffffffff)
            continue;
 
        if (l == 0xffffffff)
            l = 0;
 
        raw_sz = sz;
        if ((l & PCI_BASE_ADDRESS_SPACE) ==
                        PCI_BASE_ADDRESS_SPACE_MEMORY)
        {
            sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
            /*
             * For 64bit prefetchable memory sz could be 0, if the
             * real size is bigger than 4G, so we need to check
             * szhi for that.
             */
            if (!is_64bit_memory(l) && !sz)
                    continue;
            res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
            res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
        }
        else {
            sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
            if (!sz)
                continue;
            res->start = l & PCI_BASE_ADDRESS_IO_MASK;
            res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
        }
        res->end = res->start + (unsigned long) sz;
        res->flags |= pci_calc_resource_flags(l);
        if (is_64bit_memory(l))
        {
            u32 szhi, lhi;
 
            lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
            PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
            szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
            PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
            sz64 = ((u64)szhi << 32) | raw_sz;
            l64 = ((u64)lhi << 32) | l;
            sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
            next++;
 
#if BITS_PER_LONG == 64
            if (!sz64) {
                res->start = 0;
                res->end = 0;
                res->flags = 0;
                continue;
            }
            res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
            res->end = res->start + sz64;
#else
            if (sz64 > 0x100000000ULL) {
                printk(KERN_ERR "PCI: Unable to handle 64-bit "
                                "BAR for device %s\n", pci_name(dev));
                res->start = 0;
                res->flags = 0;
            }
            else if (lhi)
            {
                /* 64-bit wide address, treat as disabled */
                PciWrite32(dev->busnr, dev->devfn, reg,
                        l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
                PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
                res->start = 0;
                res->end = sz;
            }
#endif
        }
    }
 
    if ( rom )
    {
        dev->rom_base_reg = rom;
        res = &dev->resource[PCI_ROM_RESOURCE];
 
        l = PciRead32(dev->busnr, dev->devfn, rom);
        PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
        sz = PciRead32(dev->busnr, dev->devfn, rom);
        PciWrite32(dev->busnr, dev->devfn, rom, l);
 
        if (l == 0xffffffff)
            l = 0;
 
        if (sz && sz != 0xffffffff)
        {
            sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
 
            if (sz)
            {
                res->flags = (l & IORESOURCE_ROM_ENABLE) |
                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |
                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
                res->start = l & PCI_ROM_ADDRESS_MASK;
                res->end = res->start + (unsigned long) sz;
            }
        }
    }
}
 
static void pci_read_irq(struct pci_dev *dev)
{
    u8 irq;
 
    irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
    dev->pin = irq;
    if (irq)
        irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
    dev->irq = irq;
};
 
 
int pci_setup_device(struct pci_dev *dev)
{
    u32  class;
 
    class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
    dev->revision = class & 0xff;
    class >>= 8;                                /* upper 3 bytes */
    dev->class = class;
 
    /* "Unknown power state" */
//    dev->current_state = PCI_UNKNOWN;
 
    /* Early fixups, before probing the BARs */
 //   pci_fixup_device(pci_fixup_early, dev);
    class = dev->class >> 8;
 
    switch (dev->hdr_type)
    {
        case PCI_HEADER_TYPE_NORMAL:                /* standard header */
            if (class == PCI_CLASS_BRIDGE_PCI)
                goto bad;
            pci_read_irq(dev);
            pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
            dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
            dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
 
            /*
             *      Do the ugly legacy mode stuff here rather than broken chip
             *      quirk code. Legacy mode ATA controllers have fixed
             *      addresses. These are not always echoed in BAR0-3, and
             *      BAR0-3 in a few cases contain junk!
             */
            if (class == PCI_CLASS_STORAGE_IDE)
            {
                u8 progif;
 
                progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
                if ((progif & 1) == 0)
                {
                    dev->resource[0].start = 0x1F0;
                    dev->resource[0].end = 0x1F7;
                    dev->resource[0].flags = LEGACY_IO_RESOURCE;
                    dev->resource[1].start = 0x3F6;
                    dev->resource[1].end = 0x3F6;
                    dev->resource[1].flags = LEGACY_IO_RESOURCE;
                }
                if ((progif & 4) == 0)
                {
                    dev->resource[2].start = 0x170;
                    dev->resource[2].end = 0x177;
                    dev->resource[2].flags = LEGACY_IO_RESOURCE;
                    dev->resource[3].start = 0x376;
                    dev->resource[3].end = 0x376;
                    dev->resource[3].flags = LEGACY_IO_RESOURCE;
                };
            }
            break;
 
        case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
                if (class != PCI_CLASS_BRIDGE_PCI)
                        goto bad;
                /* The PCI-to-PCI bridge spec requires that subtractive
                   decoding (i.e. transparent) bridge must have programming
                   interface code of 0x01. */
                pci_read_irq(dev);
                dev->transparent = ((dev->class & 0xff) == 1);
                pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
                break;
 
        case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
                if (class != PCI_CLASS_BRIDGE_CARDBUS)
                        goto bad;
                pci_read_irq(dev);
                pci_read_bases(dev, 1, 0);
                dev->subsystem_vendor = PciRead16(dev->busnr,
                                                  dev->devfn,
                                                  PCI_CB_SUBSYSTEM_VENDOR_ID);
 
                dev->subsystem_device = PciRead16(dev->busnr,
                                                  dev->devfn,
                                                  PCI_CB_SUBSYSTEM_ID);
                break;
 
        default:                                    /* unknown header */
                printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
                        pci_name(dev), dev->hdr_type);
                return -1;
 
        bad:
                printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
                       pci_name(dev), class, dev->hdr_type);
                dev->class = PCI_CLASS_NOT_DEFINED;
    }
 
    /* We found a fine healthy device, go go go... */
 
    return 0;
};
 
static pci_dev_t* pci_scan_device(u32 busnr, int devfn)
{
    pci_dev_t  *dev;
 
    u32   id;
    u8    hdr;
 
    int     timeout = 10;
 
    id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
 
    /* some broken boards return 0 or ~0 if a slot is empty: */
    if (id == 0xffffffff || id == 0x00000000 ||
        id == 0x0000ffff || id == 0xffff0000)
        return NULL;
 
    while (id == 0xffff0001)
    {
 
        delay(timeout/10);
        timeout *= 2;
 
        id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
 
        /* Card hasn't responded in 60 seconds?  Must be stuck. */
        if (timeout > 60 * 100)
        {
            printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
                   "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
            return NULL;
        }
    };
 
    if( pci_scan_filter(id, busnr, devfn) == 0)
        return NULL;
 
    hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
 
    dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
    if(unlikely(dev == NULL))
        return NULL;
 
    INIT_LIST_HEAD(&dev->link);
 
 
    dev->pci_dev.busnr    = busnr;
    dev->pci_dev.devfn    = devfn;
    dev->pci_dev.hdr_type = hdr & 0x7f;
    dev->pci_dev.multifunction    = !!(hdr & 0x80);
    dev->pci_dev.vendor   = id & 0xffff;
    dev->pci_dev.device   = (id >> 16) & 0xffff;
 
    pci_setup_device(&dev->pci_dev);
 
    return dev;
 
};
 
 
 
 
int _pci_scan_slot(u32 bus, int devfn)
{
    int  func, nr = 0;
 
    for (func = 0; func < 8; func++, devfn++)
    {
        pci_dev_t  *dev;
 
        dev = pci_scan_device(bus, devfn);
        if( dev )
        {
            list_add(&dev->link, &devices);
 
            nr++;
 
            /*
             * If this is a single function device,
             * don't scan past the first function.
             */
            if (!dev->pci_dev.multifunction)
            {
                if (func > 0) {
                    dev->pci_dev.multifunction = 1;
                }
                else {
                    break;
                }
             }
        }
        else {
            if (func == 0)
                break;
        }
    };
 
    return nr;
};
 
#define PCI_FIND_CAP_TTL    48
 
static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
                   u8 pos, int cap, int *ttl)
{
    u8 id;
 
    while ((*ttl)--) {
        pos = PciRead8(bus, devfn, pos);
        if (pos < 0x40)
            break;
        pos &= ~3;
        id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
        if (id == 0xff)
            break;
        if (id == cap)
            return pos;
        pos += PCI_CAP_LIST_NEXT;
    }
    return 0;
}
 
static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
                   u8 pos, int cap)
{
    int ttl = PCI_FIND_CAP_TTL;
 
    return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
}
 
static int __pci_bus_find_cap_start(unsigned int bus,
                    unsigned int devfn, u8 hdr_type)
{
    u16 status;
 
    status = PciRead16(bus, devfn, PCI_STATUS);
    if (!(status & PCI_STATUS_CAP_LIST))
        return 0;
 
    switch (hdr_type) {
    case PCI_HEADER_TYPE_NORMAL:
    case PCI_HEADER_TYPE_BRIDGE:
        return PCI_CAPABILITY_LIST;
    case PCI_HEADER_TYPE_CARDBUS:
        return PCI_CB_CAPABILITY_LIST;
    default:
        return 0;
    }
 
    return 0;
}
 
 
int pci_find_capability(struct pci_dev *dev, int cap)
{
    int pos;
 
    pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
    if (pos)
        pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
 
    return pos;
}
 
 
 
 
int enum_pci_devices()
{
    pci_dev_t  *dev;
    u32       last_bus;
    u32       bus = 0 , devfn = 0;
 
 
    last_bus = PciApi(1);
 
 
    if( unlikely(last_bus == -1))
        return -1;
 
    for(;bus <= last_bus; bus++)
    {
        for (devfn = 0; devfn < 0x100; devfn += 8)
            _pci_scan_slot(bus, devfn);
 
 
    }
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",
                dev->pci_dev.vendor,
                dev->pci_dev.device,
                dev->pci_dev.busnr,
                dev->pci_dev.devfn);
 
    }
    return 0;
}
 
const struct pci_device_id* find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist)
{
    pci_dev_t *dev;
    const struct pci_device_id *ent;
 
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.vendor != idlist->vendor )
            continue;
 
        for(ent = idlist; ent->vendor != 0; ent++)
        {
            if(unlikely(ent->device == dev->pci_dev.device))
            {
                pdev->pci_dev = dev->pci_dev;
                return  ent;
            }
        };
    }
 
    return NULL;
};
 
struct pci_dev *
pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
{
    pci_dev_t *dev;
 
    dev = (pci_dev_t*)devices.next;
 
    if(from != NULL)
    {
        for(; &dev->link != &devices;
            dev = (pci_dev_t*)dev->link.next)
        {
            if( &dev->pci_dev == from)
            {
                dev = (pci_dev_t*)dev->link.next;
                break;
            };
        }
    };
 
    for(; &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.vendor != vendor )
                continue;
 
        if(dev->pci_dev.device == device)
        {
            return &dev->pci_dev;
        }
    }
    return NULL;
};
 
 
struct pci_dev * _pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
{
    pci_dev_t *dev;
 
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn)
            return &dev->pci_dev;
    }
    return NULL;
}
 
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
{
    pci_dev_t *dev;
 
    dev = (pci_dev_t*)devices.next;
 
    if(from != NULL)
    {
        for(; &dev->link != &devices;
            dev = (pci_dev_t*)dev->link.next)
        {
            if( &dev->pci_dev == from)
            {
                dev = (pci_dev_t*)dev->link.next;
                break;
            };
        }
    };
 
    for(; &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.class == class)
        {
            return &dev->pci_dev;
        }
    }
 
   return NULL;
}
 
 
#define PIO_OFFSET      0x10000UL
#define PIO_MASK        0x0ffffUL
#define PIO_RESERVED    0x40000UL
 
#define IO_COND(addr, is_pio, is_mmio) do {            \
    unsigned long port = (unsigned long __force)addr;  \
    if (port >= PIO_RESERVED) {                        \
        is_mmio;                                       \
    } else if (port > PIO_OFFSET) {                    \
        port &= PIO_MASK;                              \
        is_pio;                                        \
    };                                                 \
} while (0)
 
/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
    if (port > PIO_MASK)
        return NULL;
    return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
}
 
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
    resource_size_t start = pci_resource_start(dev, bar);
    resource_size_t len = pci_resource_len(dev, bar);
    unsigned long flags = pci_resource_flags(dev, bar);
 
    if (!len || !start)
        return NULL;
    if (maxlen && len > maxlen)
        len = maxlen;
    if (flags & IORESOURCE_IO)
        return ioport_map(start, len);
    if (flags & IORESOURCE_MEM) {
        return ioremap(start, len);
    }
    /* What? */
    return NULL;
}
 
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
    IO_COND(addr, /* nothing */, iounmap(addr));
}
 
 
static inline void
_pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
                         struct resource *res)
{
    region->start = res->start;
    region->end = res->end;
}
 
 
int pci_enable_rom(struct pci_dev *pdev)
{
    struct resource *res = pdev->resource + PCI_ROM_RESOURCE;
    struct pci_bus_region region;
    u32 rom_addr;
 
    if (!res->flags)
            return -1;
 
    _pcibios_resource_to_bus(pdev, ®ion, res);
    pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
    rom_addr &= ~PCI_ROM_ADDRESS_MASK;
    rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;
    pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
    return 0;
}
 
void pci_disable_rom(struct pci_dev *pdev)
{
    u32 rom_addr;
    pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
    rom_addr &= ~PCI_ROM_ADDRESS_ENABLE;
    pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
}
 
/**
 * pci_get_rom_size - obtain the actual size of the ROM image
 * @pdev: target PCI device
 * @rom: kernel virtual pointer to image of ROM
 * @size: size of PCI window
 *  return: size of actual ROM image
 *
 * Determine the actual length of the ROM image.
 * The PCI window size could be much larger than the
 * actual image size.
 */
size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
{
        void __iomem *image;
        int last_image;
 
        image = rom;
        do {
                void __iomem *pds;
                /* Standard PCI ROMs start out with these bytes 55 AA */
                if (readb(image) != 0x55) {
                        dev_err(&pdev->dev, "Invalid ROM contents\n");
                        break;
            }
                if (readb(image + 1) != 0xAA)
                        break;
                /* get the PCI data structure and check its signature */
                pds = image + readw(image + 24);
                if (readb(pds) != 'P')
                        break;
                if (readb(pds + 1) != 'C')
                        break;
                if (readb(pds + 2) != 'I')
                        break;
                if (readb(pds + 3) != 'R')
                        break;
                last_image = readb(pds + 21) & 0x80;
                /* this length is reliable */
                image += readw(pds + 16) * 512;
        } while (!last_image);
 
        /* never return a size larger than the PCI resource window */
        /* there are known ROMs that get the size wrong */
        return min((size_t)(image - rom), size);
}
 
 
/**
 * pci_map_rom - map a PCI ROM to kernel space
 * @pdev: pointer to pci device struct
 * @size: pointer to receive size of pci window over ROM
 *
 * Return: kernel virtual pointer to image of ROM
 *
 * Map a PCI ROM into kernel space. If ROM is boot video ROM,
 * the shadow BIOS copy will be returned instead of the
 * actual ROM.
 */
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
{
    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
    loff_t start;
    void __iomem *rom;
 
    /*
     * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
     * memory map if the VGA enable bit of the Bridge Control register is
     * set for embedded VGA.
     */
    if (res->flags & IORESOURCE_ROM_SHADOW) {
        /* primary video rom always starts here */
        start = (loff_t)0xC0000;
        *size = 0x20000; /* cover C000:0 through E000:0 */
    } else {
                if (res->flags &
                        (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
            *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
             return (void __iomem *)(unsigned long)
             pci_resource_start(pdev, PCI_ROM_RESOURCE);
        } else {
    				start = (loff_t)0xC0000;
    				*size = 0x20000; /* cover C000:0 through E000:0 */
 
        }
    }
 
    rom = ioremap(start, *size);
    if (!rom) {
            /* restore enable if ioremap fails */
            if (!(res->flags & (IORESOURCE_ROM_ENABLE |
                                IORESOURCE_ROM_SHADOW |
                                IORESOURCE_ROM_COPY)))
                    pci_disable_rom(pdev);
            return NULL;
    }
 
    /*
     * Try to find the true size of the ROM since sometimes the PCI window
     * size is much larger than the actual size of the ROM.
     * True size is important if the ROM is going to be copied.
     */
    *size = pci_get_rom_size(pdev, rom, *size);
    return rom;
}
 
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
{
    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
 
    if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY))
            return;
 
    iounmap(rom);
 
    /* Disable again before continuing, leave enabled if pci=rom */
    if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW)))
            pci_disable_rom(pdev);
}
 
static void __pci_set_master(struct pci_dev *dev, bool enable)
{
    u16 old_cmd, cmd;
 
    pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
    if (enable)
        cmd = old_cmd | PCI_COMMAND_MASTER;
    else
        cmd = old_cmd & ~PCI_COMMAND_MASTER;
    if (cmd != old_cmd) {
            dbgprintf("%s bus mastering\n",
                    enable ? "enabling" : "disabling");
        pci_write_config_word(dev, PCI_COMMAND, cmd);
        }
    dev->is_busmaster = enable;
}
 
 
/* pci_set_master - enables bus-mastering for device dev
 * @dev: the PCI device to enable
 *
 * Enables bus-mastering on the device and calls pcibios_set_master()
 * to do the needed arch specific settings.
 */
void pci_set_master(struct pci_dev *dev)
{
        __pci_set_master(dev, true);
//        pcibios_set_master(dev);
}
 
/**
 * pci_clear_master - disables bus-mastering for device dev
 * @dev: the PCI device to disable
 */
void pci_clear_master(struct pci_dev *dev)
{
        __pci_set_master(dev, false);
}
 
 
static inline int pcie_cap_version(const struct pci_dev *dev)
{
    return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS;
}
 
static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
{
    return true;
}
 
static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           type == PCI_EXP_TYPE_ENDPOINT ||
           type == PCI_EXP_TYPE_LEG_END;
}
 
static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           (type == PCI_EXP_TYPE_DOWNSTREAM &&
        dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);
}
 
static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           type == PCI_EXP_TYPE_RC_EC;
}
 
static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
{
    if (!pci_is_pcie(dev))
        return false;
 
    switch (pos) {
    case PCI_EXP_FLAGS_TYPE:
        return true;
    case PCI_EXP_DEVCAP:
    case PCI_EXP_DEVCTL:
    case PCI_EXP_DEVSTA:
        return pcie_cap_has_devctl(dev);
    case PCI_EXP_LNKCAP:
    case PCI_EXP_LNKCTL:
    case PCI_EXP_LNKSTA:
        return pcie_cap_has_lnkctl(dev);
    case PCI_EXP_SLTCAP:
    case PCI_EXP_SLTCTL:
    case PCI_EXP_SLTSTA:
        return pcie_cap_has_sltctl(dev);
    case PCI_EXP_RTCTL:
    case PCI_EXP_RTCAP:
    case PCI_EXP_RTSTA:
        return pcie_cap_has_rtctl(dev);
    case PCI_EXP_DEVCAP2:
    case PCI_EXP_DEVCTL2:
    case PCI_EXP_LNKCAP2:
    case PCI_EXP_LNKCTL2:
    case PCI_EXP_LNKSTA2:
        return pcie_cap_version(dev) > 1;
    default:
        return false;
    }
}
 
/*
 * Note that these accessor functions are only for the "PCI Express
 * Capability" (see PCIe spec r3.0, sec 7.8).  They do not apply to the
 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
 */
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
{
    int ret;
 
    *val = 0;
    if (pos & 1)
        return -EINVAL;
 
    if (pcie_capability_reg_implemented(dev, pos)) {
        ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
        /*
         * Reset *val to 0 if pci_read_config_word() fails, it may
         * have been written as 0xFFFF if hardware error happens
         * during pci_read_config_word().
         */
        if (ret)
            *val = 0;
        return ret;
    }
 
    /*
     * For Functions that do not implement the Slot Capabilities,
     * Slot Status, and Slot Control registers, these spaces must
     * be hardwired to 0b, with the exception of the Presence Detect
     * State bit in the Slot Status register of Downstream Ports,
     * which must be hardwired to 1b.  (PCIe Base Spec 3.0, sec 7.8)
     */
    if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
         pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
        *val = PCI_EXP_SLTSTA_PDS;
    }
 
    return 0;
}
EXPORT_SYMBOL(pcie_capability_read_word);
 
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
{
    int ret;
 
    *val = 0;
    if (pos & 3)
        return -EINVAL;
 
    if (pcie_capability_reg_implemented(dev, pos)) {
        ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
        /*
         * Reset *val to 0 if pci_read_config_dword() fails, it may
         * have been written as 0xFFFFFFFF if hardware error happens
         * during pci_read_config_dword().
         */
        if (ret)
            *val = 0;
        return ret;
    }
 
    if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
         pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
        *val = PCI_EXP_SLTSTA_PDS;
    }
 
    return 0;
}
EXPORT_SYMBOL(pcie_capability_read_dword);
 
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
{
    if (pos & 1)
        return -EINVAL;
 
    if (!pcie_capability_reg_implemented(dev, pos))
        return 0;
 
    return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_word);
 
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
{
    if (pos & 3)
        return -EINVAL;
 
    if (!pcie_capability_reg_implemented(dev, pos))
        return 0;
 
    return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_dword);
 
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
                                       u16 clear, u16 set)
{
        int ret;
        u16 val;
 
        ret = pcie_capability_read_word(dev, pos, &val);
        if (!ret) {
                val &= ~clear;
                val |= set;
                ret = pcie_capability_write_word(dev, pos, val);
        }
 
        return ret;
}
 
 
 
int pcie_get_readrq(struct pci_dev *dev)
{
        u16 ctl;
 
        pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
 
        return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
}
EXPORT_SYMBOL(pcie_get_readrq);
 
/**
 * pcie_set_readrq - set PCI Express maximum memory read request
 * @dev: PCI device to query
 * @rq: maximum memory read count in bytes
 *    valid values are 128, 256, 512, 1024, 2048, 4096
 *
 * If possible sets maximum memory read request in bytes
 */
int pcie_set_readrq(struct pci_dev *dev, int rq)
{
        u16 v;
 
        if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
                return -EINVAL;
 
        v = (ffs(rq) - 8) << 12;
 
        return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
                                                  PCI_EXP_DEVCTL_READRQ, v);
}

Rev 5271	Rev 6104
-		1	#define CONFIG_PCI
-		2
-		3	#include
1	#include	4
2	#include	5	#include
3	#include	6	#include
4	#include	7	#include
5	#include	8	#include
-		9	#include
-		10
6	#include	11	#include
7		-
-		12
8	extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);	13
9		14	extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);
10	static LIST_HEAD(devices);	15
11		16	static LIST_HEAD(devices);
12	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */	17
13	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */	18	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
14		19	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
15	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)	20
16		21	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)
17	/*	22
18	* Translate the low bits of the PCI base	23	/*
19	* to the resource type	24	* Translate the low bits of the PCI base
20	*/	25	* to the resource type
21	static inline unsigned int pci_calc_resource_flags(unsigned int flags)	26	*/
22	{	27	static inline unsigned int pci_calc_resource_flags(unsigned int flags)
23	if (flags & PCI_BASE_ADDRESS_SPACE_IO)	28	{
24	return IORESOURCE_IO;	29	if (flags & PCI_BASE_ADDRESS_SPACE_IO)
25		30	return IORESOURCE_IO;
26	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)	31
27	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;	32	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
28		33	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;
29	return IORESOURCE_MEM;	34
30	}	35	return IORESOURCE_MEM;
31		36	}
32		37
33	static u32 pci_size(u32 base, u32 maxbase, u32 mask)	38
34	{	39	static u32 pci_size(u32 base, u32 maxbase, u32 mask)
35	u32 size = mask & maxbase; /* Find the significant bits */	40	{
36		41	u32 size = mask & maxbase; /* Find the significant bits */
37	if (!size)	42
38	return 0;	43	if (!size)
39		44	return 0;
40	/* Get the lowest of them to find the decode size, and	45
41	from that the extent. */	46	/* Get the lowest of them to find the decode size, and
42	size = (size & ~(size-1)) - 1;	47	from that the extent. */
43		48	size = (size & ~(size-1)) - 1;
44	/* base == maxbase can be valid only if the BAR has	49
45	already been programmed with all 1s. */	50	/* base == maxbase can be valid only if the BAR has
46	if (base == maxbase && ((base \| size) & mask) != mask)	51	already been programmed with all 1s. */
47	return 0;	52	if (base == maxbase && ((base \| size) & mask) != mask)
48		53	return 0;
49	return size;	54
50	}	55	return size;
51		56	}
52	static u64 pci_size64(u64 base, u64 maxbase, u64 mask)	57
53	{	58	static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
54	u64 size = mask & maxbase; /* Find the significant bits */	59	{
55		60	u64 size = mask & maxbase; /* Find the significant bits */
56	if (!size)	61
57	return 0;	62	if (!size)
58		63	return 0;
59	/* Get the lowest of them to find the decode size, and	64
60	from that the extent. */	65	/* Get the lowest of them to find the decode size, and
61	size = (size & ~(size-1)) - 1;	66	from that the extent. */
62		67	size = (size & ~(size-1)) - 1;
63	/* base == maxbase can be valid only if the BAR has	68
64	already been programmed with all 1s. */	69	/* base == maxbase can be valid only if the BAR has
65	if (base == maxbase && ((base \| size) & mask) != mask)	70	already been programmed with all 1s. */
66	return 0;	71	if (base == maxbase && ((base \| size) & mask) != mask)
67		72	return 0;
68	return size;	73
69	}	74	return size;
70		75	}
71	static inline int is_64bit_memory(u32 mask)	76
72	{	77	static inline int is_64bit_memory(u32 mask)
73	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==	78	{
74	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))	79	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
75	return 1;	80	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))
76	return 0;	81	return 1;
77	}	82	return 0;
78		83	}
79	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)	84
80	{	85	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
81	u32 pos, reg, next;	86	{
82	u32 l, sz;	87	u32 pos, reg, next;
83	struct resource *res;	88	u32 l, sz;
84		89	struct resource *res;
85	for(pos=0; pos < howmany; pos = next)	90
86	{	91	for(pos=0; pos < howmany; pos = next)
87	u64 l64;	92	{
88	u64 sz64;	93	u64 l64;
89	u32 raw_sz;	94	u64 sz64;
90		95	u32 raw_sz;
91	next = pos + 1;	96
92		97	next = pos + 1;
93	res = &dev->resource[pos];	98
94		99	res = &dev->resource[pos];
95	reg = PCI_BASE_ADDRESS_0 + (pos << 2);	100
96	l = PciRead32(dev->busnr, dev->devfn, reg);	101	reg = PCI_BASE_ADDRESS_0 + (pos << 2);
97	PciWrite32(dev->busnr, dev->devfn, reg, ~0);	102	l = PciRead32(dev->busnr, dev->devfn, reg);
98	sz = PciRead32(dev->busnr, dev->devfn, reg);	103	PciWrite32(dev->busnr, dev->devfn, reg, ~0);
99	PciWrite32(dev->busnr, dev->devfn, reg, l);	104	sz = PciRead32(dev->busnr, dev->devfn, reg);
100		105	PciWrite32(dev->busnr, dev->devfn, reg, l);
101	if (!sz \|\| sz == 0xffffffff)	106
102	continue;	107	if (!sz \|\| sz == 0xffffffff)
103		108	continue;
104	if (l == 0xffffffff)	109
105	l = 0;	110	if (l == 0xffffffff)
106		111	l = 0;
107	raw_sz = sz;	112
108	if ((l & PCI_BASE_ADDRESS_SPACE) ==	113	raw_sz = sz;
109	PCI_BASE_ADDRESS_SPACE_MEMORY)	114	if ((l & PCI_BASE_ADDRESS_SPACE) ==
110	{	115	PCI_BASE_ADDRESS_SPACE_MEMORY)
111	sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);	116	{
112	/*	117	sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
113	* For 64bit prefetchable memory sz could be 0, if the	118	/*
114	* real size is bigger than 4G, so we need to check	119	* For 64bit prefetchable memory sz could be 0, if the
115	* szhi for that.	120	* real size is bigger than 4G, so we need to check
116	*/	121	* szhi for that.
117	if (!is_64bit_memory(l) && !sz)	122	*/
118	continue;	123	if (!is_64bit_memory(l) && !sz)
119	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;	124	continue;
120	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;	125	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
121	}	126	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;
122	else {	127	}
123	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);	128	else {
124	if (!sz)	129	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
125	continue;	130	if (!sz)
126	res->start = l & PCI_BASE_ADDRESS_IO_MASK;	131	continue;
127	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;	132	res->start = l & PCI_BASE_ADDRESS_IO_MASK;
128	}	133	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;
129	res->end = res->start + (unsigned long) sz;	134	}
130	res->flags \|= pci_calc_resource_flags(l);	135	res->end = res->start + (unsigned long) sz;
131	if (is_64bit_memory(l))	136	res->flags \|= pci_calc_resource_flags(l);
132	{	137	if (is_64bit_memory(l))
133	u32 szhi, lhi;	138	{
134		139	u32 szhi, lhi;
135	lhi = PciRead32(dev->busnr, dev->devfn, reg+4);	140
136	PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);	141	lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
137	szhi = PciRead32(dev->busnr, dev->devfn, reg+4);	142	PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
138	PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);	143	szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
139	sz64 = ((u64)szhi << 32) \| raw_sz;	144	PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
140	l64 = ((u64)lhi << 32) \| l;	145	sz64 = ((u64)szhi << 32) \| raw_sz;
141	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);	146	l64 = ((u64)lhi << 32) \| l;
142	next++;	147	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
143		148	next++;
144	#if BITS_PER_LONG == 64	149
145	if (!sz64) {	150	#if BITS_PER_LONG == 64
146	res->start = 0;	151	if (!sz64) {
147	res->end = 0;	152	res->start = 0;
148	res->flags = 0;	153	res->end = 0;
149	continue;	154	res->flags = 0;
150	}	155	continue;
151	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;	156	}
152	res->end = res->start + sz64;	157	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
153	#else	158	res->end = res->start + sz64;
154	if (sz64 > 0x100000000ULL) {	159	#else
155	printk(KERN_ERR "PCI: Unable to handle 64-bit "	160	if (sz64 > 0x100000000ULL) {
156	"BAR for device %s\n", pci_name(dev));	161	printk(KERN_ERR "PCI: Unable to handle 64-bit "
157	res->start = 0;	162	"BAR for device %s\n", pci_name(dev));
158	res->flags = 0;	163	res->start = 0;
159	}	164	res->flags = 0;
160	else if (lhi)	165	}
161	{	166	else if (lhi)
162	/* 64-bit wide address, treat as disabled */	167	{
163	PciWrite32(dev->busnr, dev->devfn, reg,	168	/* 64-bit wide address, treat as disabled */
164	l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);	169	PciWrite32(dev->busnr, dev->devfn, reg,
165	PciWrite32(dev->busnr, dev->devfn, reg+4, 0);	170	l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
166	res->start = 0;	171	PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
167	res->end = sz;	172	res->start = 0;
168	}	173	res->end = sz;
169	#endif	174	}
170	}	175	#endif
171	}	176	}
172		177	}
173	if ( rom )	178
174	{	179	if ( rom )
175	dev->rom_base_reg = rom;	180	{
176	res = &dev->resource[PCI_ROM_RESOURCE];	181	dev->rom_base_reg = rom;
177		182	res = &dev->resource[PCI_ROM_RESOURCE];
178	l = PciRead32(dev->busnr, dev->devfn, rom);	183
179	PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);	184	l = PciRead32(dev->busnr, dev->devfn, rom);
180	sz = PciRead32(dev->busnr, dev->devfn, rom);	185	PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
181	PciWrite32(dev->busnr, dev->devfn, rom, l);	186	sz = PciRead32(dev->busnr, dev->devfn, rom);
182		187	PciWrite32(dev->busnr, dev->devfn, rom, l);
183	if (l == 0xffffffff)	188
184	l = 0;	189	if (l == 0xffffffff)
185		190	l = 0;
186	if (sz && sz != 0xffffffff)	191
187	{	192	if (sz && sz != 0xffffffff)
188	sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);	193	{
189		194	sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
190	if (sz)	195
191	{	196	if (sz)
192	res->flags = (l & IORESOURCE_ROM_ENABLE) \|	197	{
193	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|	198	res->flags = (l & IORESOURCE_ROM_ENABLE) \|
194	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;	199	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|
195	res->start = l & PCI_ROM_ADDRESS_MASK;	200	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;
196	res->end = res->start + (unsigned long) sz;	201	res->start = l & PCI_ROM_ADDRESS_MASK;
197	}	202	res->end = res->start + (unsigned long) sz;
198	}	203	}
199	}	204	}
200	}	205	}
201		206	}
202	static void pci_read_irq(struct pci_dev *dev)	207
203	{	208	static void pci_read_irq(struct pci_dev *dev)
204	u8 irq;	209	{
205		210	u8 irq;
206	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);	211
207	dev->pin = irq;	212	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
208	if (irq)	213	dev->pin = irq;
209	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);	214	if (irq)
210	dev->irq = irq;	215	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
211	};	216	dev->irq = irq;
212		217	};
213		218
214	int pci_setup_device(struct pci_dev *dev)	219
215	{	220	int pci_setup_device(struct pci_dev *dev)
216	u32 class;	221	{
217		222	u32 class;
218	class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);	223
219	dev->revision = class & 0xff;	224	class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
220	class >>= 8; /* upper 3 bytes */	225	dev->revision = class & 0xff;
221	dev->class = class;	226	class >>= 8; /* upper 3 bytes */
222		227	dev->class = class;
223	/* "Unknown power state" */	228
224	// dev->current_state = PCI_UNKNOWN;	229	/* "Unknown power state" */
225		230	// dev->current_state = PCI_UNKNOWN;
226	/* Early fixups, before probing the BARs */	231
227	// pci_fixup_device(pci_fixup_early, dev);	232	/* Early fixups, before probing the BARs */
228	class = dev->class >> 8;	233	// pci_fixup_device(pci_fixup_early, dev);
229		234	class = dev->class >> 8;
230	switch (dev->hdr_type)	235
231	{	236	switch (dev->hdr_type)
232	case PCI_HEADER_TYPE_NORMAL: /* standard header */	237	{
233	if (class == PCI_CLASS_BRIDGE_PCI)	238	case PCI_HEADER_TYPE_NORMAL: /* standard header */
234	goto bad;	239	if (class == PCI_CLASS_BRIDGE_PCI)
235	pci_read_irq(dev);	240	goto bad;
236	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);	241	pci_read_irq(dev);
237	dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);	242	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
238	dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);	243	dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
239		244	dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
240	/*	245
241	* Do the ugly legacy mode stuff here rather than broken chip	246	/*
242	* quirk code. Legacy mode ATA controllers have fixed	247	* Do the ugly legacy mode stuff here rather than broken chip
243	* addresses. These are not always echoed in BAR0-3, and	248	* quirk code. Legacy mode ATA controllers have fixed
244	* BAR0-3 in a few cases contain junk!	249	* addresses. These are not always echoed in BAR0-3, and
245	*/	250	* BAR0-3 in a few cases contain junk!
246	if (class == PCI_CLASS_STORAGE_IDE)	251	*/
247	{	252	if (class == PCI_CLASS_STORAGE_IDE)
248	u8 progif;	253	{
249		254	u8 progif;
250	progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);	255
251	if ((progif & 1) == 0)	256	progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
252	{	257	if ((progif & 1) == 0)
253	dev->resource[0].start = 0x1F0;	258	{
254	dev->resource[0].end = 0x1F7;	259	dev->resource[0].start = 0x1F0;
255	dev->resource[0].flags = LEGACY_IO_RESOURCE;	260	dev->resource[0].end = 0x1F7;
256	dev->resource[1].start = 0x3F6;	261	dev->resource[0].flags = LEGACY_IO_RESOURCE;
257	dev->resource[1].end = 0x3F6;	262	dev->resource[1].start = 0x3F6;
258	dev->resource[1].flags = LEGACY_IO_RESOURCE;	263	dev->resource[1].end = 0x3F6;
259	}	264	dev->resource[1].flags = LEGACY_IO_RESOURCE;
260	if ((progif & 4) == 0)	265	}
261	{	266	if ((progif & 4) == 0)
262	dev->resource[2].start = 0x170;	267	{
263	dev->resource[2].end = 0x177;	268	dev->resource[2].start = 0x170;
264	dev->resource[2].flags = LEGACY_IO_RESOURCE;	269	dev->resource[2].end = 0x177;
265	dev->resource[3].start = 0x376;	270	dev->resource[2].flags = LEGACY_IO_RESOURCE;
266	dev->resource[3].end = 0x376;	271	dev->resource[3].start = 0x376;
267	dev->resource[3].flags = LEGACY_IO_RESOURCE;	272	dev->resource[3].end = 0x376;
268	};	273	dev->resource[3].flags = LEGACY_IO_RESOURCE;
269	}	274	};
270	break;	275	}
271		276	break;
272	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */	277
273	if (class != PCI_CLASS_BRIDGE_PCI)	278	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
274	goto bad;	279	if (class != PCI_CLASS_BRIDGE_PCI)
275	/* The PCI-to-PCI bridge spec requires that subtractive	280	goto bad;
276	decoding (i.e. transparent) bridge must have programming	281	/* The PCI-to-PCI bridge spec requires that subtractive
277	interface code of 0x01. */	282	decoding (i.e. transparent) bridge must have programming
278	pci_read_irq(dev);	283	interface code of 0x01. */
279	dev->transparent = ((dev->class & 0xff) == 1);	284	pci_read_irq(dev);
280	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);	285	dev->transparent = ((dev->class & 0xff) == 1);
281	break;	286	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
282		287	break;
283	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */	288
284	if (class != PCI_CLASS_BRIDGE_CARDBUS)	289	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
285	goto bad;	290	if (class != PCI_CLASS_BRIDGE_CARDBUS)
286	pci_read_irq(dev);	291	goto bad;
287	pci_read_bases(dev, 1, 0);	292	pci_read_irq(dev);
288	dev->subsystem_vendor = PciRead16(dev->busnr,	293	pci_read_bases(dev, 1, 0);
289	dev->devfn,	294	dev->subsystem_vendor = PciRead16(dev->busnr,
290	PCI_CB_SUBSYSTEM_VENDOR_ID);	295	dev->devfn,
291		296	PCI_CB_SUBSYSTEM_VENDOR_ID);
292	dev->subsystem_device = PciRead16(dev->busnr,	297
293	dev->devfn,	298	dev->subsystem_device = PciRead16(dev->busnr,
294	PCI_CB_SUBSYSTEM_ID);	299	dev->devfn,
295	break;	300	PCI_CB_SUBSYSTEM_ID);
296		301	break;
297	default: /* unknown header */	302
298	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",	303	default: /* unknown header */
299	pci_name(dev), dev->hdr_type);	304	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
300	return -1;	305	pci_name(dev), dev->hdr_type);
301		306	return -1;
302	bad:	307
303	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",	308	bad:
304	pci_name(dev), class, dev->hdr_type);	309	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
305	dev->class = PCI_CLASS_NOT_DEFINED;	310	pci_name(dev), class, dev->hdr_type);
306	}	311	dev->class = PCI_CLASS_NOT_DEFINED;
307		312	}
308	/* We found a fine healthy device, go go go... */	313
309		314	/* We found a fine healthy device, go go go... */
310	return 0;	315
311	};	316	return 0;
312		317	};
313	static pci_dev_t* pci_scan_device(u32 busnr, int devfn)	318
314	{	319	static pci_dev_t* pci_scan_device(u32 busnr, int devfn)
315	pci_dev_t *dev;	320	{
316		321	pci_dev_t *dev;
317	u32 id;	322
318	u8 hdr;	323	u32 id;
319		324	u8 hdr;
320	int timeout = 10;	325
321		326	int timeout = 10;
322	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);	327
323		328	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
324	/* some broken boards return 0 or ~0 if a slot is empty: */	329
325	if (id == 0xffffffff \|\| id == 0x00000000 \|\|	330	/* some broken boards return 0 or ~0 if a slot is empty: */
326	id == 0x0000ffff \|\| id == 0xffff0000)	331	if (id == 0xffffffff \|\| id == 0x00000000 \|\|
327	return NULL;	332	id == 0x0000ffff \|\| id == 0xffff0000)
328		333	return NULL;
329	while (id == 0xffff0001)	334
330	{	335	while (id == 0xffff0001)
331		336	{
332	delay(timeout/10);	337
333	timeout *= 2;	338	delay(timeout/10);
334		339	timeout *= 2;
335	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);	340
336		341	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
337	/* Card hasn't responded in 60 seconds? Must be stuck. */	342
338	if (timeout > 60 * 100)	343	/* Card hasn't responded in 60 seconds? Must be stuck. */
339	{	344	if (timeout > 60 * 100)
340	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "	345	{
341	"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));	346	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
342	return NULL;	347	"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
343	}	348	return NULL;
344	};	349	}
345		350	};
346	if( pci_scan_filter(id, busnr, devfn) == 0)	351
347	return NULL;	352	if( pci_scan_filter(id, busnr, devfn) == 0)
348		353	return NULL;
349	hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);	354
350		355	hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
351	dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);	356
352	if(unlikely(dev == NULL))	357	dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
353	return NULL;	358	if(unlikely(dev == NULL))
354		359	return NULL;
355	INIT_LIST_HEAD(&dev->link);	360
356		361	INIT_LIST_HEAD(&dev->link);
357		362
358	dev->pci_dev.busnr = busnr;	363
359	dev->pci_dev.devfn = devfn;	364	dev->pci_dev.busnr = busnr;
360	dev->pci_dev.hdr_type = hdr & 0x7f;	365	dev->pci_dev.devfn = devfn;
361	dev->pci_dev.multifunction = !!(hdr & 0x80);	366	dev->pci_dev.hdr_type = hdr & 0x7f;
362	dev->pci_dev.vendor = id & 0xffff;	367	dev->pci_dev.multifunction = !!(hdr & 0x80);
363	dev->pci_dev.device = (id >> 16) & 0xffff;	368	dev->pci_dev.vendor = id & 0xffff;
364		369	dev->pci_dev.device = (id >> 16) & 0xffff;
365	pci_setup_device(&dev->pci_dev);	370
366		371	pci_setup_device(&dev->pci_dev);
367	return dev;	372
368		373	return dev;
369	};	374
370		375	};
371		376
372		377
373		378
374	int pci_scan_slot(u32 bus, int devfn)	379
375	{	380	int _pci_scan_slot(u32 bus, int devfn)
376	int func, nr = 0;	381	{
377		382	int func, nr = 0;
378	for (func = 0; func < 8; func++, devfn++)	383
379	{	384	for (func = 0; func < 8; func++, devfn++)
380	pci_dev_t *dev;	385	{
381		386	pci_dev_t *dev;
382	dev = pci_scan_device(bus, devfn);	387
383	if( dev )	388	dev = pci_scan_device(bus, devfn);
384	{	389	if( dev )
385	list_add(&dev->link, &devices);	390	{
386		391	list_add(&dev->link, &devices);
387	nr++;	392
388		393	nr++;
389	/*	394
390	* If this is a single function device,	395	/*
391	* don't scan past the first function.	396	* If this is a single function device,
392	*/	397	* don't scan past the first function.
393	if (!dev->pci_dev.multifunction)	398	*/
394	{	399	if (!dev->pci_dev.multifunction)
395	if (func > 0) {	400	{
396	dev->pci_dev.multifunction = 1;	401	if (func > 0) {
397	}	402	dev->pci_dev.multifunction = 1;
398	else {	403	}
399	break;	404	else {
400	}	405	break;
401	}	406	}
402	}	407	}
403	else {	408	}
404	if (func == 0)	409	else {
405	break;	410	if (func == 0)
406	}	411	break;
407	};	412	}
408		413	};
409	return nr;	414
410	};	415	return nr;
411		416	};
412	#define PCI_FIND_CAP_TTL 48	417
413		418	#define PCI_FIND_CAP_TTL 48
414	static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,	419
415	u8 pos, int cap, int *ttl)	420	static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
416	{	421	u8 pos, int cap, int *ttl)
417	u8 id;	422	{
418		423	u8 id;
419	while ((*ttl)--) {	424
420	pos = PciRead8(bus, devfn, pos);	425	while ((*ttl)--) {
421	if (pos < 0x40)	426	pos = PciRead8(bus, devfn, pos);
422	break;	427	if (pos < 0x40)
423	pos &= ~3;	428	break;
424	id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);	429	pos &= ~3;
425	if (id == 0xff)	430	id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
426	break;	431	if (id == 0xff)
427	if (id == cap)	432	break;
428	return pos;	433	if (id == cap)
429	pos += PCI_CAP_LIST_NEXT;	434	return pos;
430	}	435	pos += PCI_CAP_LIST_NEXT;
431	return 0;	436	}
432	}	437	return 0;
433		438	}
434	static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,	439
435	u8 pos, int cap)	440	static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
436	{	441	u8 pos, int cap)
437	int ttl = PCI_FIND_CAP_TTL;	442	{
438		443	int ttl = PCI_FIND_CAP_TTL;
439	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);	444
440	}	445	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
441		446	}
442	static int __pci_bus_find_cap_start(unsigned int bus,	447
443	unsigned int devfn, u8 hdr_type)	448	static int __pci_bus_find_cap_start(unsigned int bus,
444	{	449	unsigned int devfn, u8 hdr_type)
445	u16 status;	450	{
446		451	u16 status;
447	status = PciRead16(bus, devfn, PCI_STATUS);	452
448	if (!(status & PCI_STATUS_CAP_LIST))	453	status = PciRead16(bus, devfn, PCI_STATUS);
449	return 0;	454	if (!(status & PCI_STATUS_CAP_LIST))
450		455	return 0;
451	switch (hdr_type) {	456
452	case PCI_HEADER_TYPE_NORMAL:	457	switch (hdr_type) {
453	case PCI_HEADER_TYPE_BRIDGE:	458	case PCI_HEADER_TYPE_NORMAL:
454	return PCI_CAPABILITY_LIST;	459	case PCI_HEADER_TYPE_BRIDGE:
455	case PCI_HEADER_TYPE_CARDBUS:	460	return PCI_CAPABILITY_LIST;
456	return PCI_CB_CAPABILITY_LIST;	461	case PCI_HEADER_TYPE_CARDBUS:
457	default:	462	return PCI_CB_CAPABILITY_LIST;
458	return 0;	463	default:
459	}	464	return 0;
460		465	}
461	return 0;	466
462	}	467	return 0;
463		468	}
464		469
465	int pci_find_capability(struct pci_dev *dev, int cap)	470
466	{	471	int pci_find_capability(struct pci_dev *dev, int cap)
467	int pos;	472	{
468		473	int pos;
469	pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);	474
470	if (pos)	475	pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
471	pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);	476	if (pos)
472		477	pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
473	return pos;	478
474	}	479	return pos;
475		480	}
476		481
477		482
478		483
479	int enum_pci_devices()	484
480	{	485	int enum_pci_devices()
481	pci_dev_t *dev;	486	{
482	u32 last_bus;	487	pci_dev_t *dev;
483	u32 bus = 0 , devfn = 0;	488	u32 last_bus;
484		489	u32 bus = 0 , devfn = 0;
485		490
486	last_bus = PciApi(1);	491
487		492	last_bus = PciApi(1);
488		493
489	if( unlikely(last_bus == -1))	494
490	return -1;	495	if( unlikely(last_bus == -1))
491		496	return -1;
492	for(;bus <= last_bus; bus++)	497
493	{	498	for(;bus <= last_bus; bus++)
494	for (devfn = 0; devfn < 0x100; devfn += 8)	499	{

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(root)/drivers/video/drm/radeon/pci.c – Rev 5271 → 6104