WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/pci.c


#include 
#include 
#include 
#include 
#include 
#include 
#include 
 
extern int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn);
 
static LIST_HEAD(devices);
 
/* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
#define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */
 
#define LEGACY_IO_RESOURCE      (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 
/*
 * Translate the low bits of the PCI base
 * to the resource type
 */
static inline unsigned int pci_calc_resource_flags(unsigned int flags)
{
    if (flags & PCI_BASE_ADDRESS_SPACE_IO)
        return IORESOURCE_IO;
 
    if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
        return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 
    return IORESOURCE_MEM;
}
 
 
static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask)
{
    u32_t size = mask & maxbase;      /* Find the significant bits */
 
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask)
{
    u64_t size = mask & maxbase;      /* Find the significant bits */
 
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static inline int is_64bit_memory(u32_t mask)
{
    if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
        (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
        return 1;
    return 0;
}
 
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
{
    u32_t  pos, reg, next;
    u32_t  l, sz;
    struct resource *res;
 
    for(pos=0; pos < howmany; pos = next)
    {
        u64_t  l64;
        u64_t  sz64;
        u32_t  raw_sz;
 
        next = pos + 1;
 
        res  = &dev->resource[pos];
 
        reg = PCI_BASE_ADDRESS_0 + (pos << 2);
        l = PciRead32(dev->busnr, dev->devfn, reg);
        PciWrite32(dev->busnr, dev->devfn, reg, ~0);
        sz = PciRead32(dev->busnr, dev->devfn, reg);
        PciWrite32(dev->busnr, dev->devfn, reg, l);
 
        if (!sz || sz == 0xffffffff)
            continue;
 
        if (l == 0xffffffff)
            l = 0;
 
        raw_sz = sz;
        if ((l & PCI_BASE_ADDRESS_SPACE) ==
                        PCI_BASE_ADDRESS_SPACE_MEMORY)
        {
            sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK);
            /*
             * For 64bit prefetchable memory sz could be 0, if the
             * real size is bigger than 4G, so we need to check
             * szhi for that.
             */
            if (!is_64bit_memory(l) && !sz)
                    continue;
            res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
            res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
        }
        else {
            sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
            if (!sz)
                continue;
            res->start = l & PCI_BASE_ADDRESS_IO_MASK;
            res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
        }
        res->end = res->start + (unsigned long) sz;
        res->flags |= pci_calc_resource_flags(l);
        if (is_64bit_memory(l))
        {
            u32_t szhi, lhi;
 
            lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
            PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
            szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
            PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
            sz64 = ((u64_t)szhi << 32) | raw_sz;
            l64 = ((u64_t)lhi << 32) | l;
            sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
            next++;
 
#if BITS_PER_LONG == 64
            if (!sz64) {
                res->start = 0;
                res->end = 0;
                res->flags = 0;
                continue;
            }
            res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
            res->end = res->start + sz64;
#else
            if (sz64 > 0x100000000ULL) {
                printk(KERN_ERR "PCI: Unable to handle 64-bit "
                                "BAR for device %s\n", pci_name(dev));
                res->start = 0;
                res->flags = 0;
            }
            else if (lhi)
            {
                /* 64-bit wide address, treat as disabled */
                PciWrite32(dev->busnr, dev->devfn, reg,
                        l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK);
                PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
                res->start = 0;
                res->end = sz;
            }
#endif
        }
    }
 
    if ( rom )
    {
        dev->rom_base_reg = rom;
        res = &dev->resource[PCI_ROM_RESOURCE];
 
        l = PciRead32(dev->busnr, dev->devfn, rom);
        PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
        sz = PciRead32(dev->busnr, dev->devfn, rom);
        PciWrite32(dev->busnr, dev->devfn, rom, l);
 
        if (l == 0xffffffff)
            l = 0;
 
        if (sz && sz != 0xffffffff)
        {
            sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK);
 
            if (sz)
            {
                res->flags = (l & IORESOURCE_ROM_ENABLE) |
                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |
                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
                res->start = l & PCI_ROM_ADDRESS_MASK;
                res->end = res->start + (unsigned long) sz;
            }
        }
    }
}
 
static void pci_read_irq(struct pci_dev *dev)
{
    u8_t irq;
 
    irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
    dev->pin = irq;
    if (irq)
        irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
    dev->irq = irq;
};
 
 
int pci_setup_device(struct pci_dev *dev)
{
    u32_t  class;
 
    class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
    dev->revision = class & 0xff;
    class >>= 8;                                /* upper 3 bytes */
    dev->class = class;
 
    /* "Unknown power state" */
//    dev->current_state = PCI_UNKNOWN;
 
    /* Early fixups, before probing the BARs */
 //   pci_fixup_device(pci_fixup_early, dev);
    class = dev->class >> 8;
 
    switch (dev->hdr_type)
    {
        case PCI_HEADER_TYPE_NORMAL:                /* standard header */
            if (class == PCI_CLASS_BRIDGE_PCI)
                goto bad;
            pci_read_irq(dev);
            pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
            dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
            dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
 
            /*
             *      Do the ugly legacy mode stuff here rather than broken chip
             *      quirk code. Legacy mode ATA controllers have fixed
             *      addresses. These are not always echoed in BAR0-3, and
             *      BAR0-3 in a few cases contain junk!
             */
            if (class == PCI_CLASS_STORAGE_IDE)
            {
                u8_t progif;
 
                progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
                if ((progif & 1) == 0)
                {
                    dev->resource[0].start = 0x1F0;
                    dev->resource[0].end = 0x1F7;
                    dev->resource[0].flags = LEGACY_IO_RESOURCE;
                    dev->resource[1].start = 0x3F6;
                    dev->resource[1].end = 0x3F6;
                    dev->resource[1].flags = LEGACY_IO_RESOURCE;
                }
                if ((progif & 4) == 0)
                {
                    dev->resource[2].start = 0x170;
                    dev->resource[2].end = 0x177;
                    dev->resource[2].flags = LEGACY_IO_RESOURCE;
                    dev->resource[3].start = 0x376;
                    dev->resource[3].end = 0x376;
                    dev->resource[3].flags = LEGACY_IO_RESOURCE;
                };
            }
            break;
 
        case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
                if (class != PCI_CLASS_BRIDGE_PCI)
                        goto bad;
                /* The PCI-to-PCI bridge spec requires that subtractive
                   decoding (i.e. transparent) bridge must have programming
                   interface code of 0x01. */
                pci_read_irq(dev);
                dev->transparent = ((dev->class & 0xff) == 1);
                pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
                break;
 
        case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
                if (class != PCI_CLASS_BRIDGE_CARDBUS)
                        goto bad;
                pci_read_irq(dev);
                pci_read_bases(dev, 1, 0);
                dev->subsystem_vendor = PciRead16(dev->busnr,
                                                  dev->devfn,
                                                  PCI_CB_SUBSYSTEM_VENDOR_ID);
 
                dev->subsystem_device = PciRead16(dev->busnr,
                                                  dev->devfn,
                                                  PCI_CB_SUBSYSTEM_ID);
                break;
 
        default:                                    /* unknown header */
                printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
                        pci_name(dev), dev->hdr_type);
                return -1;
 
        bad:
                printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
                       pci_name(dev), class, dev->hdr_type);
                dev->class = PCI_CLASS_NOT_DEFINED;
    }
 
    /* We found a fine healthy device, go go go... */
 
    return 0;
};
 
static pci_dev_t* pci_scan_device(u32_t busnr, int devfn)
{
    pci_dev_t  *dev;
 
    u32_t   id;
    u8_t    hdr;
 
    int     timeout = 10;
 
    id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
 
    /* some broken boards return 0 or ~0 if a slot is empty: */
    if (id == 0xffffffff || id == 0x00000000 ||
        id == 0x0000ffff || id == 0xffff0000)
        return NULL;
 
    while (id == 0xffff0001)
    {
 
        delay(timeout/10);
        timeout *= 2;
 
        id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
 
        /* Card hasn't responded in 60 seconds?  Must be stuck. */
        if (timeout > 60 * 100)
        {
            printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
                   "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
            return NULL;
        }
    };
 
    if( pci_scan_filter(id, busnr, devfn) == 0)
        return NULL;
 
    hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
 
    dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
    if(unlikely(dev == NULL))
        return NULL;
 
    INIT_LIST_HEAD(&dev->link);
 
 
    dev->pci_dev.busnr    = busnr;
    dev->pci_dev.devfn    = devfn;
    dev->pci_dev.hdr_type = hdr & 0x7f;
    dev->pci_dev.multifunction    = !!(hdr & 0x80);
    dev->pci_dev.vendor   = id & 0xffff;
    dev->pci_dev.device   = (id >> 16) & 0xffff;
 
    pci_setup_device(&dev->pci_dev);
 
    return dev;
 
};
 
 
 
 
int pci_scan_slot(u32_t bus, int devfn)
{
    int  func, nr = 0;
 
    for (func = 0; func < 8; func++, devfn++)
    {
        pci_dev_t  *dev;
 
        dev = pci_scan_device(bus, devfn);
        if( dev )
        {
            list_add(&dev->link, &devices);
 
            nr++;
 
            /*
             * If this is a single function device,
             * don't scan past the first function.
             */
            if (!dev->pci_dev.multifunction)
            {
                if (func > 0) {
                    dev->pci_dev.multifunction = 1;
                }
                else {
                    break;
                }
             }
        }
        else {
            if (func == 0)
                break;
        }
    };
 
    return nr;
};
 
#define PCI_FIND_CAP_TTL    48
 
static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
                   u8 pos, int cap, int *ttl)
{
    u8 id;
 
    while ((*ttl)--) {
        pos = PciRead8(bus, devfn, pos);
        if (pos < 0x40)
            break;
        pos &= ~3;
        id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
        if (id == 0xff)
            break;
        if (id == cap)
            return pos;
        pos += PCI_CAP_LIST_NEXT;
    }
    return 0;
}
 
static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
                   u8 pos, int cap)
{
    int ttl = PCI_FIND_CAP_TTL;
 
    return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
}
 
static int __pci_bus_find_cap_start(unsigned int bus,
                    unsigned int devfn, u8 hdr_type)
{
    u16 status;
 
    status = PciRead16(bus, devfn, PCI_STATUS);
    if (!(status & PCI_STATUS_CAP_LIST))
        return 0;
 
    switch (hdr_type) {
    case PCI_HEADER_TYPE_NORMAL:
    case PCI_HEADER_TYPE_BRIDGE:
        return PCI_CAPABILITY_LIST;
    case PCI_HEADER_TYPE_CARDBUS:
        return PCI_CB_CAPABILITY_LIST;
    default:
        return 0;
    }
 
    return 0;
}
 
 
int pci_find_capability(struct pci_dev *dev, int cap)
{
    int pos;
 
    pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
    if (pos)
        pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
 
    return pos;
}
 
 
 
 
int enum_pci_devices()
{
    pci_dev_t  *dev;
    u32_t       last_bus;
    u32_t       bus = 0 , devfn = 0;
 
 
    last_bus = PciApi(1);
 
 
    if( unlikely(last_bus == -1))
        return -1;
 
    for(;bus <= last_bus; bus++)
    {
        for (devfn = 0; devfn < 0x100; devfn += 8)
            pci_scan_slot(bus, devfn);
 
 
    }
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",
                dev->pci_dev.vendor,
                dev->pci_dev.device,
                dev->pci_dev.busnr,
                dev->pci_dev.devfn);
 
    }
    return 0;
}
 
const struct pci_device_id* find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist)
{
    pci_dev_t *dev;
    const struct pci_device_id *ent;
 
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.vendor != idlist->vendor )
            continue;
 
        for(ent = idlist; ent->vendor != 0; ent++)
        {
            if(unlikely(ent->device == dev->pci_dev.device))
            {
                pdev->pci_dev = dev->pci_dev;
                return  ent;
            }
        };
    }
 
    return NULL;
};
 
struct pci_dev *
pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
{
    pci_dev_t *dev;
 
    dev = (pci_dev_t*)devices.next;
 
    if(from != NULL)
    {
        for(; &dev->link != &devices;
            dev = (pci_dev_t*)dev->link.next)
        {
            if( &dev->pci_dev == from)
            {
                dev = (pci_dev_t*)dev->link.next;
                break;
            };
        }
    };
 
    for(; &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.vendor != vendor )
                continue;
 
        if(dev->pci_dev.device == device)
        {
            return &dev->pci_dev;
        }
    }
    return NULL;
};
 
 
struct pci_dev * pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
{
    pci_dev_t *dev;
 
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn)
            return &dev->pci_dev;
    }
    return NULL;
}
 
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
{
    pci_dev_t *dev;
 
    dev = (pci_dev_t*)devices.next;
 
    if(from != NULL)
    {
        for(; &dev->link != &devices;
            dev = (pci_dev_t*)dev->link.next)
        {
            if( &dev->pci_dev == from)
            {
                dev = (pci_dev_t*)dev->link.next;
                break;
            };
        }
    };
 
    for(; &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.class == class)
        {
            return &dev->pci_dev;
        }
    }
 
   return NULL;
}
 
 
#define PIO_OFFSET      0x10000UL
#define PIO_MASK        0x0ffffUL
#define PIO_RESERVED    0x40000UL
 
#define IO_COND(addr, is_pio, is_mmio) do {            \
    unsigned long port = (unsigned long __force)addr;  \
    if (port >= PIO_RESERVED) {                        \
        is_mmio;                                       \
    } else if (port > PIO_OFFSET) {                    \
        port &= PIO_MASK;                              \
        is_pio;                                        \
    };                                                 \
} while (0)
 
/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
    return (void __iomem *) port;
}
 
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
    resource_size_t start = pci_resource_start(dev, bar);
    resource_size_t len = pci_resource_len(dev, bar);
    unsigned long flags = pci_resource_flags(dev, bar);
 
    if (!len || !start)
        return NULL;
    if (maxlen && len > maxlen)
        len = maxlen;
    if (flags & IORESOURCE_IO)
        return ioport_map(start, len);
    if (flags & IORESOURCE_MEM) {
        return ioremap(start, len);
    }
    /* What? */
    return NULL;
}
 
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
    IO_COND(addr, /* nothing */, iounmap(addr));
}
 
 
struct pci_bus_region {
    resource_size_t start;
    resource_size_t end;
};
 
static inline void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
                         struct resource *res)
{
    region->start = res->start;
    region->end = res->end;
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
int pci_enable_rom(struct pci_dev *pdev)
{
    struct resource *res = pdev->resource + PCI_ROM_RESOURCE;
    struct pci_bus_region region;
    u32 rom_addr;
 
    if (!res->flags)
            return -1;
 
    pcibios_resource_to_bus(pdev, ®ion, res);
    pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
    rom_addr &= ~PCI_ROM_ADDRESS_MASK;
    rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;
    pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
    return 0;
}
 
void pci_disable_rom(struct pci_dev *pdev)
{
    u32 rom_addr;
    pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
    rom_addr &= ~PCI_ROM_ADDRESS_ENABLE;
    pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
}
 
/**
 * pci_get_rom_size - obtain the actual size of the ROM image
 * @pdev: target PCI device
 * @rom: kernel virtual pointer to image of ROM
 * @size: size of PCI window
 *  return: size of actual ROM image
 *
 * Determine the actual length of the ROM image.
 * The PCI window size could be much larger than the
 * actual image size.
 */
size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
{
        void __iomem *image;
        int last_image;
 
        image = rom;
        do {
                void __iomem *pds;
                /* Standard PCI ROMs start out with these bytes 55 AA */
                if (readb(image) != 0x55) {
                        dev_err(&pdev->dev, "Invalid ROM contents\n");
                        break;
            }
                if (readb(image + 1) != 0xAA)
                        break;
                /* get the PCI data structure and check its signature */
                pds = image + readw(image + 24);
                if (readb(pds) != 'P')
                        break;
                if (readb(pds + 1) != 'C')
                        break;
                if (readb(pds + 2) != 'I')
                        break;
                if (readb(pds + 3) != 'R')
                        break;
                last_image = readb(pds + 21) & 0x80;
                /* this length is reliable */
                image += readw(pds + 16) * 512;
        } while (!last_image);
 
        /* never return a size larger than the PCI resource window */
        /* there are known ROMs that get the size wrong */
        return min((size_t)(image - rom), size);
}
 
 
/**
 * pci_map_rom - map a PCI ROM to kernel space
 * @pdev: pointer to pci device struct
 * @size: pointer to receive size of pci window over ROM
 *
 * Return: kernel virtual pointer to image of ROM
 *
 * Map a PCI ROM into kernel space. If ROM is boot video ROM,
 * the shadow BIOS copy will be returned instead of the
 * actual ROM.
 */
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
{
    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
    loff_t start;
    void __iomem *rom;
 
//    ENTER();
 
//    dbgprintf("resource start %x end %x flags %x\n",
//               res->start, res->end, res->flags);
    /*
     * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
     * memory map if the VGA enable bit of the Bridge Control register is
     * set for embedded VGA.
     */
 
    start = (loff_t)0xC0000;
    *size = 0x20000; /* cover C000:0 through E000:0 */
 
#if 0
 
    if (res->flags & IORESOURCE_ROM_SHADOW) {
        /* primary video rom always starts here */
        start = (loff_t)0xC0000;
        *size = 0x20000; /* cover C000:0 through E000:0 */
    } else {
        if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
            *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
             return (void __iomem *)(unsigned long)
             pci_resource_start(pdev, PCI_ROM_RESOURCE);
        } else {
                /* assign the ROM an address if it doesn't have one */
//                        if (res->parent == NULL &&
//                            pci_assign_resource(pdev,PCI_ROM_RESOURCE))
                     return NULL;
//                        start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
//                        *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
//                        if (*size == 0)
//                                return NULL;
 
             /* Enable ROM space decodes */
//                        if (pci_enable_rom(pdev))
//                                return NULL;
        }
    }
#endif
 
    rom = ioremap(start, *size);
    if (!rom) {
            /* restore enable if ioremap fails */
            if (!(res->flags & (IORESOURCE_ROM_ENABLE |
                                IORESOURCE_ROM_SHADOW |
                                IORESOURCE_ROM_COPY)))
                    pci_disable_rom(pdev);
            return NULL;
    }
 
    /*
     * Try to find the true size of the ROM since sometimes the PCI window
     * size is much larger than the actual size of the ROM.
     * True size is important if the ROM is going to be copied.
     */
    *size = pci_get_rom_size(pdev, rom, *size);
//    LEAVE();
    return rom;
}
 
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
{
    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
 
    if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY))
            return;
 
    iounmap(rom);
 
    /* Disable again before continuing, leave enabled if pci=rom */
    if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW)))
            pci_disable_rom(pdev);
}
 
int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
{
    dev->dma_mask = mask;
 
    return 0;
}
 
 
 
static void __pci_set_master(struct pci_dev *dev, bool enable)
{
    u16 old_cmd, cmd;
 
    pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
    if (enable)
        cmd = old_cmd | PCI_COMMAND_MASTER;
    else
        cmd = old_cmd & ~PCI_COMMAND_MASTER;
    if (cmd != old_cmd) {
        pci_write_config_word(dev, PCI_COMMAND, cmd);
        }
    dev->is_busmaster = enable;
}
 
 
/* pci_set_master - enables bus-mastering for device dev
 * @dev: the PCI device to enable
 *
 * Enables bus-mastering on the device and calls pcibios_set_master()
 * to do the needed arch specific settings.
 */
void pci_set_master(struct pci_dev *dev)
{
        __pci_set_master(dev, true);
//        pcibios_set_master(dev);
}
 
/**
 * pci_clear_master - disables bus-mastering for device dev
 * @dev: the PCI device to disable
 */
void pci_clear_master(struct pci_dev *dev)
{
        __pci_set_master(dev, false);
}
 
 
static inline int pcie_cap_version(const struct pci_dev *dev)
{
    return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS;
}
 
static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
{
    return true;
}
 
static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           type == PCI_EXP_TYPE_ENDPOINT ||
           type == PCI_EXP_TYPE_LEG_END;
}
 
static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           (type == PCI_EXP_TYPE_DOWNSTREAM &&
        dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);
}
 
static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           type == PCI_EXP_TYPE_RC_EC;
}
 
static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
{
    if (!pci_is_pcie(dev))
        return false;
 
    switch (pos) {
    case PCI_EXP_FLAGS_TYPE:
        return true;
    case PCI_EXP_DEVCAP:
    case PCI_EXP_DEVCTL:
    case PCI_EXP_DEVSTA:
        return pcie_cap_has_devctl(dev);
    case PCI_EXP_LNKCAP:
    case PCI_EXP_LNKCTL:
    case PCI_EXP_LNKSTA:
        return pcie_cap_has_lnkctl(dev);
    case PCI_EXP_SLTCAP:
    case PCI_EXP_SLTCTL:
    case PCI_EXP_SLTSTA:
        return pcie_cap_has_sltctl(dev);
    case PCI_EXP_RTCTL:
    case PCI_EXP_RTCAP:
    case PCI_EXP_RTSTA:
        return pcie_cap_has_rtctl(dev);
    case PCI_EXP_DEVCAP2:
    case PCI_EXP_DEVCTL2:
    case PCI_EXP_LNKCAP2:
    case PCI_EXP_LNKCTL2:
    case PCI_EXP_LNKSTA2:
        return pcie_cap_version(dev) > 1;
    default:
        return false;
    }
}
 
/*
 * Note that these accessor functions are only for the "PCI Express
 * Capability" (see PCIe spec r3.0, sec 7.8).  They do not apply to the
 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
 */
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
{
    int ret;
 
    *val = 0;
    if (pos & 1)
        return -EINVAL;
 
    if (pcie_capability_reg_implemented(dev, pos)) {
        ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
        /*
         * Reset *val to 0 if pci_read_config_word() fails, it may
         * have been written as 0xFFFF if hardware error happens
         * during pci_read_config_word().
         */
        if (ret)
            *val = 0;
        return ret;
    }
 
    /*
     * For Functions that do not implement the Slot Capabilities,
     * Slot Status, and Slot Control registers, these spaces must
     * be hardwired to 0b, with the exception of the Presence Detect
     * State bit in the Slot Status register of Downstream Ports,
     * which must be hardwired to 1b.  (PCIe Base Spec 3.0, sec 7.8)
     */
    if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
         pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
        *val = PCI_EXP_SLTSTA_PDS;
    }
 
    return 0;
}
EXPORT_SYMBOL(pcie_capability_read_word);
 
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
{
    int ret;
 
    *val = 0;
    if (pos & 3)
        return -EINVAL;
 
    if (pcie_capability_reg_implemented(dev, pos)) {
        ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
        /*
         * Reset *val to 0 if pci_read_config_dword() fails, it may
         * have been written as 0xFFFFFFFF if hardware error happens
         * during pci_read_config_dword().
         */
        if (ret)
            *val = 0;
        return ret;
    }
 
    if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
         pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
        *val = PCI_EXP_SLTSTA_PDS;
    }
 
    return 0;
}
EXPORT_SYMBOL(pcie_capability_read_dword);
 
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
{
    if (pos & 1)
        return -EINVAL;
 
    if (!pcie_capability_reg_implemented(dev, pos))
        return 0;
 
    return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_word);
 
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
{
    if (pos & 3)
        return -EINVAL;
 
    if (!pcie_capability_reg_implemented(dev, pos))
        return 0;
 
    return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_dword);

Rev 2997	Rev 3031
1	#include	1	#include
2	#include	2	#include
3	#include	3	#include
4	#include	4	#include
5	#include	5	#include
6	#include	6	#include
7	#include	7	#include
8		8
9	extern int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn);	9	extern int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn);
10		10
11	static LIST_HEAD(devices);	11	static LIST_HEAD(devices);
12		12
13	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */	13	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
14	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */	14	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
15		15
16	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)	16	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)
17		17
18	/*	18	/*
19	* Translate the low bits of the PCI base	19	* Translate the low bits of the PCI base
20	* to the resource type	20	* to the resource type
21	*/	21	*/
22	static inline unsigned int pci_calc_resource_flags(unsigned int flags)	22	static inline unsigned int pci_calc_resource_flags(unsigned int flags)
23	{	23	{
24	if (flags & PCI_BASE_ADDRESS_SPACE_IO)	24	if (flags & PCI_BASE_ADDRESS_SPACE_IO)
25	return IORESOURCE_IO;	25	return IORESOURCE_IO;
26		26
27	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)	27	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
28	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;	28	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;
29		29
30	return IORESOURCE_MEM;	30	return IORESOURCE_MEM;
31	}	31	}
32		32
33		33
34	static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask)	34	static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask)
35	{	35	{
36	u32_t size = mask & maxbase; /* Find the significant bits */	36	u32_t size = mask & maxbase; /* Find the significant bits */
37		37
38	if (!size)	38	if (!size)
39	return 0;	39	return 0;
40		40
41	/* Get the lowest of them to find the decode size, and	41	/* Get the lowest of them to find the decode size, and
42	from that the extent. */	42	from that the extent. */
43	size = (size & ~(size-1)) - 1;	43	size = (size & ~(size-1)) - 1;
44		44
45	/* base == maxbase can be valid only if the BAR has	45	/* base == maxbase can be valid only if the BAR has
46	already been programmed with all 1s. */	46	already been programmed with all 1s. */
47	if (base == maxbase && ((base \| size) & mask) != mask)	47	if (base == maxbase && ((base \| size) & mask) != mask)
48	return 0;	48	return 0;
49		49
50	return size;	50	return size;
51	}	51	}
52		52
53	static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask)	53	static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask)
54	{	54	{
55	u64_t size = mask & maxbase; /* Find the significant bits */	55	u64_t size = mask & maxbase; /* Find the significant bits */
56		56
57	if (!size)	57	if (!size)
58	return 0;	58	return 0;
59		59
60	/* Get the lowest of them to find the decode size, and	60	/* Get the lowest of them to find the decode size, and
61	from that the extent. */	61	from that the extent. */
62	size = (size & ~(size-1)) - 1;	62	size = (size & ~(size-1)) - 1;
63		63
64	/* base == maxbase can be valid only if the BAR has	64	/* base == maxbase can be valid only if the BAR has
65	already been programmed with all 1s. */	65	already been programmed with all 1s. */
66	if (base == maxbase && ((base \| size) & mask) != mask)	66	if (base == maxbase && ((base \| size) & mask) != mask)
67	return 0;	67	return 0;
68		68
69	return size;	69	return size;
70	}	70	}
71		71
72	static inline int is_64bit_memory(u32_t mask)	72	static inline int is_64bit_memory(u32_t mask)
73	{	73	{
74	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==	74	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
75	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))	75	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))
76	return 1;	76	return 1;
77	return 0;	77	return 0;
78	}	78	}
79		79
80	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)	80	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
81	{	81	{
82	u32_t pos, reg, next;	82	u32_t pos, reg, next;
83	u32_t l, sz;	83	u32_t l, sz;
84	struct resource *res;	84	struct resource *res;
85		85
86	for(pos=0; pos < howmany; pos = next)	86	for(pos=0; pos < howmany; pos = next)
87	{	87	{
88	u64_t l64;	88	u64_t l64;
89	u64_t sz64;	89	u64_t sz64;
90	u32_t raw_sz;	90	u32_t raw_sz;
91		91
92	next = pos + 1;	92	next = pos + 1;
93		93
94	res = &dev->resource[pos];	94	res = &dev->resource[pos];
95		95
96	reg = PCI_BASE_ADDRESS_0 + (pos << 2);	96	reg = PCI_BASE_ADDRESS_0 + (pos << 2);
97	l = PciRead32(dev->busnr, dev->devfn, reg);	97	l = PciRead32(dev->busnr, dev->devfn, reg);
98	PciWrite32(dev->busnr, dev->devfn, reg, ~0);	98	PciWrite32(dev->busnr, dev->devfn, reg, ~0);
99	sz = PciRead32(dev->busnr, dev->devfn, reg);	99	sz = PciRead32(dev->busnr, dev->devfn, reg);
100	PciWrite32(dev->busnr, dev->devfn, reg, l);	100	PciWrite32(dev->busnr, dev->devfn, reg, l);
101		101
102	if (!sz \|\| sz == 0xffffffff)	102	if (!sz \|\| sz == 0xffffffff)
103	continue;	103	continue;
104		104
105	if (l == 0xffffffff)	105	if (l == 0xffffffff)
106	l = 0;	106	l = 0;
107		107
108	raw_sz = sz;	108	raw_sz = sz;
109	if ((l & PCI_BASE_ADDRESS_SPACE) ==	109	if ((l & PCI_BASE_ADDRESS_SPACE) ==
110	PCI_BASE_ADDRESS_SPACE_MEMORY)	110	PCI_BASE_ADDRESS_SPACE_MEMORY)
111	{	111	{
112	sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK);	112	sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK);
113	/*	113	/*
114	* For 64bit prefetchable memory sz could be 0, if the	114	* For 64bit prefetchable memory sz could be 0, if the
115	* real size is bigger than 4G, so we need to check	115	* real size is bigger than 4G, so we need to check
116	* szhi for that.	116	* szhi for that.
117	*/	117	*/
118	if (!is_64bit_memory(l) && !sz)	118	if (!is_64bit_memory(l) && !sz)
119	continue;	119	continue;
120	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;	120	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
121	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;	121	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;
122	}	122	}
123	else {	123	else {
124	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);	124	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
125	if (!sz)	125	if (!sz)
126	continue;	126	continue;
127	res->start = l & PCI_BASE_ADDRESS_IO_MASK;	127	res->start = l & PCI_BASE_ADDRESS_IO_MASK;
128	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;	128	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;
129	}	129	}
130	res->end = res->start + (unsigned long) sz;	130	res->end = res->start + (unsigned long) sz;
131	res->flags \|= pci_calc_resource_flags(l);	131	res->flags \|= pci_calc_resource_flags(l);
132	if (is_64bit_memory(l))	132	if (is_64bit_memory(l))
133	{	133	{
134	u32_t szhi, lhi;	134	u32_t szhi, lhi;
135		135
136	lhi = PciRead32(dev->busnr, dev->devfn, reg+4);	136	lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
137	PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);	137	PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
138	szhi = PciRead32(dev->busnr, dev->devfn, reg+4);	138	szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
139	PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);	139	PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
140	sz64 = ((u64_t)szhi << 32) \| raw_sz;	140	sz64 = ((u64_t)szhi << 32) \| raw_sz;
141	l64 = ((u64_t)lhi << 32) \| l;	141	l64 = ((u64_t)lhi << 32) \| l;
142	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);	142	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
143	next++;	143	next++;
144		144
145	#if BITS_PER_LONG == 64	145	#if BITS_PER_LONG == 64
146	if (!sz64) {	146	if (!sz64) {
147	res->start = 0;	147	res->start = 0;
148	res->end = 0;	148	res->end = 0;
149	res->flags = 0;	149	res->flags = 0;
150	continue;	150	continue;
151	}	151	}
152	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;	152	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
153	res->end = res->start + sz64;	153	res->end = res->start + sz64;
154	#else	154	#else
155	if (sz64 > 0x100000000ULL) {	155	if (sz64 > 0x100000000ULL) {
156	printk(KERN_ERR "PCI: Unable to handle 64-bit "	156	printk(KERN_ERR "PCI: Unable to handle 64-bit "
157	"BAR for device %s\n", pci_name(dev));	157	"BAR for device %s\n", pci_name(dev));
158	res->start = 0;	158	res->start = 0;
159	res->flags = 0;	159	res->flags = 0;
160	}	160	}
161	else if (lhi)	161	else if (lhi)
162	{	162	{
163	/* 64-bit wide address, treat as disabled */	163	/* 64-bit wide address, treat as disabled */
164	PciWrite32(dev->busnr, dev->devfn, reg,	164	PciWrite32(dev->busnr, dev->devfn, reg,
165	l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK);	165	l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK);
166	PciWrite32(dev->busnr, dev->devfn, reg+4, 0);	166	PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
167	res->start = 0;	167	res->start = 0;
168	res->end = sz;	168	res->end = sz;
169	}	169	}
170	#endif	170	#endif
171	}	171	}
172	}	172	}
173		173
174	if ( rom )	174	if ( rom )
175	{	175	{
176	dev->rom_base_reg = rom;	176	dev->rom_base_reg = rom;
177	res = &dev->resource[PCI_ROM_RESOURCE];	177	res = &dev->resource[PCI_ROM_RESOURCE];
178		178
179	l = PciRead32(dev->busnr, dev->devfn, rom);	179	l = PciRead32(dev->busnr, dev->devfn, rom);
180	PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);	180	PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
181	sz = PciRead32(dev->busnr, dev->devfn, rom);	181	sz = PciRead32(dev->busnr, dev->devfn, rom);
182	PciWrite32(dev->busnr, dev->devfn, rom, l);	182	PciWrite32(dev->busnr, dev->devfn, rom, l);
183		183
184	if (l == 0xffffffff)	184	if (l == 0xffffffff)
185	l = 0;	185	l = 0;
186		186
187	if (sz && sz != 0xffffffff)	187	if (sz && sz != 0xffffffff)
188	{	188	{
189	sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK);	189	sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK);
190		190
191	if (sz)	191	if (sz)
192	{	192	{
193	res->flags = (l & IORESOURCE_ROM_ENABLE) \|	193	res->flags = (l & IORESOURCE_ROM_ENABLE) \|
194	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|	194	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|
195	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;	195	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;
196	res->start = l & PCI_ROM_ADDRESS_MASK;	196	res->start = l & PCI_ROM_ADDRESS_MASK;
197	res->end = res->start + (unsigned long) sz;	197	res->end = res->start + (unsigned long) sz;
198	}	198	}
199	}	199	}
200	}	200	}
201	}	201	}
202		202
203	static void pci_read_irq(struct pci_dev *dev)	203	static void pci_read_irq(struct pci_dev *dev)
204	{	204	{
205	u8_t irq;	205	u8_t irq;
206		206
207	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);	207	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
208	dev->pin = irq;	208	dev->pin = irq;
209	if (irq)	209	if (irq)
210	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);	210	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
211	dev->irq = irq;	211	dev->irq = irq;
212	};	212	};
213		213
214		214
215	int pci_setup_device(struct pci_dev *dev)	215	int pci_setup_device(struct pci_dev *dev)
216	{	216	{
217	u32_t class;	217	u32_t class;
218		218
219	class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);	219	class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
220	dev->revision = class & 0xff;	220	dev->revision = class & 0xff;
221	class >>= 8; /* upper 3 bytes */	221	class >>= 8; /* upper 3 bytes */
222	dev->class = class;	222	dev->class = class;
223		223
224	/* "Unknown power state" */	224	/* "Unknown power state" */
225	// dev->current_state = PCI_UNKNOWN;	225	// dev->current_state = PCI_UNKNOWN;
226		226
227	/* Early fixups, before probing the BARs */	227	/* Early fixups, before probing the BARs */
228	// pci_fixup_device(pci_fixup_early, dev);	228	// pci_fixup_device(pci_fixup_early, dev);
229	class = dev->class >> 8;	229	class = dev->class >> 8;
230		230
231	switch (dev->hdr_type)	231	switch (dev->hdr_type)
232	{	232	{
233	case PCI_HEADER_TYPE_NORMAL: /* standard header */	233	case PCI_HEADER_TYPE_NORMAL: /* standard header */
234	if (class == PCI_CLASS_BRIDGE_PCI)	234	if (class == PCI_CLASS_BRIDGE_PCI)
235	goto bad;	235	goto bad;
236	pci_read_irq(dev);	236	pci_read_irq(dev);
237	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);	237	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
238	dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);	238	dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
239	dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);	239	dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
240		240
241	/*	241	/*
242	* Do the ugly legacy mode stuff here rather than broken chip	242	* Do the ugly legacy mode stuff here rather than broken chip
243	* quirk code. Legacy mode ATA controllers have fixed	243	* quirk code. Legacy mode ATA controllers have fixed
244	* addresses. These are not always echoed in BAR0-3, and	244	* addresses. These are not always echoed in BAR0-3, and
245	* BAR0-3 in a few cases contain junk!	245	* BAR0-3 in a few cases contain junk!
246	*/	246	*/
247	if (class == PCI_CLASS_STORAGE_IDE)	247	if (class == PCI_CLASS_STORAGE_IDE)
248	{	248	{
249	u8_t progif;	249	u8_t progif;
250		250
251	progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);	251	progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
252	if ((progif & 1) == 0)	252	if ((progif & 1) == 0)
253	{	253	{
254	dev->resource[0].start = 0x1F0;	254	dev->resource[0].start = 0x1F0;
255	dev->resource[0].end = 0x1F7;	255	dev->resource[0].end = 0x1F7;
256	dev->resource[0].flags = LEGACY_IO_RESOURCE;	256	dev->resource[0].flags = LEGACY_IO_RESOURCE;
257	dev->resource[1].start = 0x3F6;	257	dev->resource[1].start = 0x3F6;
258	dev->resource[1].end = 0x3F6;	258	dev->resource[1].end = 0x3F6;
259	dev->resource[1].flags = LEGACY_IO_RESOURCE;	259	dev->resource[1].flags = LEGACY_IO_RESOURCE;
260	}	260	}
261	if ((progif & 4) == 0)	261	if ((progif & 4) == 0)
262	{	262	{
263	dev->resource[2].start = 0x170;	263	dev->resource[2].start = 0x170;
264	dev->resource[2].end = 0x177;	264	dev->resource[2].end = 0x177;
265	dev->resource[2].flags = LEGACY_IO_RESOURCE;	265	dev->resource[2].flags = LEGACY_IO_RESOURCE;
266	dev->resource[3].start = 0x376;	266	dev->resource[3].start = 0x376;
267	dev->resource[3].end = 0x376;	267	dev->resource[3].end = 0x376;
268	dev->resource[3].flags = LEGACY_IO_RESOURCE;	268	dev->resource[3].flags = LEGACY_IO_RESOURCE;
269	};	269	};
270	}	270	}
271	break;	271	break;
272		272
273	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */	273	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
274	if (class != PCI_CLASS_BRIDGE_PCI)	274	if (class != PCI_CLASS_BRIDGE_PCI)
275	goto bad;	275	goto bad;
276	/* The PCI-to-PCI bridge spec requires that subtractive	276	/* The PCI-to-PCI bridge spec requires that subtractive
277	decoding (i.e. transparent) bridge must have programming	277	decoding (i.e. transparent) bridge must have programming
278	interface code of 0x01. */	278	interface code of 0x01. */
279	pci_read_irq(dev);	279	pci_read_irq(dev);
280	dev->transparent = ((dev->class & 0xff) == 1);	280	dev->transparent = ((dev->class & 0xff) == 1);
281	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);	281	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
282	break;	282	break;
283		283
284	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */	284	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
285	if (class != PCI_CLASS_BRIDGE_CARDBUS)	285	if (class != PCI_CLASS_BRIDGE_CARDBUS)
286	goto bad;	286	goto bad;
287	pci_read_irq(dev);	287	pci_read_irq(dev);
288	pci_read_bases(dev, 1, 0);	288	pci_read_bases(dev, 1, 0);
289	dev->subsystem_vendor = PciRead16(dev->busnr,	289	dev->subsystem_vendor = PciRead16(dev->busnr,
290	dev->devfn,	290	dev->devfn,
291	PCI_CB_SUBSYSTEM_VENDOR_ID);	291	PCI_CB_SUBSYSTEM_VENDOR_ID);
292		292
293	dev->subsystem_device = PciRead16(dev->busnr,	293	dev->subsystem_device = PciRead16(dev->busnr,
294	dev->devfn,	294	dev->devfn,
295	PCI_CB_SUBSYSTEM_ID);	295	PCI_CB_SUBSYSTEM_ID);
296	break;	296	break;
297		297
298	default: /* unknown header */	298	default: /* unknown header */
299	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",	299	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
300	pci_name(dev), dev->hdr_type);	300	pci_name(dev), dev->hdr_type);
301	return -1;	301	return -1;
302		302
303	bad:	303	bad:
304	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",	304	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
305	pci_name(dev), class, dev->hdr_type);	305	pci_name(dev), class, dev->hdr_type);
306	dev->class = PCI_CLASS_NOT_DEFINED;	306	dev->class = PCI_CLASS_NOT_DEFINED;
307	}	307	}
308		308
309	/* We found a fine healthy device, go go go... */	309	/* We found a fine healthy device, go go go... */
310		310
311	return 0;	311	return 0;
312	};	312	};
313		313
314	static pci_dev_t* pci_scan_device(u32_t busnr, int devfn)	314	static pci_dev_t* pci_scan_device(u32_t busnr, int devfn)
315	{	315	{
316	pci_dev_t *dev;	316	pci_dev_t *dev;
317		317
318	u32_t id;	318	u32_t id;
319	u8_t hdr;	319	u8_t hdr;
320		320
321	int timeout = 10;	321	int timeout = 10;
322		322
323	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);	323	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
324		324
325	/* some broken boards return 0 or ~0 if a slot is empty: */	325	/* some broken boards return 0 or ~0 if a slot is empty: */
326	if (id == 0xffffffff \|\| id == 0x00000000 \|\|	326	if (id == 0xffffffff \|\| id == 0x00000000 \|\|
327	id == 0x0000ffff \|\| id == 0xffff0000)	327	id == 0x0000ffff \|\| id == 0xffff0000)
328	return NULL;	328	return NULL;
329		329
330	while (id == 0xffff0001)	330	while (id == 0xffff0001)
331	{	331	{
332		332
333	delay(timeout/10);	333	delay(timeout/10);
334	timeout *= 2;	334	timeout *= 2;
335		335
336	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);	336	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
337		337
338	/* Card hasn't responded in 60 seconds? Must be stuck. */	338	/* Card hasn't responded in 60 seconds? Must be stuck. */
339	if (timeout > 60 * 100)	339	if (timeout > 60 * 100)
340	{	340	{
341	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "	341	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
342	"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));	342	"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
343	return NULL;	343	return NULL;
344	}	344	}
345	};	345	};
346		346
347	if( pci_scan_filter(id, busnr, devfn) == 0)	347	if( pci_scan_filter(id, busnr, devfn) == 0)
348	return NULL;	348	return NULL;
349		349
350	hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);	350	hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
351		351
352	dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);	352	dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
353	if(unlikely(dev == NULL))	353	if(unlikely(dev == NULL))
354	return NULL;	354	return NULL;
355		355
356	INIT_LIST_HEAD(&dev->link);	356	INIT_LIST_HEAD(&dev->link);
357		357
358		358
359	dev->pci_dev.busnr = busnr;	359	dev->pci_dev.busnr = busnr;
360	dev->pci_dev.devfn = devfn;	360	dev->pci_dev.devfn = devfn;
361	dev->pci_dev.hdr_type = hdr & 0x7f;	361	dev->pci_dev.hdr_type = hdr & 0x7f;
362	dev->pci_dev.multifunction = !!(hdr & 0x80);	362	dev->pci_dev.multifunction = !!(hdr & 0x80);
363	dev->pci_dev.vendor = id & 0xffff;	363	dev->pci_dev.vendor = id & 0xffff;
364	dev->pci_dev.device = (id >> 16) & 0xffff;	364	dev->pci_dev.device = (id >> 16) & 0xffff;
365		365
366	pci_setup_device(&dev->pci_dev);	366	pci_setup_device(&dev->pci_dev);
367		367
368	return dev;	368	return dev;
369		369
370	};	370	};
371		371
372		372
373		373
374		374
375	int pci_scan_slot(u32_t bus, int devfn)	375	int pci_scan_slot(u32_t bus, int devfn)
376	{	376	{
377	int func, nr = 0;	377	int func, nr = 0;
378		378
379	for (func = 0; func < 8; func++, devfn++)	379	for (func = 0; func < 8; func++, devfn++)
380	{	380	{
381	pci_dev_t *dev;	381	pci_dev_t *dev;
382		382
383	dev = pci_scan_device(bus, devfn);	383	dev = pci_scan_device(bus, devfn);
384	if( dev )	384	if( dev )
385	{	385	{
386	list_add(&dev->link, &devices);	386	list_add(&dev->link, &devices);
387		387
388	nr++;	388	nr++;
389		389
390	/*	390	/*
391	* If this is a single function device,	391	* If this is a single function device,
392	* don't scan past the first function.	392	* don't scan past the first function.
393	*/	393	*/
394	if (!dev->pci_dev.multifunction)	394	if (!dev->pci_dev.multifunction)
395	{	395	{
396	if (func > 0) {	396	if (func > 0) {
397	dev->pci_dev.multifunction = 1;	397	dev->pci_dev.multifunction = 1;
398	}	398	}
399	else {	399	else {
400	break;	400	break;
401	}	401	}
402	}	402	}
403	}	403	}
404	else {	404	else {
405	if (func == 0)	405	if (func == 0)
406	break;	406	break;
407	}	407	}
408	};	408	};
409		409
410	return nr;	410	return nr;
411	};	411	};
412		412
413	#define PCI_FIND_CAP_TTL 48	413	#define PCI_FIND_CAP_TTL 48
414		414
415	static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,	415	static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
416	u8 pos, int cap, int *ttl)	416	u8 pos, int cap, int *ttl)
417	{	417	{
418	u8 id;	418	u8 id;
419		419
420	while ((*ttl)--) {	420	while ((*ttl)--) {
421	pos = PciRead8(bus, devfn, pos);	421	pos = PciRead8(bus, devfn, pos);
422	if (pos < 0x40)	422	if (pos < 0x40)
423	break;	423	break;
424	pos &= ~3;	424	pos &= ~3;
425	id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);	425	id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
426	if (id == 0xff)	426	if (id == 0xff)
427	break;	427	break;
428	if (id == cap)	428	if (id == cap)
429	return pos;	429	return pos;
430	pos += PCI_CAP_LIST_NEXT;	430	pos += PCI_CAP_LIST_NEXT;
431	}	431	}
432	return 0;	432	return 0;
433	}	433	}
434		434
435	static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,	435	static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
436	u8 pos, int cap)	436	u8 pos, int cap)
437	{	437	{
438	int ttl = PCI_FIND_CAP_TTL;	438	int ttl = PCI_FIND_CAP_TTL;
439		439
440	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);	440	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
441	}	441	}
442		442
443	static int __pci_bus_find_cap_start(unsigned int bus,	443	static int __pci_bus_find_cap_start(unsigned int bus,
444	unsigned int devfn, u8 hdr_type)	444	unsigned int devfn, u8 hdr_type)
445	{	445	{
446	u16 status;	446	u16 status;
447		447
448	status = PciRead16(bus, devfn, PCI_STATUS);	448	status = PciRead16(bus, devfn, PCI_STATUS);
449	if (!(status & PCI_STATUS_CAP_LIST))	449	if (!(status & PCI_STATUS_CAP_LIST))
450	return 0;	450	return 0;
451		451
452	switch (hdr_type) {	452	switch (hdr_type) {
453	case PCI_HEADER_TYPE_NORMAL:	453	case PCI_HEADER_TYPE_NORMAL:
454	case PCI_HEADER_TYPE_BRIDGE:	454	case PCI_HEADER_TYPE_BRIDGE:
455	return PCI_CAPABILITY_LIST;	455	return PCI_CAPABILITY_LIST;
456	case PCI_HEADER_TYPE_CARDBUS:	456	case PCI_HEADER_TYPE_CARDBUS:
457	return PCI_CB_CAPABILITY_LIST;	457	return PCI_CB_CAPABILITY_LIST;
458	default:	458	default:
459	return 0;	459	return 0;
460	}	460	}
461		461
462	return 0;	462	return 0;
463	}	463	}
464		464
465		465
466	int pci_find_capability(struct pci_dev *dev, int cap)	466	int pci_find_capability(struct pci_dev *dev, int cap)
467	{	467	{
468	int pos;	468	int pos;
469		469
470	pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);	470	pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
471	if (pos)	471	if (pos)
472	pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);	472	pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
473		473
474	return pos;	474	return pos;
475	}	475	}
476		476
477		477
478		478
479		479
480	int enum_pci_devices()	480	int enum_pci_devices()
481	{	481	{
482	pci_dev_t *dev;	482	pci_dev_t *dev;
483	u32_t last_bus;	483	u32_t last_bus;
484	u32_t bus = 0 , devfn = 0;	484	u32_t bus = 0 , devfn = 0;
485		485
486		486
487	last_bus = PciApi(1);	487	last_bus = PciApi(1);
488		488
489		489
490	if( unlikely(last_bus == -1))	490	if( unlikely(last_bus == -1))
491	return -1;	491	return -1;
492		492
493	for(;bus <= last_bus; bus++)	493	for(;bus <= last_bus; bus++)
494	{	494	{
495	for (devfn = 0; devfn < 0x100; devfn += 8)	495	for (devfn = 0; devfn < 0x100; devfn += 8)
496	pci_scan_slot(bus, devfn);	496	pci_scan_slot(bus, devfn);
497		497
498		498
499	}	499	}
500	for(dev = (pci_dev_t*)devices.next;	500	for(dev = (pci_dev_t*)devices.next;

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(root)/drivers/video/drm/radeon/pci.c – Rev 2997 → 3031