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Rev 5078 Rev 6104
Line 44... Line 44...
44 
#define CAYMAN_GB_ADDR_CONFIG_GOLDEN       0x02011003
 44 
#define CAYMAN_GB_ADDR_CONFIG_GOLDEN       0x02011003
45 
#define ARUBA_GB_ADDR_CONFIG_GOLDEN        0x12010001
 45 
#define ARUBA_GB_ADDR_CONFIG_GOLDEN        0x12010001
Line 46... Line 46...
46 
 
 46 
 
Line -... Line 47...
- 
 
 47 
#define DMIF_ADDR_CONFIG  				0xBD4
- 
 
 48 
 
- 
 
 49 
/* fusion vce clocks */
- 
 
 50 
#define CG_ECLK_CNTL                                    0x620
- 
 
 51 
#       define ECLK_DIVIDER_MASK                        0x7f
- 
 
 52 
#       define ECLK_DIR_CNTL_EN                         (1 << 8)
- 
 
 53 
#define CG_ECLK_STATUS                                  0x624
47 
#define DMIF_ADDR_CONFIG  				0xBD4
 54 
#       define ECLK_STATUS                              (1 << 0)
48 
 
 55 
 
Line 49... Line 56...
49 
/* DCE6 only */
 56 
/* DCE6 only */
50 
#define DMIF_ADDR_CALC  				0xC00
 57 
#define DMIF_ADDR_CALC  				0xC00
Line 80... Line 87...
80 
#define		SOFT_RESET_DMA				(1 << 20)
 87 
#define		SOFT_RESET_DMA				(1 << 20)
81 
#define		SOFT_RESET_TST				(1 << 21)
 88 
#define		SOFT_RESET_TST				(1 << 21)
82 
#define		SOFT_RESET_REGBB			(1 << 22)
 89 
#define		SOFT_RESET_REGBB			(1 << 22)
83 
#define		SOFT_RESET_ORB				(1 << 23)
 90 
#define		SOFT_RESET_ORB				(1 << 23)
Line -... Line 91...
- 
 
 91 
 
- 
 
 92 
#define SRBM_READ_ERROR					0xE98
- 
 
 93 
#define SRBM_INT_CNTL					0xEA0
- 
 
 94 
#define SRBM_INT_ACK					0xEA8
84 
 
 95 
 
85 
#define	SRBM_STATUS2				        0x0EC4
 96 
#define	SRBM_STATUS2				        0x0EC4
86 
#define		DMA_BUSY 				(1 << 5)
 97 
#define		DMA_BUSY 				(1 << 5)
Line 87... Line 98...
87 
#define		DMA1_BUSY 				(1 << 6)
 98 
#define		DMA1_BUSY 				(1 << 6)
Line 810... Line 821...
810 
#define MC_SEQ_PMG_TIMING_LP                            0x2b4c
 821 
#define MC_SEQ_PMG_TIMING_LP                            0x2b4c
Line 811... Line 822...
811 
 
 822 
 
812 
#define MC_PMG_CMD_MRS2                                 0x2b5c
 823 
#define MC_PMG_CMD_MRS2                                 0x2b5c
Line -... Line 824...
- 
 
 824 
#define MC_SEQ_PMG_CMD_MRS2_LP                          0x2b60
- 
 
 825 
 
- 
 
 826 
#define AUX_CONTROL					0x6200
- 
 
 827 
#define 	AUX_EN					(1 << 0)
- 
 
 828 
#define 	AUX_LS_READ_EN				(1 << 8)
- 
 
 829 
#define 	AUX_LS_UPDATE_DISABLE(x)		(((x) & 0x1) << 12)
- 
 
 830 
#define 	AUX_HPD_DISCON(x)			(((x) & 0x1) << 16)
- 
 
 831 
#define 	AUX_DET_EN				(1 << 18)
- 
 
 832 
#define 	AUX_HPD_SEL(x)				(((x) & 0x7) << 20)
- 
 
 833 
#define 	AUX_IMPCAL_REQ_EN			(1 << 24)
- 
 
 834 
#define 	AUX_TEST_MODE				(1 << 28)
- 
 
 835 
#define 	AUX_DEGLITCH_EN				(1 << 29)
- 
 
 836 
#define AUX_SW_CONTROL					0x6204
- 
 
 837 
#define 	AUX_SW_GO				(1 << 0)
- 
 
 838 
#define 	AUX_LS_READ_TRIG			(1 << 2)
- 
 
 839 
#define 	AUX_SW_START_DELAY(x)			(((x) & 0xf) << 4)
- 
 
 840 
#define 	AUX_SW_WR_BYTES(x)			(((x) & 0x1f) << 16)
- 
 
 841 
 
- 
 
 842 
#define AUX_SW_INTERRUPT_CONTROL			0x620c
- 
 
 843 
#define 	AUX_SW_DONE_INT				(1 << 0)
- 
 
 844 
#define 	AUX_SW_DONE_ACK				(1 << 1)
- 
 
 845 
#define 	AUX_SW_DONE_MASK			(1 << 2)
- 
 
 846 
#define 	AUX_SW_LS_DONE_INT			(1 << 4)
- 
 
 847 
#define 	AUX_SW_LS_DONE_MASK			(1 << 6)
- 
 
 848 
#define AUX_SW_STATUS					0x6210
- 
 
 849 
#define 	AUX_SW_DONE				(1 << 0)
- 
 
 850 
#define 	AUX_SW_REQ				(1 << 1)
- 
 
 851 
#define 	AUX_SW_RX_TIMEOUT_STATE(x)		(((x) & 0x7) << 4)
- 
 
 852 
#define 	AUX_SW_RX_TIMEOUT			(1 << 7)
- 
 
 853 
#define 	AUX_SW_RX_OVERFLOW			(1 << 8)
- 
 
 854 
#define 	AUX_SW_RX_HPD_DISCON			(1 << 9)
- 
 
 855 
#define 	AUX_SW_RX_PARTIAL_BYTE			(1 << 10)
- 
 
 856 
#define 	AUX_SW_NON_AUX_MODE			(1 << 11)
- 
 
 857 
#define 	AUX_SW_RX_MIN_COUNT_VIOL		(1 << 12)
- 
 
 858 
#define 	AUX_SW_RX_INVALID_STOP			(1 << 14)
- 
 
 859 
#define 	AUX_SW_RX_SYNC_INVALID_L		(1 << 17)
- 
 
 860 
#define 	AUX_SW_RX_SYNC_INVALID_H		(1 << 18)
- 
 
 861 
#define 	AUX_SW_RX_INVALID_START			(1 << 19)
- 
 
 862 
#define 	AUX_SW_RX_RECV_NO_DET			(1 << 20)
- 
 
 863 
#define 	AUX_SW_RX_RECV_INVALID_H		(1 << 22)
- 
 
 864 
#define 	AUX_SW_RX_RECV_INVALID_V		(1 << 23)
- 
 
 865 
 
- 
 
 866 
#define AUX_SW_DATA					0x6218
- 
 
 867 
#define AUX_SW_DATA_RW					(1 << 0)
- 
 
 868 
#define AUX_SW_DATA_MASK(x)				(((x) & 0xff) << 8)
- 
 
 869 
#define AUX_SW_DATA_INDEX(x)				(((x) & 0x1f) << 16)
813 
#define MC_SEQ_PMG_CMD_MRS2_LP                          0x2b60
 870 
#define AUX_SW_AUTOINCREMENT_DISABLE			(1 << 31)
814 
 
 871 
 
815 
#define	LB_SYNC_RESET_SEL				0x6b28
 872 
#define	LB_SYNC_RESET_SEL				0x6b28
Line 816... Line 873...
816 
#define		LB_SYNC_RESET_SEL_MASK			(3 << 0)
 873 
#define		LB_SYNC_RESET_SEL_MASK			(3 << 0)
Line 1080... Line 1137...
1080 
#define UVD_UDEC_ADDR_CONFIG				0xEF4C
 1137 
#define UVD_UDEC_ADDR_CONFIG				0xEF4C
1081 
#define UVD_UDEC_DB_ADDR_CONFIG				0xEF50
 1138 
#define UVD_UDEC_DB_ADDR_CONFIG				0xEF50
1082 
#define UVD_UDEC_DBW_ADDR_CONFIG			0xEF54
 1139 
#define UVD_UDEC_DBW_ADDR_CONFIG			0xEF54
1083 
#define UVD_RBC_RB_RPTR					0xF690
 1140 
#define UVD_RBC_RB_RPTR					0xF690
1084 
#define UVD_RBC_RB_WPTR					0xF694
 1141 
#define UVD_RBC_RB_WPTR					0xF694
- 
 
 1142 
#define UVD_STATUS					0xf6bc
Line 1085... Line 1143...
1085 
 
 1143 
 
1086 
/*
 1144 
/*
1087 
 * PM4
 1145 
 * PM4
1088 
 */
 1146 
 */
Line 1131... Line 1189...
1131 
#define	PACKET3_DRAW_INDEX_MULTI_ELEMENT		0x36
 1189 
#define	PACKET3_DRAW_INDEX_MULTI_ELEMENT		0x36
1132 
#define	PACKET3_WRITE_DATA				0x37
 1190 
#define	PACKET3_WRITE_DATA				0x37
1133 
#define	PACKET3_MEM_SEMAPHORE				0x39
 1191 
#define	PACKET3_MEM_SEMAPHORE				0x39
1134 
#define	PACKET3_MPEG_INDEX				0x3A
 1192 
#define	PACKET3_MPEG_INDEX				0x3A
1135 
#define	PACKET3_WAIT_REG_MEM				0x3C
 1193 
#define	PACKET3_WAIT_REG_MEM				0x3C
- 
 
 1194 
#define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
- 
 
 1195 
                /* 0 - always
- 
 
 1196 
		 * 1 - <
- 
 
 1197 
		 * 2 - <=
- 
 
 1198 
		 * 3 - ==
- 
 
 1199 
		 * 4 - !=
- 
 
 1200 
		 * 5 - >=
- 
 
 1201 
		 * 6 - >
- 
 
 1202 
		 */
- 
 
 1203 
#define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
- 
 
 1204 
                /* 0 - reg
- 
 
 1205 
		 * 1 - mem
- 
 
 1206 
		 */
- 
 
 1207 
#define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
- 
 
 1208 
                /* 0 - me
- 
 
 1209 
		 * 1 - pfp
- 
 
 1210 
		 */
1136 
#define	PACKET3_MEM_WRITE				0x3D
 1211 
#define	PACKET3_MEM_WRITE				0x3D
1137 
#define	PACKET3_PFP_SYNC_ME				0x42
 1212 
#define	PACKET3_PFP_SYNC_ME				0x42
1138 
#define	PACKET3_SURFACE_SYNC				0x43
 1213 
#define	PACKET3_SURFACE_SYNC				0x43
1139 
#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
 1214 
#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
1140 
#              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
 1215 
#              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
Line 1270... Line 1345...
1270 
#define DMA_PTE_PDE_PACKET(n)		((2 << 28) |			\
 1345 
#define DMA_PTE_PDE_PACKET(n)		((2 << 28) |			\
1271 
					 (1 << 26) |			\
 1346 
					 (1 << 26) |			\
1272 
					 (1 << 21) |			\
 1347 
					 (1 << 21) |			\
1273 
					 (((n) & 0xFFFFF) << 0))
 1348 
					 (((n) & 0xFFFFF) << 0))
Line -... Line 1349...
- 
 
 1349 
 
- 
 
 1350 
#define DMA_SRBM_POLL_PACKET		((9 << 28) |			\
- 
 
 1351 
					 (1 << 27) |			\
- 
 
 1352 
					 (1 << 26))
- 
 
 1353 
 
- 
 
 1354 
#define DMA_SRBM_READ_PACKET		((9 << 28) |			\
- 
 
 1355 
					 (1 << 27))
1274 
 
 1356 
 
1275 
/* async DMA Packet types */
 1357 
/* async DMA Packet types */
1276 
#define	DMA_PACKET_WRITE				  0x2
 1358 
#define	DMA_PACKET_WRITE				  0x2
1277 
#define	DMA_PACKET_COPY					  0x3
 1359 
#define	DMA_PACKET_COPY					  0x3
1278 
#define	DMA_PACKET_INDIRECT_BUFFER			  0x4
 1360 
#define	DMA_PACKET_INDIRECT_BUFFER			  0x4