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Line 48... Line 48...
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#define	SRBM_GFX_CNTL				        0x0E44
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#define	SRBM_GFX_CNTL				        0x0E44
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#define		RINGID(x)					(((x) & 0x3) << 0)
 49 
#define		RINGID(x)					(((x) & 0x3) << 0)
50 
#define		VMID(x)						(((x) & 0x7) << 0)
 50 
#define		VMID(x)						(((x) & 0x7) << 0)
51 
#define	SRBM_STATUS				        0x0E50
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#define	SRBM_STATUS				        0x0E50
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 52 
 
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#define	SRBM_SOFT_RESET				        0x0E60
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#define		SOFT_RESET_BIF				(1 << 1)
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#define		SOFT_RESET_CG				(1 << 2)
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#define		SOFT_RESET_DC				(1 << 5)
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 57 
#define		SOFT_RESET_DMA1				(1 << 6)
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 58 
#define		SOFT_RESET_GRBM				(1 << 8)
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#define		SOFT_RESET_HDP				(1 << 9)
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#define		SOFT_RESET_IH				(1 << 10)
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#define		SOFT_RESET_MC				(1 << 11)
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#define		SOFT_RESET_RLC				(1 << 13)
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#define		SOFT_RESET_ROM				(1 << 14)
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#define		SOFT_RESET_SEM				(1 << 15)
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#define		SOFT_RESET_VMC				(1 << 17)
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#define		SOFT_RESET_DMA				(1 << 20)
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#define		SOFT_RESET_TST				(1 << 21)
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 68 
#define		SOFT_RESET_REGBB		       	(1 << 22)
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#define		SOFT_RESET_ORB				(1 << 23)
52 
 
 70 
 
53 
#define VM_CONTEXT0_REQUEST_RESPONSE			0x1470
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#define VM_CONTEXT0_REQUEST_RESPONSE			0x1470
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#define		REQUEST_TYPE(x)					(((x) & 0xf) << 0)
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#define		REQUEST_TYPE(x)					(((x) & 0xf) << 0)
55 
#define		RESPONSE_TYPE_MASK				0x000000F0
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#define		RESPONSE_TYPE_MASK				0x000000F0
56 
#define		RESPONSE_TYPE_SHIFT				4
 74 
#define		RESPONSE_TYPE_SHIFT				4
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78 
#define	VM_L2_STATUS					0x140C
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#define	VM_L2_STATUS					0x140C
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#define		L2_BUSY						(1 << 0)
 97 
#define		L2_BUSY						(1 << 0)
80 
#define VM_CONTEXT0_CNTL				0x1410
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#define VM_CONTEXT0_CNTL				0x1410
81 
#define		ENABLE_CONTEXT					(1 << 0)
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#define		ENABLE_CONTEXT					(1 << 0)
82 
#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
 100 
#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
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 101 
#define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 3)
83 
#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
 102 
#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
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 103 
#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 << 6)
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 104 
#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 << 7)
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#define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 9)
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 106 
#define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 10)
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#define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 12)
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 108 
#define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 13)
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#define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 15)
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#define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 16)
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#define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 18)
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 112 
#define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 19)
84 
#define VM_CONTEXT1_CNTL				0x1414
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#define VM_CONTEXT1_CNTL				0x1414
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#define VM_CONTEXT0_CNTL2				0x1430
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#define VM_CONTEXT0_CNTL2				0x1430
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#define VM_CONTEXT1_CNTL2				0x1434
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#define VM_CONTEXT1_CNTL2				0x1434
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#define VM_INVALIDATE_REQUEST				0x1478
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#define VM_INVALIDATE_REQUEST				0x1478
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#define VM_INVALIDATE_RESPONSE				0x147c
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#define VM_INVALIDATE_RESPONSE				0x147c
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586 
#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
 615 
#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
587 
#define	PACKET3_SET_RESOURCE_INDIRECT			0x74
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#define	PACKET3_SET_RESOURCE_INDIRECT			0x74
588 
#define	PACKET3_SET_APPEND_CNT			        0x75
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#define	PACKET3_SET_APPEND_CNT			        0x75
589 
#define	PACKET3_ME_WRITE				0x7A
 618 
#define	PACKET3_ME_WRITE				0x7A
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 619 
 
- 
 
 620 
/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
- 
 
 621 
#define DMA0_REGISTER_OFFSET                              0x0 /* not a register */
- 
 
 622 
#define DMA1_REGISTER_OFFSET                              0x800 /* not a register */
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 623 
 
- 
 
 624 
#define DMA_RB_CNTL                                       0xd000
- 
 
 625 
#       define DMA_RB_ENABLE                              (1 << 0)
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 626 
#       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */
- 
 
 627 
#       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */
- 
 
 628 
#       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)
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 629 
#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */
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 630 
#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */
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 631 
#define DMA_RB_BASE                                       0xd004
- 
 
 632 
#define DMA_RB_RPTR                                       0xd008
- 
 
 633 
#define DMA_RB_WPTR                                       0xd00c
- 
 
 634 
 
- 
 
 635 
#define DMA_RB_RPTR_ADDR_HI                               0xd01c
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 636 
#define DMA_RB_RPTR_ADDR_LO                               0xd020
- 
 
 637 
 
- 
 
 638 
#define DMA_IB_CNTL                                       0xd024
- 
 
 639 
#       define DMA_IB_ENABLE                              (1 << 0)
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 640 
#       define DMA_IB_SWAP_ENABLE                         (1 << 4)
- 
 
 641 
#       define CMD_VMID_FORCE                             (1 << 31)
- 
 
 642 
#define DMA_IB_RPTR                                       0xd028
- 
 
 643 
#define DMA_CNTL                                          0xd02c
- 
 
 644 
#       define TRAP_ENABLE                                (1 << 0)
- 
 
 645 
#       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)
- 
 
 646 
#       define SEM_WAIT_INT_ENABLE                        (1 << 2)
- 
 
 647 
#       define DATA_SWAP_ENABLE                           (1 << 3)
- 
 
 648 
#       define FENCE_SWAP_ENABLE                          (1 << 4)
- 
 
 649 
#       define CTXEMPTY_INT_ENABLE                        (1 << 28)
- 
 
 650 
#define DMA_STATUS_REG                                    0xd034
- 
 
 651 
#       define DMA_IDLE                                   (1 << 0)
- 
 
 652 
#define DMA_SEM_INCOMPLETE_TIMER_CNTL                     0xd044
- 
 
 653 
#define DMA_SEM_WAIT_FAIL_TIMER_CNTL                      0xd048
- 
 
 654 
#define DMA_TILING_CONFIG  				  0xd0b8
- 
 
 655 
#define DMA_MODE                                          0xd0bc
- 
 
 656 
 
- 
 
 657 
#define DMA_PACKET(cmd, t, s, n)	((((cmd) & 0xF) << 28) |	\
- 
 
 658 
					 (((t) & 0x1) << 23) |		\
- 
 
 659 
					 (((s) & 0x1) << 22) |		\
- 
 
 660 
					 (((n) & 0xFFFFF) << 0))
- 
 
 661 
 
- 
 
 662 
#define DMA_IB_PACKET(cmd, vmid, n)	((((cmd) & 0xF) << 28) |	\
- 
 
 663 
					 (((vmid) & 0xF) << 20) |	\
590 
 
 664 
					 (((n) & 0xFFFFF) << 0))
- 
 
 665 
 
- 
 
 666 
/* async DMA Packet types */
- 
 
 667 
#define	DMA_PACKET_WRITE				  0x2
- 
 
 668 
#define	DMA_PACKET_COPY					  0x3
- 
 
 669 
#define	DMA_PACKET_INDIRECT_BUFFER			  0x4
- 
 
 670 
#define	DMA_PACKET_SEMAPHORE				  0x5
- 
 
 671 
#define	DMA_PACKET_FENCE				  0x6
- 
 
 672 
#define	DMA_PACKET_TRAP					  0x7
- 
 
 673 
#define	DMA_PACKET_SRBM_WRITE				  0x9
- 
 
 674 
#define	DMA_PACKET_CONSTANT_FILL			  0xd
Line -... Line 675...
- 
 
 675 
#define	DMA_PACKET_NOP					  0xf