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Rev 5139 Rev 5271
Line 121... Line 121...
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 */
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 */
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void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
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void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
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				struct radeon_ib *ib)
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				struct radeon_ib *ib)
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{
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{
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	struct radeon_ring *ring = &rdev->ring[ib->ring];
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	struct radeon_ring *ring = &rdev->ring[ib->ring];
- 
 
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	unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
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 127 
 
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	if (rdev->wb.enabled) {
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	if (rdev->wb.enabled) {
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		u32 next_rptr = ring->wptr + 4;
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		u32 next_rptr = ring->wptr + 4;
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		while ((next_rptr & 7) != 5)
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		while ((next_rptr & 7) != 5)
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	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
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	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
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	 * Pad as necessary with NOPs.
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	 * Pad as necessary with NOPs.
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	 */
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	 */
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	while ((ring->wptr & 7) != 5)
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	while ((ring->wptr & 7) != 5)
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		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
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		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
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	radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
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	radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0));
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	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
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	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
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	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
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	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
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{
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{
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	while (ib->length_dw & 0x7)
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	while (ib->length_dw & 0x7)
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		ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
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		ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
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}
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}
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- 
 
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void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
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void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
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			 unsigned vm_id, uint64_t pd_addr)
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{
 - 
 
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	struct radeon_ring *ring = &rdev->ring[ridx];
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	if (vm == NULL)
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		return;
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{
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	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
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	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
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	radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
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	radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2));
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	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
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	radeon_ring_write(ring, pd_addr >> 12);
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	/* flush hdp cache */
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	/* flush hdp cache */
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	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
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	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
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	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
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	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
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	radeon_ring_write(ring, 1);
 460 
	radeon_ring_write(ring, 1);
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 461 
 
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	/* bits 0-7 are the VM contexts0-7 */
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	/* bits 0-7 are the VM contexts0-7 */
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	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
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	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));