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| Rev 3764 | Rev 5078 | ||
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
21 | * |
| 22 | * Authors: Alex Deucher |
22 | * Authors: Alex Deucher |
| 23 | */ |
23 | */ |
| 24 | #include |
24 | #include |
| 25 | //#include |
- | |
| 26 | #include |
25 | #include |
| 27 | #include |
26 | #include |
| 28 | #include |
27 | #include |
| 29 | #include "radeon.h" |
28 | #include "radeon.h" |
| 30 | #include "radeon_asic.h" |
29 | #include "radeon_asic.h" |
| 31 | #include |
30 | #include |
| 32 | #include "nid.h" |
31 | #include "nid.h" |
| 33 | #include "atom.h" |
32 | #include "atom.h" |
| 34 | #include "ni_reg.h" |
33 | #include "ni_reg.h" |
| 35 | #include "cayman_blit_shaders.h" |
34 | #include "cayman_blit_shaders.h" |
| - | 35 | #include "radeon_ucode.h" |
|
| - | 36 | #include "clearstate_cayman.h" |
|
| - | 37 | ||
| - | 38 | static const u32 tn_rlc_save_restore_register_list[] = |
|
| - | 39 | { |
|
| - | 40 | 0x98fc, |
|
| - | 41 | 0x98f0, |
|
| - | 42 | 0x9834, |
|
| - | 43 | 0x9838, |
|
| - | 44 | 0x9870, |
|
| - | 45 | 0x9874, |
|
| - | 46 | 0x8a14, |
|
| - | 47 | 0x8b24, |
|
| - | 48 | 0x8bcc, |
|
| - | 49 | 0x8b10, |
|
| - | 50 | 0x8c30, |
|
| - | 51 | 0x8d00, |
|
| - | 52 | 0x8d04, |
|
| - | 53 | 0x8c00, |
|
| - | 54 | 0x8c04, |
|
| - | 55 | 0x8c10, |
|
| - | 56 | 0x8c14, |
|
| - | 57 | 0x8d8c, |
|
| - | 58 | 0x8cf0, |
|
| - | 59 | 0x8e38, |
|
| - | 60 | 0x9508, |
|
| - | 61 | 0x9688, |
|
| - | 62 | 0x9608, |
|
| - | 63 | 0x960c, |
|
| - | 64 | 0x9610, |
|
| - | 65 | 0x9614, |
|
| - | 66 | 0x88c4, |
|
| - | 67 | 0x8978, |
|
| - | 68 | 0x88d4, |
|
| - | 69 | 0x900c, |
|
| - | 70 | 0x9100, |
|
| - | 71 | 0x913c, |
|
| - | 72 | 0x90e8, |
|
| - | 73 | 0x9354, |
|
| - | 74 | 0xa008, |
|
| - | 75 | 0x98f8, |
|
| - | 76 | 0x9148, |
|
| - | 77 | 0x914c, |
|
| - | 78 | 0x3f94, |
|
| - | 79 | 0x98f4, |
|
| - | 80 | 0x9b7c, |
|
| - | 81 | 0x3f8c, |
|
| - | 82 | 0x8950, |
|
| - | 83 | 0x8954, |
|
| - | 84 | 0x8a18, |
|
| - | 85 | 0x8b28, |
|
| - | 86 | 0x9144, |
|
| - | 87 | 0x3f90, |
|
| - | 88 | 0x915c, |
|
| - | 89 | 0x9160, |
|
| - | 90 | 0x9178, |
|
| - | 91 | 0x917c, |
|
| - | 92 | 0x9180, |
|
| - | 93 | 0x918c, |
|
| - | 94 | 0x9190, |
|
| - | 95 | 0x9194, |
|
| - | 96 | 0x9198, |
|
| - | 97 | 0x919c, |
|
| - | 98 | 0x91a8, |
|
| - | 99 | 0x91ac, |
|
| - | 100 | 0x91b0, |
|
| - | 101 | 0x91b4, |
|
| - | 102 | 0x91b8, |
|
| - | 103 | 0x91c4, |
|
| - | 104 | 0x91c8, |
|
| - | 105 | 0x91cc, |
|
| - | 106 | 0x91d0, |
|
| - | 107 | 0x91d4, |
|
| - | 108 | 0x91e0, |
|
| - | 109 | 0x91e4, |
|
| - | 110 | 0x91ec, |
|
| - | 111 | 0x91f0, |
|
| - | 112 | 0x91f4, |
|
| - | 113 | 0x9200, |
|
| - | 114 | 0x9204, |
|
| - | 115 | 0x929c, |
|
| - | 116 | 0x8030, |
|
| - | 117 | 0x9150, |
|
| - | 118 | 0x9a60, |
|
| - | 119 | 0x920c, |
|
| - | 120 | 0x9210, |
|
| - | 121 | 0x9228, |
|
| - | 122 | 0x922c, |
|
| - | 123 | 0x9244, |
|
| - | 124 | 0x9248, |
|
| - | 125 | 0x91e8, |
|
| - | 126 | 0x9294, |
|
| - | 127 | 0x9208, |
|
| - | 128 | 0x9224, |
|
| - | 129 | 0x9240, |
|
| - | 130 | 0x9220, |
|
| - | 131 | 0x923c, |
|
| - | 132 | 0x9258, |
|
| - | 133 | 0x9744, |
|
| - | 134 | 0xa200, |
|
| - | 135 | 0xa204, |
|
| - | 136 | 0xa208, |
|
| - | 137 | 0xa20c, |
|
| - | 138 | 0x8d58, |
|
| - | 139 | 0x9030, |
|
| - | 140 | 0x9034, |
|
| - | 141 | 0x9038, |
|
| - | 142 | 0x903c, |
|
| - | 143 | 0x9040, |
|
| - | 144 | 0x9654, |
|
| - | 145 | 0x897c, |
|
| - | 146 | 0xa210, |
|
| - | 147 | 0xa214, |
|
| - | 148 | 0x9868, |
|
| - | 149 | 0xa02c, |
|
| - | 150 | 0x9664, |
|
| - | 151 | 0x9698, |
|
| - | 152 | 0x949c, |
|
| - | 153 | 0x8e10, |
|
| - | 154 | 0x8e18, |
|
| - | 155 | 0x8c50, |
|
| - | 156 | 0x8c58, |
|
| - | 157 | 0x8c60, |
|
| - | 158 | 0x8c68, |
|
| - | 159 | 0x89b4, |
|
| - | 160 | 0x9830, |
|
| - | 161 | 0x802c, |
|
| - | 162 | }; |
|
| Line 36... | Line 163... | ||
| 36 | 163 | ||
| 37 | extern bool evergreen_is_display_hung(struct radeon_device *rdev); |
164 | extern bool evergreen_is_display_hung(struct radeon_device *rdev); |
| 38 | extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); |
165 | extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); |
| 39 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
166 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
| Line 42... | Line 169... | ||
| 42 | extern void evergreen_mc_program(struct radeon_device *rdev); |
169 | extern void evergreen_mc_program(struct radeon_device *rdev); |
| 43 | extern void evergreen_irq_suspend(struct radeon_device *rdev); |
170 | extern void evergreen_irq_suspend(struct radeon_device *rdev); |
| 44 | extern int evergreen_mc_init(struct radeon_device *rdev); |
171 | extern int evergreen_mc_init(struct radeon_device *rdev); |
| 45 | extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); |
172 | extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); |
| 46 | extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); |
173 | extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); |
| 47 | extern void si_rlc_fini(struct radeon_device *rdev); |
174 | extern void evergreen_program_aspm(struct radeon_device *rdev); |
| 48 | extern int si_rlc_init(struct radeon_device *rdev); |
175 | extern void sumo_rlc_fini(struct radeon_device *rdev); |
| 49 | - | ||
| 50 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
176 | extern int sumo_rlc_init(struct radeon_device *rdev); |
| 51 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
177 | extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev); |
| 52 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
- | |
| 53 | #define BTC_MC_UCODE_SIZE 6024 |
- | |
| 54 | - | ||
| 55 | #define CAYMAN_PFP_UCODE_SIZE 2176 |
- | |
| 56 | #define CAYMAN_PM4_UCODE_SIZE 2176 |
- | |
| 57 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
- | |
| 58 | #define CAYMAN_MC_UCODE_SIZE 6037 |
- | |
| 59 | - | ||
| 60 | #define ARUBA_RLC_UCODE_SIZE 1536 |
- | |
| Line 61... | Line 178... | ||
| 61 | 178 | ||
| 62 | /* Firmware Names */ |
179 | /* Firmware Names */ |
| 63 | MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); |
180 | MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); |
| 64 | MODULE_FIRMWARE("radeon/BARTS_me.bin"); |
181 | MODULE_FIRMWARE("radeon/BARTS_me.bin"); |
| - | 182 | MODULE_FIRMWARE("radeon/BARTS_mc.bin"); |
|
| 65 | MODULE_FIRMWARE("radeon/BARTS_mc.bin"); |
183 | MODULE_FIRMWARE("radeon/BARTS_smc.bin"); |
| 66 | MODULE_FIRMWARE("radeon/BTC_rlc.bin"); |
184 | MODULE_FIRMWARE("radeon/BTC_rlc.bin"); |
| 67 | MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); |
185 | MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); |
| 68 | MODULE_FIRMWARE("radeon/TURKS_me.bin"); |
186 | MODULE_FIRMWARE("radeon/TURKS_me.bin"); |
| - | 187 | MODULE_FIRMWARE("radeon/TURKS_mc.bin"); |
|
| 69 | MODULE_FIRMWARE("radeon/TURKS_mc.bin"); |
188 | MODULE_FIRMWARE("radeon/TURKS_smc.bin"); |
| 70 | MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); |
189 | MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); |
| 71 | MODULE_FIRMWARE("radeon/CAICOS_me.bin"); |
190 | MODULE_FIRMWARE("radeon/CAICOS_me.bin"); |
| - | 191 | MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); |
|
| 72 | MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); |
192 | MODULE_FIRMWARE("radeon/CAICOS_smc.bin"); |
| 73 | MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); |
193 | MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); |
| 74 | MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); |
194 | MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); |
| 75 | MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); |
195 | MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); |
| - | 196 | MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); |
|
| 76 | MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); |
197 | MODULE_FIRMWARE("radeon/CAYMAN_smc.bin"); |
| 77 | MODULE_FIRMWARE("radeon/ARUBA_pfp.bin"); |
198 | MODULE_FIRMWARE("radeon/ARUBA_pfp.bin"); |
| 78 | MODULE_FIRMWARE("radeon/ARUBA_me.bin"); |
199 | MODULE_FIRMWARE("radeon/ARUBA_me.bin"); |
| Line 560... | Line 681... | ||
| 560 | return 0; |
681 | return 0; |
| 561 | } |
682 | } |
| Line 562... | Line 683... | ||
| 562 | 683 | ||
| 563 | int ni_init_microcode(struct radeon_device *rdev) |
684 | int ni_init_microcode(struct radeon_device *rdev) |
| 564 | { |
- | |
| 565 | struct platform_device *pdev; |
685 | { |
| 566 | const char *chip_name; |
686 | const char *chip_name; |
| 567 | const char *rlc_chip_name; |
687 | const char *rlc_chip_name; |
| - | 688 | size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; |
|
| 568 | size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; |
689 | size_t smc_req_size = 0; |
| 569 | char fw_name[30]; |
690 | char fw_name[30]; |
| Line 570... | Line 691... | ||
| 570 | int err; |
691 | int err; |
| Line 571... | Line -... | ||
| 571 | - | ||
| 572 | DRM_DEBUG("\n"); |
- | |
| 573 | - | ||
| 574 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
- | |
| 575 | err = IS_ERR(pdev); |
- | |
| 576 | if (err) { |
- | |
| 577 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
- | |
| 578 | return -EINVAL; |
692 | |
| 579 | } |
693 | DRM_DEBUG("\n"); |
| 580 | 694 | ||
| 581 | switch (rdev->family) { |
695 | switch (rdev->family) { |
| 582 | case CHIP_BARTS: |
696 | case CHIP_BARTS: |
| 583 | chip_name = "BARTS"; |
697 | chip_name = "BARTS"; |
| 584 | rlc_chip_name = "BTC"; |
698 | rlc_chip_name = "BTC"; |
| 585 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
699 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
| - | 700 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
|
| 586 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
701 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
| 587 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
702 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
| 588 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
703 | smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4); |
| 589 | break; |
704 | break; |
| 590 | case CHIP_TURKS: |
705 | case CHIP_TURKS: |
| 591 | chip_name = "TURKS"; |
706 | chip_name = "TURKS"; |
| 592 | rlc_chip_name = "BTC"; |
707 | rlc_chip_name = "BTC"; |
| 593 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
708 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
| - | 709 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
|
| 594 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
710 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
| 595 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
711 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
| 596 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
712 | smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4); |
| 597 | break; |
713 | break; |
| 598 | case CHIP_CAICOS: |
714 | case CHIP_CAICOS: |
| 599 | chip_name = "CAICOS"; |
715 | chip_name = "CAICOS"; |
| 600 | rlc_chip_name = "BTC"; |
716 | rlc_chip_name = "BTC"; |
| 601 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
717 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
| - | 718 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
|
| 602 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
719 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
| 603 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
720 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
| 604 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
721 | smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4); |
| 605 | break; |
722 | break; |
| 606 | case CHIP_CAYMAN: |
723 | case CHIP_CAYMAN: |
| 607 | chip_name = "CAYMAN"; |
724 | chip_name = "CAYMAN"; |
| 608 | rlc_chip_name = "CAYMAN"; |
725 | rlc_chip_name = "CAYMAN"; |
| 609 | pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; |
726 | pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; |
| - | 727 | me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; |
|
| 610 | me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; |
728 | rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; |
| 611 | rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; |
729 | mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; |
| 612 | mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; |
730 | smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4); |
| 613 | break; |
731 | break; |
| 614 | case CHIP_ARUBA: |
732 | case CHIP_ARUBA: |
| Line 624... | Line 742... | ||
| 624 | } |
742 | } |
| Line 625... | Line 743... | ||
| 625 | 743 | ||
| Line 626... | Line 744... | ||
| 626 | DRM_INFO("Loading %s Microcode\n", chip_name); |
744 | DRM_INFO("Loading %s Microcode\n", chip_name); |
| 627 | 745 | ||
| 628 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); |
746 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); |
| 629 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); |
747 | err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); |
| 630 | if (err) |
748 | if (err) |
| 631 | goto out; |
749 | goto out; |
| 632 | if (rdev->pfp_fw->size != pfp_req_size) { |
750 | if (rdev->pfp_fw->size != pfp_req_size) { |
| Line 636... | Line 754... | ||
| 636 | err = -EINVAL; |
754 | err = -EINVAL; |
| 637 | goto out; |
755 | goto out; |
| 638 | } |
756 | } |
| Line 639... | Line 757... | ||
| 639 | 757 | ||
| 640 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); |
758 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); |
| 641 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
759 | err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); |
| 642 | if (err) |
760 | if (err) |
| 643 | goto out; |
761 | goto out; |
| 644 | if (rdev->me_fw->size != me_req_size) { |
762 | if (rdev->me_fw->size != me_req_size) { |
| 645 | printk(KERN_ERR |
763 | printk(KERN_ERR |
| 646 | "ni_cp: Bogus length %zu in firmware \"%s\"\n", |
764 | "ni_cp: Bogus length %zu in firmware \"%s\"\n", |
| 647 | rdev->me_fw->size, fw_name); |
765 | rdev->me_fw->size, fw_name); |
| 648 | err = -EINVAL; |
766 | err = -EINVAL; |
| Line 649... | Line 767... | ||
| 649 | } |
767 | } |
| 650 | 768 | ||
| 651 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); |
769 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); |
| 652 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); |
770 | err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); |
| 653 | if (err) |
771 | if (err) |
| 654 | goto out; |
772 | goto out; |
| 655 | if (rdev->rlc_fw->size != rlc_req_size) { |
773 | if (rdev->rlc_fw->size != rlc_req_size) { |
| Line 660... | Line 778... | ||
| 660 | } |
778 | } |
| Line 661... | Line 779... | ||
| 661 | 779 | ||
| 662 | /* no MC ucode on TN */ |
780 | /* no MC ucode on TN */ |
| 663 | if (!(rdev->flags & RADEON_IS_IGP)) { |
781 | if (!(rdev->flags & RADEON_IS_IGP)) { |
| 664 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); |
782 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); |
| 665 | err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); |
783 | err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); |
| 666 | if (err) |
784 | if (err) |
| 667 | goto out; |
785 | goto out; |
| 668 | if (rdev->mc_fw->size != mc_req_size) { |
786 | if (rdev->mc_fw->size != mc_req_size) { |
| 669 | printk(KERN_ERR |
787 | printk(KERN_ERR |
| 670 | "ni_mc: Bogus length %zu in firmware \"%s\"\n", |
788 | "ni_mc: Bogus length %zu in firmware \"%s\"\n", |
| 671 | rdev->mc_fw->size, fw_name); |
789 | rdev->mc_fw->size, fw_name); |
| 672 | err = -EINVAL; |
790 | err = -EINVAL; |
| 673 | } |
791 | } |
| 674 | } |
- | |
| 675 | out: |
- | |
| Line -... | Line 792... | ||
| - | 792 | } |
|
| - | 793 | ||
| - | 794 | if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { |
|
| - | 795 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); |
|
| - | 796 | err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); |
|
| - | 797 | if (err) { |
|
| - | 798 | printk(KERN_ERR |
|
| - | 799 | "smc: error loading firmware \"%s\"\n", |
|
| - | 800 | fw_name); |
|
| - | 801 | release_firmware(rdev->smc_fw); |
|
| - | 802 | rdev->smc_fw = NULL; |
|
| - | 803 | err = 0; |
|
| - | 804 | } else if (rdev->smc_fw->size != smc_req_size) { |
|
| - | 805 | printk(KERN_ERR |
|
| - | 806 | "ni_mc: Bogus length %zu in firmware \"%s\"\n", |
|
| - | 807 | rdev->mc_fw->size, fw_name); |
|
| - | 808 | err = -EINVAL; |
|
| - | 809 | } |
|
| - | 810 | } |
|
| 676 | platform_device_unregister(pdev); |
811 | |
| 677 | 812 | out: |
|
| 678 | if (err) { |
813 | if (err) { |
| 679 | if (err != -EINVAL) |
814 | if (err != -EINVAL) |
| 680 | printk(KERN_ERR |
815 | printk(KERN_ERR |
| Line 690... | Line 825... | ||
| 690 | rdev->mc_fw = NULL; |
825 | rdev->mc_fw = NULL; |
| 691 | } |
826 | } |
| 692 | return err; |
827 | return err; |
| 693 | } |
828 | } |
| Line -... | Line 829... | ||
| - | 829 | ||
| - | 830 | int tn_get_temp(struct radeon_device *rdev) |
|
| - | 831 | { |
|
| - | 832 | u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; |
|
| - | 833 | int actual_temp = (temp / 8) - 49; |
|
| - | 834 | ||
| - | 835 | return actual_temp * 1000; |
|
| - | 836 | } |
|
| 694 | 837 | ||
| 695 | /* |
838 | /* |
| 696 | * Core functions |
839 | * Core functions |
| 697 | */ |
840 | */ |
| 698 | static void cayman_gpu_init(struct radeon_device *rdev) |
841 | static void cayman_gpu_init(struct radeon_device *rdev) |
| Line 751... | Line 894... | ||
| 751 | (rdev->pdev->device == 0x9917) || |
894 | (rdev->pdev->device == 0x9917) || |
| 752 | (rdev->pdev->device == 0x9999) || |
895 | (rdev->pdev->device == 0x9999) || |
| 753 | (rdev->pdev->device == 0x999C)) { |
896 | (rdev->pdev->device == 0x999C)) { |
| 754 | rdev->config.cayman.max_simds_per_se = 6; |
897 | rdev->config.cayman.max_simds_per_se = 6; |
| 755 | rdev->config.cayman.max_backends_per_se = 2; |
898 | rdev->config.cayman.max_backends_per_se = 2; |
| - | 899 | rdev->config.cayman.max_hw_contexts = 8; |
|
| - | 900 | rdev->config.cayman.sx_max_export_size = 256; |
|
| - | 901 | rdev->config.cayman.sx_max_export_pos_size = 64; |
|
| - | 902 | rdev->config.cayman.sx_max_export_smx_size = 192; |
|
| 756 | } else if ((rdev->pdev->device == 0x9903) || |
903 | } else if ((rdev->pdev->device == 0x9903) || |
| 757 | (rdev->pdev->device == 0x9904) || |
904 | (rdev->pdev->device == 0x9904) || |
| 758 | (rdev->pdev->device == 0x990A) || |
905 | (rdev->pdev->device == 0x990A) || |
| 759 | (rdev->pdev->device == 0x990D) || |
906 | (rdev->pdev->device == 0x990D) || |
| 760 | (rdev->pdev->device == 0x990E) || |
907 | (rdev->pdev->device == 0x990E) || |
| 761 | (rdev->pdev->device == 0x9913) || |
908 | (rdev->pdev->device == 0x9913) || |
| 762 | (rdev->pdev->device == 0x9918) || |
909 | (rdev->pdev->device == 0x9918) || |
| 763 | (rdev->pdev->device == 0x999D)) { |
910 | (rdev->pdev->device == 0x999D)) { |
| 764 | rdev->config.cayman.max_simds_per_se = 4; |
911 | rdev->config.cayman.max_simds_per_se = 4; |
| 765 | rdev->config.cayman.max_backends_per_se = 2; |
912 | rdev->config.cayman.max_backends_per_se = 2; |
| - | 913 | rdev->config.cayman.max_hw_contexts = 8; |
|
| - | 914 | rdev->config.cayman.sx_max_export_size = 256; |
|
| - | 915 | rdev->config.cayman.sx_max_export_pos_size = 64; |
|
| - | 916 | rdev->config.cayman.sx_max_export_smx_size = 192; |
|
| 766 | } else if ((rdev->pdev->device == 0x9919) || |
917 | } else if ((rdev->pdev->device == 0x9919) || |
| 767 | (rdev->pdev->device == 0x9990) || |
918 | (rdev->pdev->device == 0x9990) || |
| 768 | (rdev->pdev->device == 0x9991) || |
919 | (rdev->pdev->device == 0x9991) || |
| 769 | (rdev->pdev->device == 0x9994) || |
920 | (rdev->pdev->device == 0x9994) || |
| 770 | (rdev->pdev->device == 0x9995) || |
921 | (rdev->pdev->device == 0x9995) || |
| 771 | (rdev->pdev->device == 0x9996) || |
922 | (rdev->pdev->device == 0x9996) || |
| 772 | (rdev->pdev->device == 0x999A) || |
923 | (rdev->pdev->device == 0x999A) || |
| 773 | (rdev->pdev->device == 0x99A0)) { |
924 | (rdev->pdev->device == 0x99A0)) { |
| 774 | rdev->config.cayman.max_simds_per_se = 3; |
925 | rdev->config.cayman.max_simds_per_se = 3; |
| 775 | rdev->config.cayman.max_backends_per_se = 1; |
926 | rdev->config.cayman.max_backends_per_se = 1; |
| - | 927 | rdev->config.cayman.max_hw_contexts = 4; |
|
| - | 928 | rdev->config.cayman.sx_max_export_size = 128; |
|
| - | 929 | rdev->config.cayman.sx_max_export_pos_size = 32; |
|
| - | 930 | rdev->config.cayman.sx_max_export_smx_size = 96; |
|
| 776 | } else { |
931 | } else { |
| 777 | rdev->config.cayman.max_simds_per_se = 2; |
932 | rdev->config.cayman.max_simds_per_se = 2; |
| 778 | rdev->config.cayman.max_backends_per_se = 1; |
933 | rdev->config.cayman.max_backends_per_se = 1; |
| - | 934 | rdev->config.cayman.max_hw_contexts = 4; |
|
| - | 935 | rdev->config.cayman.sx_max_export_size = 128; |
|
| - | 936 | rdev->config.cayman.sx_max_export_pos_size = 32; |
|
| - | 937 | rdev->config.cayman.sx_max_export_smx_size = 96; |
|
| 779 | } |
938 | } |
| 780 | rdev->config.cayman.max_texture_channel_caches = 2; |
939 | rdev->config.cayman.max_texture_channel_caches = 2; |
| 781 | rdev->config.cayman.max_gprs = 256; |
940 | rdev->config.cayman.max_gprs = 256; |
| 782 | rdev->config.cayman.max_threads = 256; |
941 | rdev->config.cayman.max_threads = 256; |
| 783 | rdev->config.cayman.max_gs_threads = 32; |
942 | rdev->config.cayman.max_gs_threads = 32; |
| 784 | rdev->config.cayman.max_stack_entries = 512; |
943 | rdev->config.cayman.max_stack_entries = 512; |
| 785 | rdev->config.cayman.sx_num_of_sets = 8; |
944 | rdev->config.cayman.sx_num_of_sets = 8; |
| 786 | rdev->config.cayman.sx_max_export_size = 256; |
- | |
| 787 | rdev->config.cayman.sx_max_export_pos_size = 64; |
- | |
| 788 | rdev->config.cayman.sx_max_export_smx_size = 192; |
- | |
| 789 | rdev->config.cayman.max_hw_contexts = 8; |
- | |
| 790 | rdev->config.cayman.sq_num_cf_insts = 2; |
945 | rdev->config.cayman.sq_num_cf_insts = 2; |
| Line 791... | Line 946... | ||
| 791 | 946 | ||
| 792 | rdev->config.cayman.sc_prim_fifo_size = 0x40; |
947 | rdev->config.cayman.sc_prim_fifo_size = 0x40; |
| 793 | rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; |
948 | rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; |
| Line 900... | Line 1055... | ||
| 900 | if ((disabled_rb_mask & tmp) == tmp) { |
1055 | if ((disabled_rb_mask & tmp) == tmp) { |
| 901 | for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) |
1056 | for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) |
| 902 | disabled_rb_mask &= ~(1 << i); |
1057 | disabled_rb_mask &= ~(1 << i); |
| 903 | } |
1058 | } |
| Line -... | Line 1059... | ||
| - | 1059 | ||
| - | 1060 | for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { |
|
| - | 1061 | u32 simd_disable_bitmap; |
|
| - | 1062 | ||
| - | 1063 | WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); |
|
| - | 1064 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); |
|
| - | 1065 | simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; |
|
| - | 1066 | simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; |
|
| - | 1067 | tmp <<= 16; |
|
| - | 1068 | tmp |= simd_disable_bitmap; |
|
| - | 1069 | } |
|
| - | 1070 | rdev->config.cayman.active_simds = hweight32(~tmp); |
|
| 904 | 1071 | ||
| 905 | WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
1072 | WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
| Line 906... | Line 1073... | ||
| 906 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
1073 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
| 907 | 1074 | ||
| Line 1025... | Line 1192... | ||
| 1025 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
1192 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
| Line 1026... | Line 1193... | ||
| 1026 | 1193 | ||
| Line 1027... | Line 1194... | ||
| 1027 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); |
1194 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); |
| - | 1195 | ||
| - | 1196 | udelay(50); |
|
| - | 1197 | ||
| - | 1198 | /* set clockgating golden values on TN */ |
|
| - | 1199 | if (rdev->family == CHIP_ARUBA) { |
|
| - | 1200 | tmp = RREG32_CG(CG_CGTT_LOCAL_0); |
|
| - | 1201 | tmp &= ~0x00380000; |
|
| - | 1202 | WREG32_CG(CG_CGTT_LOCAL_0, tmp); |
|
| - | 1203 | tmp = RREG32_CG(CG_CGTT_LOCAL_1); |
|
| - | 1204 | tmp &= ~0x0e000000; |
|
| 1028 | 1205 | WREG32_CG(CG_CGTT_LOCAL_1, tmp); |
|
| Line 1029... | Line 1206... | ||
| 1029 | udelay(50); |
1206 | } |
| 1030 | } |
1207 | } |
| 1031 | 1208 | ||
| Line 1050... | Line 1227... | ||
| 1050 | return -EINVAL; |
1227 | return -EINVAL; |
| 1051 | } |
1228 | } |
| 1052 | r = radeon_gart_table_vram_pin(rdev); |
1229 | r = radeon_gart_table_vram_pin(rdev); |
| 1053 | if (r) |
1230 | if (r) |
| 1054 | return r; |
1231 | return r; |
| 1055 | radeon_gart_restore(rdev); |
- | |
| 1056 | /* Setup TLB control */ |
1232 | /* Setup TLB control */ |
| 1057 | WREG32(MC_VM_MX_L1_TLB_CNTL, |
1233 | WREG32(MC_VM_MX_L1_TLB_CNTL, |
| 1058 | (0xA << 7) | |
1234 | (0xA << 7) | |
| 1059 | ENABLE_L1_TLB | |
1235 | ENABLE_L1_TLB | |
| 1060 | ENABLE_L1_FRAGMENT_PROCESSING | |
1236 | ENABLE_L1_FRAGMENT_PROCESSING | |
| 1061 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
1237 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 1062 | ENABLE_ADVANCED_DRIVER_MODEL | |
1238 | ENABLE_ADVANCED_DRIVER_MODEL | |
| 1063 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
1239 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
| 1064 | /* Setup L2 cache */ |
1240 | /* Setup L2 cache */ |
| 1065 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | |
1241 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | |
| - | 1242 | ENABLE_L2_FRAGMENT_PROCESSING | |
|
| 1066 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
1243 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 1067 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | |
1244 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | |
| 1068 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
1245 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
| 1069 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
1246 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
| 1070 | WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); |
1247 | WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); |
| 1071 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
1248 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
| - | 1249 | BANK_SELECT(6) | |
|
| 1072 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
1250 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
| 1073 | /* setup context0 */ |
1251 | /* setup context0 */ |
| 1074 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
1252 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
| 1075 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
1253 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
| 1076 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
1254 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
| Line 1091... | Line 1269... | ||
| 1091 | */ |
1269 | */ |
| 1092 | for (i = 1; i < 8; i++) { |
1270 | for (i = 1; i < 8; i++) { |
| 1093 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); |
1271 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); |
| 1094 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn); |
1272 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn); |
| 1095 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), |
1273 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), |
| 1096 | rdev->gart.table_addr >> 12); |
1274 | rdev->vm_manager.saved_table_addr[i]); |
| 1097 | } |
1275 | } |
| Line 1098... | Line 1276... | ||
| 1098 | 1276 | ||
| 1099 | /* enable context1-7 */ |
1277 | /* enable context1-7 */ |
| 1100 | WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, |
1278 | WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, |
| 1101 | (u32)(rdev->dummy_page.addr >> 12)); |
1279 | (u32)(rdev->dummy_page.addr >> 12)); |
| 1102 | WREG32(VM_CONTEXT1_CNTL2, 4); |
1280 | WREG32(VM_CONTEXT1_CNTL2, 4); |
| - | 1281 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | |
|
| 1103 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | |
1282 | PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | |
| 1104 | RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
1283 | RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
| 1105 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
1284 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
| 1106 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
1285 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
| 1107 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
1286 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
| Line 1122... | Line 1301... | ||
| 1122 | return 0; |
1301 | return 0; |
| 1123 | } |
1302 | } |
| Line 1124... | Line 1303... | ||
| 1124 | 1303 | ||
| 1125 | static void cayman_pcie_gart_disable(struct radeon_device *rdev) |
1304 | static void cayman_pcie_gart_disable(struct radeon_device *rdev) |
| - | 1305 | { |
|
| - | 1306 | unsigned i; |
|
| - | 1307 | ||
| - | 1308 | for (i = 1; i < 8; ++i) { |
|
| - | 1309 | rdev->vm_manager.saved_table_addr[i] = RREG32( |
|
| - | 1310 | VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2)); |
|
| - | 1311 | } |
|
| 1126 | { |
1312 | |
| 1127 | /* Disable all tables */ |
1313 | /* Disable all tables */ |
| 1128 | WREG32(VM_CONTEXT0_CNTL, 0); |
1314 | WREG32(VM_CONTEXT0_CNTL, 0); |
| 1129 | WREG32(VM_CONTEXT1_CNTL, 0); |
1315 | WREG32(VM_CONTEXT1_CNTL, 0); |
| 1130 | /* Setup TLB control */ |
1316 | /* Setup TLB control */ |
| Line 1157... | Line 1343... | ||
| 1157 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
1343 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
| 1158 | struct radeon_fence *fence) |
1344 | struct radeon_fence *fence) |
| 1159 | { |
1345 | { |
| 1160 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
1346 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
| 1161 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
1347 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
| - | 1348 | u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | |
|
| - | 1349 | PACKET3_SH_ACTION_ENA; |
|
| Line 1162... | Line 1350... | ||
| 1162 | 1350 | ||
| 1163 | /* flush read cache over gart for this vmid */ |
- | |
| 1164 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
- | |
| 1165 | radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); |
- | |
| 1166 | radeon_ring_write(ring, 0); |
1351 | /* flush read cache over gart for this vmid */ |
| 1167 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
1352 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 1168 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); |
1353 | radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); |
| 1169 | radeon_ring_write(ring, 0xFFFFFFFF); |
1354 | radeon_ring_write(ring, 0xFFFFFFFF); |
| 1170 | radeon_ring_write(ring, 0); |
1355 | radeon_ring_write(ring, 0); |
| 1171 | radeon_ring_write(ring, 10); /* poll interval */ |
1356 | radeon_ring_write(ring, 10); /* poll interval */ |
| 1172 | /* EVENT_WRITE_EOP - flush caches, send int */ |
1357 | /* EVENT_WRITE_EOP - flush caches, send int */ |
| 1173 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
1358 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
| 1174 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); |
1359 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); |
| 1175 | radeon_ring_write(ring, addr & 0xffffffff); |
1360 | radeon_ring_write(ring, lower_32_bits(addr)); |
| 1176 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); |
1361 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); |
| 1177 | radeon_ring_write(ring, fence->seq); |
1362 | radeon_ring_write(ring, fence->seq); |
| 1178 | radeon_ring_write(ring, 0); |
1363 | radeon_ring_write(ring, 0); |
| Line 1179... | Line 1364... | ||
| 1179 | } |
1364 | } |
| 1180 | 1365 | ||
| 1181 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
1366 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
| - | 1367 | { |
|
| - | 1368 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
|
| Line 1182... | Line 1369... | ||
| 1182 | { |
1369 | u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | |
| 1183 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
1370 | PACKET3_SH_ACTION_ENA; |
| 1184 | 1371 | ||
| Line 1203... | Line 1390... | ||
| 1203 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
1390 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
| 1204 | radeon_ring_write(ring, ib->length_dw | |
1391 | radeon_ring_write(ring, ib->length_dw | |
| 1205 | (ib->vm ? (ib->vm->id << 24) : 0)); |
1392 | (ib->vm ? (ib->vm->id << 24) : 0)); |
| Line 1206... | Line 1393... | ||
| 1206 | 1393 | ||
| 1207 | /* flush read cache over gart for this vmid */ |
- | |
| 1208 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
- | |
| 1209 | radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); |
- | |
| 1210 | radeon_ring_write(ring, ib->vm ? ib->vm->id : 0); |
1394 | /* flush read cache over gart for this vmid */ |
| 1211 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
1395 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 1212 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); |
1396 | radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); |
| 1213 | radeon_ring_write(ring, 0xFFFFFFFF); |
1397 | radeon_ring_write(ring, 0xFFFFFFFF); |
| 1214 | radeon_ring_write(ring, 0); |
1398 | radeon_ring_write(ring, 0); |
| 1215 | radeon_ring_write(ring, 10); /* poll interval */ |
- | |
| 1216 | } |
- | |
| 1217 | - | ||
| 1218 | void cayman_uvd_semaphore_emit(struct radeon_device *rdev, |
- | |
| 1219 | struct radeon_ring *ring, |
- | |
| 1220 | struct radeon_semaphore *semaphore, |
- | |
| 1221 | bool emit_wait) |
- | |
| 1222 | { |
- | |
| 1223 | uint64_t addr = semaphore->gpu_addr; |
- | |
| 1224 | - | ||
| 1225 | radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); |
- | |
| 1226 | radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); |
- | |
| 1227 | - | ||
| 1228 | radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); |
- | |
| 1229 | radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); |
- | |
| 1230 | - | ||
| 1231 | radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); |
- | |
| 1232 | radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); |
1399 | radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */ |
| Line 1233... | Line 1400... | ||
| 1233 | } |
1400 | } |
| 1234 | 1401 | ||
| 1235 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
1402 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
| 1236 | { |
1403 | { |
| 1237 | if (enable) |
1404 | if (enable) |
| - | 1405 | WREG32(CP_ME_CNTL, 0); |
|
| 1238 | WREG32(CP_ME_CNTL, 0); |
1406 | else { |
| 1239 | else { |
1407 | if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) |
| 1240 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
1408 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
| 1241 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
1409 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
| 1242 | WREG32(SCRATCH_UMSK, 0); |
1410 | WREG32(SCRATCH_UMSK, 0); |
| 1243 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
1411 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
| Line -... | Line 1412... | ||
| - | 1412 | } |
|
| - | 1413 | } |
|
| - | 1414 | ||
| - | 1415 | u32 cayman_gfx_get_rptr(struct radeon_device *rdev, |
|
| - | 1416 | struct radeon_ring *ring) |
|
| - | 1417 | { |
|
| - | 1418 | u32 rptr; |
|
| - | 1419 | ||
| - | 1420 | if (rdev->wb.enabled) |
|
| - | 1421 | rptr = rdev->wb.wb[ring->rptr_offs/4]; |
|
| - | 1422 | else { |
|
| - | 1423 | if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) |
|
| - | 1424 | rptr = RREG32(CP_RB0_RPTR); |
|
| - | 1425 | else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) |
|
| - | 1426 | rptr = RREG32(CP_RB1_RPTR); |
|
| - | 1427 | else |
|
| - | 1428 | rptr = RREG32(CP_RB2_RPTR); |
|
| - | 1429 | } |
|
| - | 1430 | ||
| - | 1431 | return rptr; |
|
| - | 1432 | } |
|
| - | 1433 | ||
| - | 1434 | u32 cayman_gfx_get_wptr(struct radeon_device *rdev, |
|
| - | 1435 | struct radeon_ring *ring) |
|
| - | 1436 | { |
|
| - | 1437 | u32 wptr; |
|
| - | 1438 | ||
| - | 1439 | if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) |
|
| - | 1440 | wptr = RREG32(CP_RB0_WPTR); |
|
| - | 1441 | else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) |
|
| - | 1442 | wptr = RREG32(CP_RB1_WPTR); |
|
| - | 1443 | else |
|
| - | 1444 | wptr = RREG32(CP_RB2_WPTR); |
|
| - | 1445 | ||
| - | 1446 | return wptr; |
|
| - | 1447 | } |
|
| - | 1448 | ||
| - | 1449 | void cayman_gfx_set_wptr(struct radeon_device *rdev, |
|
| - | 1450 | struct radeon_ring *ring) |
|
| - | 1451 | { |
|
| - | 1452 | if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { |
|
| - | 1453 | WREG32(CP_RB0_WPTR, ring->wptr); |
|
| - | 1454 | (void)RREG32(CP_RB0_WPTR); |
|
| - | 1455 | } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { |
|
| - | 1456 | WREG32(CP_RB1_WPTR, ring->wptr); |
|
| - | 1457 | (void)RREG32(CP_RB1_WPTR); |
|
| - | 1458 | } else { |
|
| - | 1459 | WREG32(CP_RB2_WPTR, ring->wptr); |
|
| - | 1460 | (void)RREG32(CP_RB2_WPTR); |
|
| 1244 | } |
1461 | } |
| 1245 | } |
1462 | } |
| 1246 | 1463 | ||
| 1247 | static int cayman_cp_load_microcode(struct radeon_device *rdev) |
1464 | static int cayman_cp_load_microcode(struct radeon_device *rdev) |
| Line 1286... | Line 1503... | ||
| 1286 | radeon_ring_write(ring, 0x0); |
1503 | radeon_ring_write(ring, 0x0); |
| 1287 | radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); |
1504 | radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); |
| 1288 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
1505 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
| 1289 | radeon_ring_write(ring, 0); |
1506 | radeon_ring_write(ring, 0); |
| 1290 | radeon_ring_write(ring, 0); |
1507 | radeon_ring_write(ring, 0); |
| 1291 | radeon_ring_unlock_commit(rdev, ring); |
1508 | radeon_ring_unlock_commit(rdev, ring, false); |
| Line 1292... | Line 1509... | ||
| 1292 | 1509 | ||
| Line 1293... | Line 1510... | ||
| 1293 | cayman_cp_enable(rdev, true); |
1510 | cayman_cp_enable(rdev, true); |
| 1294 | 1511 | ||
| Line 1328... | Line 1545... | ||
| 1328 | radeon_ring_write(ring, 0xc0026900); |
1545 | radeon_ring_write(ring, 0xc0026900); |
| 1329 | radeon_ring_write(ring, 0x00000316); |
1546 | radeon_ring_write(ring, 0x00000316); |
| 1330 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
1547 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
| 1331 | radeon_ring_write(ring, 0x00000010); /* */ |
1548 | radeon_ring_write(ring, 0x00000010); /* */ |
| Line 1332... | Line 1549... | ||
| 1332 | 1549 | ||
| Line 1333... | Line 1550... | ||
| 1333 | radeon_ring_unlock_commit(rdev, ring); |
1550 | radeon_ring_unlock_commit(rdev, ring, false); |
| Line 1334... | Line 1551... | ||
| 1334 | 1551 | ||
| 1335 | /* XXX init other rings */ |
1552 | /* XXX init other rings */ |
| Line 1363... | Line 1580... | ||
| 1363 | static const unsigned cp_rb_base[] = { |
1580 | static const unsigned cp_rb_base[] = { |
| 1364 | CP_RB0_BASE, |
1581 | CP_RB0_BASE, |
| 1365 | CP_RB1_BASE, |
1582 | CP_RB1_BASE, |
| 1366 | CP_RB2_BASE |
1583 | CP_RB2_BASE |
| 1367 | }; |
1584 | }; |
| - | 1585 | static const unsigned cp_rb_rptr[] = { |
|
| - | 1586 | CP_RB0_RPTR, |
|
| - | 1587 | CP_RB1_RPTR, |
|
| - | 1588 | CP_RB2_RPTR |
|
| - | 1589 | }; |
|
| - | 1590 | static const unsigned cp_rb_wptr[] = { |
|
| - | 1591 | CP_RB0_WPTR, |
|
| - | 1592 | CP_RB1_WPTR, |
|
| - | 1593 | CP_RB2_WPTR |
|
| - | 1594 | }; |
|
| 1368 | struct radeon_ring *ring; |
1595 | struct radeon_ring *ring; |
| 1369 | int i, r; |
1596 | int i, r; |
| Line 1370... | Line 1597... | ||
| 1370 | 1597 | ||
| 1371 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ |
1598 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ |
| Line 1396... | Line 1623... | ||
| 1396 | uint32_t rb_cntl; |
1623 | uint32_t rb_cntl; |
| 1397 | uint64_t addr; |
1624 | uint64_t addr; |
| Line 1398... | Line 1625... | ||
| 1398 | 1625 | ||
| 1399 | /* Set ring buffer size */ |
1626 | /* Set ring buffer size */ |
| 1400 | ring = &rdev->ring[ridx[i]]; |
1627 | ring = &rdev->ring[ridx[i]]; |
| 1401 | rb_cntl = drm_order(ring->ring_size / 8); |
1628 | rb_cntl = order_base_2(ring->ring_size / 8); |
| 1402 | rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8; |
1629 | rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; |
| 1403 | #ifdef __BIG_ENDIAN |
1630 | #ifdef __BIG_ENDIAN |
| 1404 | rb_cntl |= BUF_SWAP_32BIT; |
1631 | rb_cntl |= BUF_SWAP_32BIT; |
| 1405 | #endif |
1632 | #endif |
| Line 1420... | Line 1647... | ||
| 1420 | for (i = 0; i < 3; ++i) { |
1647 | for (i = 0; i < 3; ++i) { |
| 1421 | /* Initialize the ring buffer's read and write pointers */ |
1648 | /* Initialize the ring buffer's read and write pointers */ |
| 1422 | ring = &rdev->ring[ridx[i]]; |
1649 | ring = &rdev->ring[ridx[i]]; |
| 1423 | WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); |
1650 | WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); |
| Line 1424... | Line 1651... | ||
| 1424 | 1651 | ||
| 1425 | ring->rptr = ring->wptr = 0; |
1652 | ring->wptr = 0; |
| 1426 | WREG32(ring->rptr_reg, ring->rptr); |
1653 | WREG32(cp_rb_rptr[i], 0); |
| Line 1427... | Line 1654... | ||
| 1427 | WREG32(ring->wptr_reg, ring->wptr); |
1654 | WREG32(cp_rb_wptr[i], ring->wptr); |
| 1428 | 1655 | ||
| 1429 | mdelay(1); |
1656 | mdelay(1); |
| Line 1442... | Line 1669... | ||
| 1442 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; |
1669 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; |
| 1443 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; |
1670 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; |
| 1444 | return r; |
1671 | return r; |
| 1445 | } |
1672 | } |
| Line 1446... | Line -... | ||
| 1446 | - | ||
| 1447 | return 0; |
- | |
| 1448 | } |
- | |
| 1449 | - | ||
| 1450 | /* |
- | |
| 1451 | * DMA |
- | |
| 1452 | * Starting with R600, the GPU has an asynchronous |
- | |
| 1453 | * DMA engine. The programming model is very similar |
- | |
| 1454 | * to the 3D engine (ring buffer, IBs, etc.), but the |
- | |
| 1455 | * DMA controller has it's own packet format that is |
- | |
| 1456 | * different form the PM4 format used by the 3D engine. |
- | |
| 1457 | * It supports copying data, writing embedded data, |
- | |
| 1458 | * solid fills, and a number of other things. It also |
- | |
| 1459 | * has support for tiling/detiling of buffers. |
- | |
| 1460 | * Cayman and newer support two asynchronous DMA engines. |
- | |
| 1461 | */ |
- | |
| 1462 | /** |
- | |
| 1463 | * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine |
- | |
| 1464 | * |
- | |
| 1465 | * @rdev: radeon_device pointer |
- | |
| 1466 | * @ib: IB object to schedule |
- | |
| 1467 | * |
- | |
| 1468 | * Schedule an IB in the DMA ring (cayman-SI). |
- | |
| 1469 | */ |
- | |
| 1470 | void cayman_dma_ring_ib_execute(struct radeon_device *rdev, |
- | |
| 1471 | struct radeon_ib *ib) |
- | |
| 1472 | { |
- | |
| 1473 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
- | |
| 1474 | - | ||
| 1475 | if (rdev->wb.enabled) { |
- | |
| 1476 | u32 next_rptr = ring->wptr + 4; |
- | |
| 1477 | while ((next_rptr & 7) != 5) |
- | |
| 1478 | next_rptr++; |
- | |
| 1479 | next_rptr += 3; |
- | |
| 1480 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); |
- | |
| 1481 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
- | |
| 1482 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); |
- | |
| 1483 | radeon_ring_write(ring, next_rptr); |
- | |
| 1484 | } |
- | |
| 1485 | - | ||
| 1486 | /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. |
- | |
| 1487 | * Pad as necessary with NOPs. |
- | |
| 1488 | */ |
- | |
| 1489 | while ((ring->wptr & 7) != 5) |
- | |
| 1490 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
- | |
| 1491 | radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0)); |
- | |
| 1492 | radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); |
- | |
| 1493 | radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); |
- | |
| 1494 | - | ||
| 1495 | } |
- | |
| 1496 | - | ||
| 1497 | /** |
- | |
| 1498 | * cayman_dma_stop - stop the async dma engines |
- | |
| 1499 | * |
- | |
| 1500 | * @rdev: radeon_device pointer |
- | |
| 1501 | * |
- | |
| 1502 | * Stop the async dma engines (cayman-SI). |
- | |
| 1503 | */ |
- | |
| 1504 | void cayman_dma_stop(struct radeon_device *rdev) |
- | |
| 1505 | { |
- | |
| 1506 | u32 rb_cntl; |
- | |
| 1507 | - | ||
| 1508 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
- | |
| 1509 | - | ||
| 1510 | /* dma0 */ |
- | |
| 1511 | rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); |
- | |
| 1512 | rb_cntl &= ~DMA_RB_ENABLE; |
- | |
| 1513 | WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); |
- | |
| 1514 | - | ||
| 1515 | /* dma1 */ |
- | |
| 1516 | rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); |
- | |
| 1517 | rb_cntl &= ~DMA_RB_ENABLE; |
- | |
| 1518 | WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); |
- | |
| 1519 | - | ||
| 1520 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; |
- | |
| 1521 | rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; |
- | |
| 1522 | } |
- | |
| 1523 | - | ||
| 1524 | /** |
- | |
| 1525 | * cayman_dma_resume - setup and start the async dma engines |
- | |
| 1526 | * |
- | |
| 1527 | * @rdev: radeon_device pointer |
- | |
| 1528 | * |
- | |
| 1529 | * Set up the DMA ring buffers and enable them. (cayman-SI). |
- | |
| 1530 | * Returns 0 for success, error for failure. |
- | |
| 1531 | */ |
- | |
| 1532 | int cayman_dma_resume(struct radeon_device *rdev) |
- | |
| 1533 | { |
- | |
| 1534 | struct radeon_ring *ring; |
- | |
| 1535 | u32 rb_cntl, dma_cntl, ib_cntl; |
- | |
| 1536 | u32 rb_bufsz; |
- | |
| 1537 | u32 reg_offset, wb_offset; |
- | |
| 1538 | int i, r; |
- | |
| 1539 | - | ||
| 1540 | /* Reset dma */ |
- | |
| 1541 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); |
- | |
| 1542 | RREG32(SRBM_SOFT_RESET); |
- | |
| 1543 | udelay(50); |
- | |
| 1544 | WREG32(SRBM_SOFT_RESET, 0); |
- | |
| 1545 | - | ||
| 1546 | for (i = 0; i < 2; i++) { |
- | |
| 1547 | if (i == 0) { |
- | |
| 1548 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
- | |
| 1549 | reg_offset = DMA0_REGISTER_OFFSET; |
- | |
| 1550 | wb_offset = R600_WB_DMA_RPTR_OFFSET; |
- | |
| 1551 | } else { |
1673 | |
| 1552 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; |
- | |
| 1553 | reg_offset = DMA1_REGISTER_OFFSET; |
- | |
| 1554 | wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; |
- | |
| 1555 | } |
- | |
| 1556 | - | ||
| 1557 | WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); |
- | |
| 1558 | WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); |
- | |
| 1559 | - | ||
| 1560 | /* Set ring buffer size in dwords */ |
- | |
| 1561 | rb_bufsz = drm_order(ring->ring_size / 4); |
- | |
| 1562 | rb_cntl = rb_bufsz << 1; |
- | |
| 1563 | #ifdef __BIG_ENDIAN |
- | |
| 1564 | rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; |
- | |
| 1565 | #endif |
- | |
| 1566 | WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); |
- | |
| 1567 | - | ||
| 1568 | /* Initialize the ring buffer's read and write pointers */ |
- | |
| 1569 | WREG32(DMA_RB_RPTR + reg_offset, 0); |
- | |
| 1570 | WREG32(DMA_RB_WPTR + reg_offset, 0); |
- | |
| 1571 | - | ||
| 1572 | /* set the wb address whether it's enabled or not */ |
- | |
| 1573 | WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, |
- | |
| 1574 | upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); |
- | |
| 1575 | WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, |
- | |
| 1576 | ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); |
- | |
| 1577 | - | ||
| 1578 | if (rdev->wb.enabled) |
- | |
| 1579 | rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; |
- | |
| 1580 | - | ||
| 1581 | WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); |
- | |
| 1582 | - | ||
| 1583 | /* enable DMA IBs */ |
- | |
| 1584 | ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE; |
- | |
| 1585 | #ifdef __BIG_ENDIAN |
- | |
| 1586 | ib_cntl |= DMA_IB_SWAP_ENABLE; |
- | |
| 1587 | #endif |
- | |
| 1588 | WREG32(DMA_IB_CNTL + reg_offset, ib_cntl); |
- | |
| 1589 | - | ||
| 1590 | dma_cntl = RREG32(DMA_CNTL + reg_offset); |
- | |
| 1591 | dma_cntl &= ~CTXEMPTY_INT_ENABLE; |
- | |
| 1592 | WREG32(DMA_CNTL + reg_offset, dma_cntl); |
- | |
| 1593 | - | ||
| 1594 | ring->wptr = 0; |
- | |
| 1595 | WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2); |
- | |
| 1596 | - | ||
| 1597 | ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2; |
- | |
| 1598 | - | ||
| 1599 | WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); |
- | |
| 1600 | - | ||
| 1601 | ring->ready = true; |
- | |
| 1602 | - | ||
| 1603 | r = radeon_ring_test(rdev, ring->idx, ring); |
- | |
| 1604 | if (r) { |
- | |
| 1605 | ring->ready = false; |
- | |
| 1606 | return r; |
- | |
| 1607 | } |
- | |
| 1608 | } |
- | |
| 1609 | 1674 | if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) |
|
| Line 1610... | Line 1675... | ||
| 1610 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
1675 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
| 1611 | 1676 | ||
| Line 1612... | Line -... | ||
| 1612 | return 0; |
- | |
| 1613 | } |
- | |
| 1614 | - | ||
| 1615 | /** |
- | |
| 1616 | * cayman_dma_fini - tear down the async dma engines |
- | |
| 1617 | * |
- | |
| 1618 | * @rdev: radeon_device pointer |
- | |
| 1619 | * |
- | |
| 1620 | * Stop the async dma engines and free the rings (cayman-SI). |
- | |
| 1621 | */ |
- | |
| 1622 | void cayman_dma_fini(struct radeon_device *rdev) |
- | |
| 1623 | { |
- | |
| 1624 | cayman_dma_stop(rdev); |
- | |
| 1625 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); |
- | |
| 1626 | radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); |
1677 | return 0; |
| 1627 | } |
1678 | } |
| 1628 | 1679 | ||
| 1629 | static u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) |
1680 | u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) |
| Line 1630... | Line 1681... | ||
| 1630 | { |
1681 | { |
| Line 1847... | Line 1898... | ||
| 1847 | 1898 | ||
| Line 1848... | Line 1899... | ||
| 1848 | cayman_gpu_soft_reset(rdev, reset_mask); |
1899 | cayman_gpu_soft_reset(rdev, reset_mask); |
| Line 1849... | Line 1900... | ||
| 1849 | 1900 | ||
| - | 1901 | reset_mask = cayman_gpu_check_soft_reset(rdev); |
|
| - | 1902 | ||
| 1850 | reset_mask = cayman_gpu_check_soft_reset(rdev); |
1903 | if (reset_mask) |
| Line 1851... | Line 1904... | ||
| 1851 | 1904 | evergreen_gpu_pci_config_reset(rdev); |
|
| 1852 | if (!reset_mask) |
1905 | |
| Line 1869... | Line 1922... | ||
| 1869 | u32 reset_mask = cayman_gpu_check_soft_reset(rdev); |
1922 | u32 reset_mask = cayman_gpu_check_soft_reset(rdev); |
| Line 1870... | Line 1923... | ||
| 1870 | 1923 | ||
| 1871 | if (!(reset_mask & (RADEON_RESET_GFX | |
1924 | if (!(reset_mask & (RADEON_RESET_GFX | |
| 1872 | RADEON_RESET_COMPUTE | |
1925 | RADEON_RESET_COMPUTE | |
| 1873 | RADEON_RESET_CP))) { |
1926 | RADEON_RESET_CP))) { |
| 1874 | radeon_ring_lockup_update(ring); |
- | |
| 1875 | return false; |
- | |
| 1876 | } |
- | |
| 1877 | /* force CP activities */ |
- | |
| 1878 | radeon_ring_force_activity(rdev, ring); |
- | |
| 1879 | return radeon_ring_test_lockup(rdev, ring); |
- | |
| 1880 | } |
- | |
| 1881 | - | ||
| 1882 | /** |
- | |
| 1883 | * cayman_dma_is_lockup - Check if the DMA engine is locked up |
- | |
| 1884 | * |
- | |
| 1885 | * @rdev: radeon_device pointer |
- | |
| 1886 | * @ring: radeon_ring structure holding ring information |
- | |
| 1887 | * |
- | |
| 1888 | * Check if the async DMA engine is locked up. |
- | |
| 1889 | * Returns true if the engine appears to be locked up, false if not. |
- | |
| 1890 | */ |
- | |
| 1891 | bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
- | |
| 1892 | { |
- | |
| 1893 | u32 reset_mask = cayman_gpu_check_soft_reset(rdev); |
- | |
| 1894 | u32 mask; |
- | |
| 1895 | - | ||
| 1896 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
- | |
| 1897 | mask = RADEON_RESET_DMA; |
- | |
| 1898 | else |
- | |
| 1899 | mask = RADEON_RESET_DMA1; |
- | |
| 1900 | - | ||
| 1901 | if (!(reset_mask & mask)) { |
- | |
| 1902 | radeon_ring_lockup_update(ring); |
1927 | radeon_ring_lockup_update(rdev, ring); |
| 1903 | return false; |
1928 | return false; |
| 1904 | } |
- | |
| 1905 | /* force ring activities */ |
- | |
| 1906 | radeon_ring_force_activity(rdev, ring); |
1929 | } |
| 1907 | return radeon_ring_test_lockup(rdev, ring); |
1930 | return radeon_ring_test_lockup(rdev, ring); |
| Line 1908... | Line 1931... | ||
| 1908 | } |
1931 | } |
| 1909 | 1932 | ||
| 1910 | static int cayman_startup(struct radeon_device *rdev) |
1933 | static int cayman_startup(struct radeon_device *rdev) |
| 1911 | { |
1934 | { |
| Line 1912... | Line 1935... | ||
| 1912 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
1935 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
| 1913 | int r; |
1936 | int r; |
| - | 1937 | ||
| - | 1938 | /* enable pcie gen2 link */ |
|
| Line 1914... | Line -... | ||
| 1914 | - | ||
| 1915 | /* enable pcie gen2 link */ |
1939 | evergreen_pcie_gen2_enable(rdev); |
| 1916 | evergreen_pcie_gen2_enable(rdev); |
- | |
| 1917 | - | ||
| 1918 | if (rdev->flags & RADEON_IS_IGP) { |
- | |
| 1919 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
- | |
| 1920 | r = ni_init_microcode(rdev); |
- | |
| 1921 | if (r) { |
- | |
| 1922 | DRM_ERROR("Failed to load firmware!\n"); |
- | |
| 1923 | return r; |
- | |
| 1924 | } |
1940 | /* enable aspm */ |
| 1925 | } |
1941 | evergreen_program_aspm(rdev); |
| 1926 | } else { |
- | |
| 1927 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { |
1942 | |
| 1928 | r = ni_init_microcode(rdev); |
- | |
| 1929 | if (r) { |
- | |
| Line -... | Line 1943... | ||
| - | 1943 | /* scratch needs to be initialized before MC */ |
|
| - | 1944 | r = r600_vram_scratch_init(rdev); |
|
| - | 1945 | if (r) |
|
| 1930 | DRM_ERROR("Failed to load firmware!\n"); |
1946 | return r; |
| 1931 | return r; |
1947 | |
| 1932 | } |
1948 | evergreen_mc_program(rdev); |
| 1933 | } |
1949 | |
| 1934 | 1950 | if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { |
|
| 1935 | r = ni_mc_load_microcode(rdev); |
1951 | r = ni_mc_load_microcode(rdev); |
| Line 1936... | Line -... | ||
| 1936 | if (r) { |
- | |
| 1937 | DRM_ERROR("Failed to load MC firmware!\n"); |
- | |
| 1938 | return r; |
- | |
| 1939 | } |
- | |
| 1940 | } |
- | |
| 1941 | 1952 | if (r) { |
|
| 1942 | r = r600_vram_scratch_init(rdev); |
1953 | DRM_ERROR("Failed to load MC firmware!\n"); |
| 1943 | if (r) |
1954 | return r; |
| 1944 | return r; |
1955 | } |
| Line 1945... | Line -... | ||
| 1945 | - | ||
| 1946 | evergreen_mc_program(rdev); |
- | |
| 1947 | r = cayman_pcie_gart_enable(rdev); |
- | |
| 1948 | if (r) |
- | |
| 1949 | return r; |
- | |
| 1950 | cayman_gpu_init(rdev); |
- | |
| 1951 | - | ||
| 1952 | r = evergreen_blit_init(rdev); |
1956 | } |
| 1953 | if (r) { |
1957 | |
| - | 1958 | r = cayman_pcie_gart_enable(rdev); |
|
| - | 1959 | if (r) |
|
| - | 1960 | return r; |
|
| - | 1961 | cayman_gpu_init(rdev); |
|
| 1954 | // r600_blit_fini(rdev); |
1962 | |
| 1955 | rdev->asic->copy.copy = NULL; |
1963 | /* allocate rlc buffers */ |
| 1956 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
1964 | if (rdev->flags & RADEON_IS_IGP) { |
| 1957 | } |
1965 | rdev->rlc.reg_list = tn_rlc_save_restore_register_list; |
| 1958 | 1966 | rdev->rlc.reg_list_size = |
|
| 1959 | /* allocate rlc buffers */ |
1967 | (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list); |
| Line 2024... | Line 2032... | ||
| 2024 | return r; |
2032 | return r; |
| 2025 | } |
2033 | } |
| 2026 | evergreen_irq_set(rdev); |
2034 | evergreen_irq_set(rdev); |
| Line 2027... | Line 2035... | ||
| 2027 | 2035 | ||
| 2028 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
- | |
| 2029 | CP_RB0_RPTR, CP_RB0_WPTR, |
2036 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
| 2030 | 0, 0xfffff, RADEON_CP_PACKET2); |
2037 | RADEON_CP_PACKET2); |
| 2031 | if (r) |
2038 | if (r) |
| Line 2032... | Line 2039... | ||
| 2032 | return r; |
2039 | return r; |
| 2033 | 2040 | ||
| 2034 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
- | |
| 2035 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
- | |
| 2036 | DMA_RB_RPTR + DMA0_REGISTER_OFFSET, |
2041 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
| 2037 | DMA_RB_WPTR + DMA0_REGISTER_OFFSET, |
2042 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
| 2038 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
2043 | DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
| Line 2039... | Line 2044... | ||
| 2039 | if (r) |
2044 | if (r) |
| 2040 | return r; |
2045 | return r; |
| 2041 | - | ||
| 2042 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; |
- | |
| 2043 | r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, |
2046 | |
| 2044 | DMA_RB_RPTR + DMA1_REGISTER_OFFSET, |
2047 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; |
| 2045 | DMA_RB_WPTR + DMA1_REGISTER_OFFSET, |
2048 | r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, |
| Line 2046... | Line 2049... | ||
| 2046 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
2049 | DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
| 2047 | if (r) |
2050 | if (r) |
| Line 2056... | Line 2059... | ||
| 2056 | 2059 | ||
| 2057 | r = cayman_dma_resume(rdev); |
2060 | r = cayman_dma_resume(rdev); |
| 2058 | if (r) |
2061 | if (r) |
| Line 2059... | Line -... | ||
| 2059 | return r; |
- | |
| 2060 | - | ||
| 2061 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
- | |
| 2062 | if (ring->ring_size) { |
- | |
| 2063 | r = radeon_ring_init(rdev, ring, ring->ring_size, |
- | |
| 2064 | R600_WB_UVD_RPTR_OFFSET, |
- | |
| 2065 | UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, |
- | |
| 2066 | 0, 0xfffff, RADEON_CP_PACKET2); |
- | |
| 2067 | if (!r) |
- | |
| 2068 | r = r600_uvd_init(rdev); |
- | |
| 2069 | if (r) |
- | |
| Line 2070... | Line 2062... | ||
| 2070 | DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
2062 | return r; |
| 2071 | } |
2063 | |
| 2072 | 2064 | ||
| 2073 | r = radeon_ib_pool_init(rdev); |
2065 | r = radeon_ib_pool_init(rdev); |
| Line 2143... | Line 2135... | ||
| 2143 | /* Memory manager */ |
2135 | /* Memory manager */ |
| 2144 | r = radeon_bo_init(rdev); |
2136 | r = radeon_bo_init(rdev); |
| 2145 | if (r) |
2137 | if (r) |
| 2146 | return r; |
2138 | return r; |
| Line -... | Line 2139... | ||
| - | 2139 | ||
| - | 2140 | if (rdev->flags & RADEON_IS_IGP) { |
|
| - | 2141 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
|
| - | 2142 | r = ni_init_microcode(rdev); |
|
| - | 2143 | if (r) { |
|
| - | 2144 | DRM_ERROR("Failed to load firmware!\n"); |
|
| - | 2145 | return r; |
|
| - | 2146 | } |
|
| - | 2147 | } |
|
| - | 2148 | } else { |
|
| - | 2149 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { |
|
| - | 2150 | r = ni_init_microcode(rdev); |
|
| - | 2151 | if (r) { |
|
| - | 2152 | DRM_ERROR("Failed to load firmware!\n"); |
|
| - | 2153 | return r; |
|
| - | 2154 | } |
|
| - | 2155 | } |
|
| - | 2156 | } |
|
| - | 2157 | ||
| - | 2158 | /* Initialize power management */ |
|
| - | 2159 | radeon_pm_init(rdev); |
|
| 2147 | 2160 | ||
| 2148 | ring->ring_obj = NULL; |
2161 | ring->ring_obj = NULL; |
| Line 2149... | Line 2162... | ||
| 2149 | r600_ring_init(rdev, ring, 1024 * 1024); |
2162 | r600_ring_init(rdev, ring, 1024 * 1024); |
| 2150 | 2163 | ||
| Line 2211... | Line 2224... | ||
| 2211 | 2224 | ||
| 2212 | void cayman_vm_fini(struct radeon_device *rdev) |
2225 | void cayman_vm_fini(struct radeon_device *rdev) |
| 2213 | { |
2226 | { |
| Line 2214... | Line -... | ||
| 2214 | } |
- | |
| 2215 | - | ||
| 2216 | #define R600_ENTRY_VALID (1 << 0) |
- | |
| 2217 | #define R600_PTE_SYSTEM (1 << 1) |
- | |
| 2218 | #define R600_PTE_SNOOPED (1 << 2) |
- | |
| 2219 | #define R600_PTE_READABLE (1 << 5) |
- | |
| 2220 | #define R600_PTE_WRITEABLE (1 << 6) |
- | |
| 2221 | - | ||
| 2222 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags) |
- | |
| 2223 | { |
- | |
| 2224 | uint32_t r600_flags = 0; |
- | |
| 2225 | r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0; |
- | |
| 2226 | r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0; |
- | |
| 2227 | r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0; |
- | |
| 2228 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
- | |
| 2229 | r600_flags |= R600_PTE_SYSTEM; |
- | |
| 2230 | r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0; |
- | |
| 2231 | } |
- | |
| 2232 | return r600_flags; |
- | |
| 2233 | } |
2227 | } |
| 2234 | 2228 | ||
| 2235 | /** |
2229 | /** |
| 2236 | * cayman_vm_set_page - update the page tables using the CP |
2230 | * cayman_vm_decode_fault - print human readable fault info |
| 2237 | * |
2231 | * |
| 2238 | * @rdev: radeon_device pointer |
- | |
| 2239 | * @ib: indirect buffer to fill with commands |
2232 | * @rdev: radeon_device pointer |
| 2240 | * @pe: addr of the page entry |
- | |
| 2241 | * @addr: dst addr to write into pe |
- | |
| 2242 | * @count: number of page entries to update |
- | |
| 2243 | * @incr: increase next addr by incr bytes |
2233 | * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value |
| 2244 | * @flags: access flags |
2234 | * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value |
| 2245 | * |
2235 | * |
| 2246 | * Update the page tables using the CP (cayman/TN). |
2236 | * Print human readable fault information (cayman/TN). |
| 2247 | */ |
- | |
| 2248 | void cayman_vm_set_page(struct radeon_device *rdev, |
- | |
| 2249 | struct radeon_ib *ib, |
- | |
| 2250 | uint64_t pe, |
2237 | */ |
| 2251 | uint64_t addr, unsigned count, |
2238 | void cayman_vm_decode_fault(struct radeon_device *rdev, |
| - | 2239 | u32 status, u32 addr) |
|
| 2252 | uint32_t incr, uint32_t flags) |
2240 | { |
| 2253 | { |
2241 | u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; |
| 2254 | uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); |
2242 | u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT; |
| 2255 | uint64_t value; |
2243 | u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT; |
| 2256 | unsigned ndw; |
- | |
| 2257 | 2244 | char *block; |
|
| 2258 | if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) { |
2245 | |
| - | 2246 | switch (mc_id) { |
|
| - | 2247 | case 32: |
|
| - | 2248 | case 16: |
|
| - | 2249 | case 96: |
|
| - | 2250 | case 80: |
|
| - | 2251 | case 160: |
|
| 2259 | while (count) { |
2252 | case 144: |
| 2260 | ndw = 1 + count * 2; |
2253 | case 224: |
| 2261 | if (ndw > 0x3FFF) |
2254 | case 208: |
| - | 2255 | block = "CB"; |
|
| - | 2256 | break; |
|
| - | 2257 | case 33: |
|
| - | 2258 | case 17: |
|
| - | 2259 | case 97: |
|
| - | 2260 | case 81: |
|
| - | 2261 | case 161: |
|
| - | 2262 | case 145: |
|
| 2262 | ndw = 0x3FFF; |
2263 | case 225: |
| 2263 | 2264 | case 209: |
|
| - | 2265 | block = "CB_FMASK"; |
|
| - | 2266 | break; |
|
| - | 2267 | case 34: |
|
| - | 2268 | case 18: |
|
| - | 2269 | case 98: |
|
| - | 2270 | case 82: |
|
| - | 2271 | case 162: |
|
| - | 2272 | case 146: |
|
| 2264 | ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw); |
2273 | case 226: |
| - | 2274 | case 210: |
|
| - | 2275 | block = "CB_CMASK"; |
|
| - | 2276 | break; |
|
| - | 2277 | case 35: |
|
| 2265 | ib->ptr[ib->length_dw++] = pe; |
2278 | case 19: |
| - | 2279 | case 99: |
|
| - | 2280 | case 83: |
|
| - | 2281 | case 163: |
|
| - | 2282 | case 147: |
|
| 2266 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
2283 | case 227: |
| - | 2284 | case 211: |
|
| - | 2285 | block = "CB_IMMED"; |
|
| - | 2286 | break; |
|
| - | 2287 | case 36: |
|
| - | 2288 | case 20: |
|
| - | 2289 | case 100: |
|
| - | 2290 | case 84: |
|
| - | 2291 | case 164: |
|
| - | 2292 | case 148: |
|
| 2267 | for (; ndw > 1; ndw -= 2, --count, pe += 8) { |
2293 | case 228: |
| - | 2294 | case 212: |
|
| - | 2295 | block = "DB"; |
|
| - | 2296 | break; |
|
| 2268 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
2297 | case 37: |
| - | 2298 | case 21: |
|
| - | 2299 | case 101: |
|
| - | 2300 | case 85: |
|
| - | 2301 | case 165: |
|
| - | 2302 | case 149: |
|
| 2269 | value = radeon_vm_map_gart(rdev, addr); |
2303 | case 229: |
| 2270 | value &= 0xFFFFFFFFFFFFF000ULL; |
2304 | case 213: |
| - | 2305 | block = "DB_HTILE"; |
|
| - | 2306 | break; |
|
| - | 2307 | case 38: |
|
| - | 2308 | case 22: |
|
| - | 2309 | case 102: |
|
| 2271 | } else if (flags & RADEON_VM_PAGE_VALID) { |
2310 | case 86: |
| 2272 | value = addr; |
2311 | case 166: |
| 2273 | } else { |
2312 | case 150: |
| 2274 | value = 0; |
2313 | case 230: |
| - | 2314 | case 214: |
|
| - | 2315 | block = "SX"; |
|
| - | 2316 | break; |
|
| - | 2317 | case 39: |
|
| - | 2318 | case 23: |
|
| - | 2319 | case 103: |
|
| - | 2320 | case 87: |
|
| - | 2321 | case 167: |
|
| - | 2322 | case 151: |
|
| 2275 | } |
2323 | case 231: |
| 2276 | addr += incr; |
2324 | case 215: |
| - | 2325 | block = "DB_STEN"; |
|
| - | 2326 | break; |
|
| - | 2327 | case 40: |
|
| - | 2328 | case 24: |
|
| - | 2329 | case 104: |
|
| - | 2330 | case 88: |
|
| - | 2331 | case 232: |
|
| - | 2332 | case 216: |
|
| 2277 | value |= r600_flags; |
2333 | case 168: |
| 2278 | ib->ptr[ib->length_dw++] = value; |
2334 | case 152: |
| - | 2335 | block = "TC_TFETCH"; |
|
| 2279 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
2336 | break; |
| - | 2337 | case 41: |
|
| 2280 | } |
2338 | case 25: |
| - | 2339 | case 105: |
|
| - | 2340 | case 89: |
|
| - | 2341 | case 233: |
|
| - | 2342 | case 217: |
|
| 2281 | } |
2343 | case 169: |
| - | 2344 | case 153: |
|
| - | 2345 | block = "TC_VFETCH"; |
|
| - | 2346 | break; |
|
| 2282 | } else { |
2347 | case 42: |
| - | 2348 | case 26: |
|
| 2283 | if ((flags & RADEON_VM_PAGE_SYSTEM) || |
2349 | case 106: |
| 2284 | (count == 1)) { |
2350 | case 90: |
| 2285 | while (count) { |
2351 | case 234: |
| - | 2352 | case 218: |
|
| 2286 | ndw = count * 2; |
2353 | case 170: |
| 2287 | if (ndw > 0xFFFFE) |
2354 | case 154: |
| 2288 | ndw = 0xFFFFE; |
2355 | block = "VC"; |
| 2289 | 2356 | break; |
|
| 2290 | /* for non-physically contiguous pages (system) */ |
2357 | case 112: |
| 2291 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw); |
2358 | block = "CP"; |
| 2292 | ib->ptr[ib->length_dw++] = pe; |
2359 | break; |
| 2293 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
2360 | case 113: |
| 2294 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { |
2361 | case 114: |
| 2295 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
2362 | block = "SH"; |
| 2296 | value = radeon_vm_map_gart(rdev, addr); |
2363 | break; |
| 2297 | value &= 0xFFFFFFFFFFFFF000ULL; |
2364 | case 115: |
| 2298 | } else if (flags & RADEON_VM_PAGE_VALID) { |
2365 | block = "VGT"; |
| 2299 | value = addr; |
2366 | break; |
| 2300 | } else { |
2367 | case 178: |
| - | 2368 | block = "IH"; |
|
| 2301 | value = 0; |
2369 | break; |
| - | 2370 | case 51: |
|
| - | 2371 | block = "RLC"; |
|
| 2302 | } |
2372 | break; |
| - | 2373 | case 55: |
|
| - | 2374 | block = "DMA"; |
|
| 2303 | addr += incr; |
2375 | break; |
| - | 2376 | case 56: |
|
| - | 2377 | block = "HDP"; |
|
| 2304 | value |= r600_flags; |
2378 | break; |
| 2305 | ib->ptr[ib->length_dw++] = value; |
2379 | default: |
| 2306 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
2380 | block = "unknown"; |
| 2307 | } |
- | |
| 2308 | } |
- | |
| 2309 | while (ib->length_dw & 0x7) |
- | |
| 2310 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0); |
- | |
| 2311 | } else { |
- | |
| 2312 | while (count) { |
- | |
| 2313 | ndw = count * 2; |
- | |
| Line 2314... | Line -... | ||
| 2314 | if (ndw > 0xFFFFE) |
- | |
| 2315 | ndw = 0xFFFFE; |
- | |
| 2316 | - | ||
| 2317 | if (flags & RADEON_VM_PAGE_VALID) |
- | |
| 2318 | value = addr; |
2381 | break; |
| 2319 | else |
- | |
| 2320 | value = 0; |
- | |
| 2321 | /* for physically contiguous pages (vram) */ |
- | |
| 2322 | ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); |
- | |
| 2323 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ |
2382 | } |
| 2324 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
- | |
| 2325 | ib->ptr[ib->length_dw++] = r600_flags; /* mask */ |
- | |
| 2326 | ib->ptr[ib->length_dw++] = 0; |
2383 | |
| 2327 | ib->ptr[ib->length_dw++] = value; /* value */ |
- | |
| 2328 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
2384 | printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", |
| 2329 | ib->ptr[ib->length_dw++] = incr; /* increment size */ |
- | |
| 2330 | ib->ptr[ib->length_dw++] = 0; |
- | |
| 2331 | pe += ndw * 4; |
- | |
| 2332 | addr += (ndw / 2) * incr; |
- | |
| 2333 | count -= ndw / 2; |
- | |
| 2334 | } |
- | |
| 2335 | } |
- | |
| 2336 | while (ib->length_dw & 0x7) |
2385 | protections, vmid, addr, |
| Line 2337... | Line 2386... | ||
| 2337 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0); |
2386 | (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read", |
| 2338 | } |
2387 | block, mc_id); |
| 2339 | } |
2388 | } |
| Line 2366... | Line 2415... | ||
| 2366 | 2415 | ||
| 2367 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
2416 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
| 2368 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
2417 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
| 2369 | radeon_ring_write(ring, 0x0); |
2418 | radeon_ring_write(ring, 0x0); |
| 2370 | } |
- | |
| 2371 | - | ||
| 2372 | void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) |
- | |
| 2373 | { |
- | |
| 2374 | struct radeon_ring *ring = &rdev->ring[ridx]; |
- | |
| 2375 | - | ||
| 2376 | if (vm == NULL) |
- | |
| 2377 | return; |
- | |
| 2378 | - | ||
| 2379 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); |
- | |
| 2380 | radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2)); |
- | |
| 2381 | radeon_ring_write(ring, vm->pd_gpu_addr >> 12); |
- | |
| 2382 | - | ||
| 2383 | /* flush hdp cache */ |
- | |
| 2384 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); |
- | |
| 2385 | radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); |
- | |
| 2386 | radeon_ring_write(ring, 1); |
- | |
| 2387 | - | ||
| 2388 | /* bits 0-7 are the VM contexts0-7 */ |
- | |
| 2389 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); |
- | |
| 2390 | radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); |
- | |
| 2391 | radeon_ring_write(ring, 1 << vm->id); |
- | |
| 2392 | } |
- | |