Rev 2005 | Rev 2997 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 2005 | Rev 2160 | ||
|---|---|---|---|
| Line 831... | Line 831... | ||
| 831 | rdev->config.cayman.tile_config |= |
831 | rdev->config.cayman.tile_config |= |
| 832 | ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; |
832 | ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; |
| 833 | rdev->config.cayman.tile_config |= |
833 | rdev->config.cayman.tile_config |= |
| 834 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; |
834 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; |
| Line -... | Line 835... | ||
| - | 835 | ||
| 835 | 836 | rdev->config.cayman.backend_map = gb_backend_map; |
|
| 836 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
837 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
| 837 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
838 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
| 838 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
839 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
| Line 1145... | Line 1146... | ||
| 1145 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ |
1146 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ |
| 1146 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | |
1147 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | |
| 1147 | SOFT_RESET_PA | |
1148 | SOFT_RESET_PA | |
| 1148 | SOFT_RESET_SH | |
1149 | SOFT_RESET_SH | |
| 1149 | SOFT_RESET_VGT | |
1150 | SOFT_RESET_VGT | |
| - | 1151 | SOFT_RESET_SPI | |
|
| 1150 | SOFT_RESET_SX)); |
1152 | SOFT_RESET_SX)); |
| 1151 | RREG32(GRBM_SOFT_RESET); |
1153 | RREG32(GRBM_SOFT_RESET); |
| 1152 | mdelay(15); |
1154 | mdelay(15); |
| 1153 | WREG32(GRBM_SOFT_RESET, 0); |
1155 | WREG32(GRBM_SOFT_RESET, 0); |
| 1154 | RREG32(GRBM_SOFT_RESET); |
1156 | RREG32(GRBM_SOFT_RESET); |