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Line 29... | Line 29... | ||
29 | #include "radeon_asic.h" |
29 | #include "radeon_asic.h" |
30 | #include "radeon_drm.h" |
30 | #include "radeon_drm.h" |
31 | #include "nid.h" |
31 | #include "nid.h" |
32 | #include "atom.h" |
32 | #include "atom.h" |
33 | #include "ni_reg.h" |
33 | #include "ni_reg.h" |
34 | //#include "cayman_blit_shaders.h" |
34 | #include "cayman_blit_shaders.h" |
Line 35... | Line 35... | ||
35 | 35 | ||
36 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
36 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
37 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
37 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
38 | extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
38 | extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
Line 387... | Line 387... | ||
387 | rdev->mc_fw = NULL; |
387 | rdev->mc_fw = NULL; |
388 | } |
388 | } |
389 | return err; |
389 | return err; |
390 | } |
390 | } |
Line 391... | Line -... | ||
391 | - | ||
392 | #if 0 |
391 | |
393 | /* |
392 | /* |
394 | * Core functions |
393 | * Core functions |
395 | */ |
394 | */ |
396 | static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
395 | static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
Line 1027... | Line 1026... | ||
1027 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
1026 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
1028 | } |
1027 | } |
1029 | } |
1028 | } |
1030 | } |
1029 | } |
Line 1031... | Line -... | ||
1031 | - | ||
1032 | void cayman_pcie_gart_fini(struct radeon_device *rdev) |
- | |
1033 | { |
- | |
1034 | cayman_pcie_gart_disable(rdev); |
- | |
1035 | radeon_gart_table_vram_free(rdev); |
- | |
1036 | radeon_gart_fini(rdev); |
- | |
Line 1037... | Line 1030... | ||
1037 | } |
1030 | |
1038 | 1031 | ||
1039 | /* |
1032 | /* |
1040 | * CP. |
1033 | * CP. |
1041 | */ |
1034 | */ |
1042 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
1035 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
1043 | { |
1036 | { |
1044 | if (enable) |
1037 | if (enable) |
1045 | WREG32(CP_ME_CNTL, 0); |
- | |
1046 | else { |
1038 | WREG32(CP_ME_CNTL, 0); |
1047 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
1039 | else { |
1048 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
1040 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
1049 | WREG32(SCRATCH_UMSK, 0); |
1041 | WREG32(SCRATCH_UMSK, 0); |
Line 1140... | Line 1132... | ||
1140 | /* XXX init other rings */ |
1132 | /* XXX init other rings */ |
Line 1141... | Line 1133... | ||
1141 | 1133 | ||
1142 | return 0; |
1134 | return 0; |
Line 1143... | Line -... | ||
1143 | } |
- | |
1144 | - | ||
1145 | static void cayman_cp_fini(struct radeon_device *rdev) |
- | |
1146 | { |
- | |
1147 | cayman_cp_enable(rdev, false); |
1135 | } |
Line 1148... | Line 1136... | ||
1148 | radeon_ring_fini(rdev); |
1136 | |
1149 | } |
1137 | |
1150 | 1138 | ||
1151 | int cayman_cp_resume(struct radeon_device *rdev) |
1139 | int cayman_cp_resume(struct radeon_device *rdev) |
Line 1386... | Line 1374... | ||
1386 | r = cayman_pcie_gart_enable(rdev); |
1374 | r = cayman_pcie_gart_enable(rdev); |
1387 | if (r) |
1375 | if (r) |
1388 | return r; |
1376 | return r; |
1389 | cayman_gpu_init(rdev); |
1377 | cayman_gpu_init(rdev); |
Line 1390... | Line -... | ||
1390 | - | ||
1391 | r = evergreen_blit_init(rdev); |
- | |
1392 | if (r) { |
- | |
1393 | evergreen_blit_fini(rdev); |
- | |
1394 | rdev->asic->copy = NULL; |
- | |
1395 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
- | |
Line 1396... | Line 1378... | ||
1396 | } |
1378 | |
1397 | - | ||
1398 | /* allocate wb buffer */ |
- | |
1399 | r = radeon_wb_init(rdev); |
- | |
Line 1400... | Line 1379... | ||
1400 | if (r) |
1379 | |
1401 | return r; |
- | |
1402 | - | ||
1403 | /* Enable IRQ */ |
- | |
1404 | r = r600_irq_init(rdev); |
- | |
1405 | if (r) { |
- | |
1406 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
- | |
1407 | radeon_irq_kms_fini(rdev); |
- | |
Line 1408... | Line 1380... | ||
1408 | return r; |
1380 | /* allocate wb buffer */ |
1409 | } |
1381 | |
1410 | evergreen_irq_set(rdev); |
1382 | /* Enable IRQ */ |
1411 | 1383 | ||
Line 1420... | Line 1392... | ||
1420 | return r; |
1392 | return r; |
Line 1421... | Line 1393... | ||
1421 | 1393 | ||
1422 | return 0; |
1394 | return 0; |
Line 1423... | Line -... | ||
1423 | } |
- | |
1424 | - | ||
1425 | int cayman_resume(struct radeon_device *rdev) |
- | |
1426 | { |
- | |
1427 | int r; |
- | |
1428 | - | ||
1429 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, |
- | |
1430 | * posting will perform necessary task to bring back GPU into good |
- | |
1431 | * shape. |
- | |
1432 | */ |
- | |
1433 | /* post card */ |
- | |
1434 | atom_asic_init(rdev->mode_info.atom_context); |
- | |
1435 | - | ||
1436 | r = cayman_startup(rdev); |
- | |
1437 | if (r) { |
- | |
1438 | DRM_ERROR("cayman startup failed on resume\n"); |
- | |
1439 | return r; |
- | |
1440 | } |
- | |
1441 | - | ||
1442 | r = r600_ib_test(rdev); |
- | |
1443 | if (r) { |
- | |
1444 | DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
- | |
1445 | return r; |
- | |
1446 | } |
- | |
1447 | - | ||
1448 | return r; |
- | |
1449 | - | ||
1450 | } |
- | |
1451 | - | ||
1452 | int cayman_suspend(struct radeon_device *rdev) |
- | |
Line 1453... | Line -... | ||
1453 | { |
- | |
1454 | int r; |
- | |
1455 | - | ||
1456 | /* FIXME: we should wait for ring to be empty */ |
- | |
1457 | cayman_cp_enable(rdev, false); |
- | |
1458 | rdev->cp.ready = false; |
- | |
Line 1459... | Line -... | ||
1459 | evergreen_irq_suspend(rdev); |
- | |
1460 | radeon_wb_disable(rdev); |
- | |
1461 | cayman_pcie_gart_disable(rdev); |
- | |
1462 | - | ||
1463 | /* unpin shaders bo */ |
- | |
1464 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
- | |
Line 1465... | Line -... | ||
1465 | if (likely(r == 0)) { |
- | |
1466 | radeon_bo_unpin(rdev->r600_blit.shader_obj); |
- | |
Line 1467... | Line 1395... | ||
1467 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
1395 | } |
1468 | } |
1396 | |
1469 | 1397 | ||
1470 | return 0; |
1398 | |
Line 1512... | Line 1440... | ||
1512 | /* Initialize surface registers */ |
1440 | /* Initialize surface registers */ |
1513 | radeon_surface_init(rdev); |
1441 | radeon_surface_init(rdev); |
1514 | /* Initialize clocks */ |
1442 | /* Initialize clocks */ |
1515 | radeon_get_clock_info(rdev->ddev); |
1443 | radeon_get_clock_info(rdev->ddev); |
1516 | /* Fence driver */ |
1444 | /* Fence driver */ |
1517 | r = radeon_fence_driver_init(rdev); |
- | |
1518 | if (r) |
- | |
1519 | return r; |
- | |
1520 | /* initialize memory controller */ |
1445 | /* initialize memory controller */ |
1521 | r = evergreen_mc_init(rdev); |
1446 | r = evergreen_mc_init(rdev); |
1522 | if (r) |
1447 | if (r) |
1523 | return r; |
1448 | return r; |
1524 | /* Memory manager */ |
1449 | /* Memory manager */ |
1525 | r = radeon_bo_init(rdev); |
1450 | r = radeon_bo_init(rdev); |
1526 | if (r) |
1451 | if (r) |
1527 | return r; |
1452 | return r; |
Line 1528... | Line -... | ||
1528 | - | ||
1529 | r = radeon_irq_kms_init(rdev); |
- | |
1530 | if (r) |
- | |
Line 1531... | Line 1453... | ||
1531 | return r; |
1453 | |
1532 | 1454 | ||
Line 1533... | Line -... | ||
1533 | rdev->cp.ring_obj = NULL; |
- | |
1534 | r600_ring_init(rdev, 1024 * 1024); |
- | |
Line 1535... | Line 1455... | ||
1535 | 1455 | rdev->cp.ring_obj = NULL; |
|
1536 | rdev->ih.ring_obj = NULL; |
1456 | r600_ring_init(rdev, 1024 * 1024); |
1537 | r600_ih_ring_init(rdev, 64 * 1024); |
1457 | |
Line 1538... | Line 1458... | ||
1538 | 1458 | ||
1539 | r = r600_pcie_gart_init(rdev); |
1459 | r = r600_pcie_gart_init(rdev); |
1540 | if (r) |
1460 | if (r) |
1541 | return r; |
1461 | return r; |
1542 | - | ||
1543 | rdev->accel_working = true; |
- | |
1544 | r = cayman_startup(rdev); |
- | |
1545 | if (r) { |
- | |
1546 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
- | |
1547 | cayman_cp_fini(rdev); |
1462 | |
1548 | r600_irq_fini(rdev); |
1463 | rdev->accel_working = true; |
1549 | radeon_wb_fini(rdev); |
1464 | r = cayman_startup(rdev); |
1550 | radeon_irq_kms_fini(rdev); |
- | |
1551 | cayman_pcie_gart_fini(rdev); |
- | |
1552 | rdev->accel_working = false; |
- | |
1553 | } |
- | |
1554 | if (rdev->accel_working) { |
- | |
1555 | r = radeon_ib_pool_init(rdev); |
- | |
1556 | if (r) { |
- | |
1557 | DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); |
- | |
1558 | rdev->accel_working = false; |
- | |
1559 | } |
- | |
1560 | r = r600_ib_test(rdev); |
1465 | if (r) { |
Line 1561... | Line 1466... | ||
1561 | if (r) { |
1466 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
1562 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
1467 | rdev->accel_working = false; |
1563 | rdev->accel_working = false; |
1468 | } |
Line 1574... | Line 1479... | ||
1574 | } |
1479 | } |
Line 1575... | Line 1480... | ||
1575 | 1480 | ||
1576 | return 0; |
1481 | return 0; |
Line 1577... | Line -... | ||
1577 | } |
- | |
1578 | - | ||
1579 | void cayman_fini(struct radeon_device *rdev) |
- | |
1580 | { |
- | |
1581 | evergreen_blit_fini(rdev); |
- | |
1582 | cayman_cp_fini(rdev); |
- | |
1583 | r600_irq_fini(rdev); |
- | |
1584 | radeon_wb_fini(rdev); |
- | |
1585 | radeon_irq_kms_fini(rdev); |
- | |
1586 | cayman_pcie_gart_fini(rdev); |
- | |
1587 | radeon_gem_fini(rdev); |
- | |
1588 | radeon_fence_driver_fini(rdev); |
- | |
1589 | radeon_bo_fini(rdev); |
- | |
1590 | radeon_atombios_fini(rdev); |
- | |
1591 | kfree(rdev->bios); |
- | |
1592 | rdev->bios = NULL; |
- |