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Rev 5271 Rev 6104
Line 1167... Line 1167...
1167 
		if (ret)
 1167 
		if (ret)
1168 
			DRM_ERROR("kv_smc_bapm_enable failed\n");
 1168 
			DRM_ERROR("kv_smc_bapm_enable failed\n");
1169 
	}
 1169 
	}
1170 
}
 1170 
}
Line -... Line 1171...
- 
 
 1171 
 
- 
 
 1172 
static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable)
- 
 
 1173 
{
- 
 
 1174 
	u32 thermal_int;
- 
 
 1175 
 
- 
 
 1176 
	thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL);
- 
 
 1177 
	if (enable)
- 
 
 1178 
		thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;
- 
 
 1179 
	else
- 
 
 1180 
		thermal_int &= ~(THERM_INTH_MASK | THERM_INTL_MASK);
- 
 
 1181 
	WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);
- 
 
 1182 
 
- 
 
 1183 
}
1171 
 
 1184 
 
1172 
int kv_dpm_enable(struct radeon_device *rdev)
 1185 
int kv_dpm_enable(struct radeon_device *rdev)
1173 
{
 1186 
{
1174 
	struct kv_power_info *pi = kv_get_pi(rdev);
 1187 
	struct kv_power_info *pi = kv_get_pi(rdev);
Line 1278... Line 1291...
1278 
		ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
 1291 
		ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1279 
		if (ret) {
 1292 
		if (ret) {
1280 
			DRM_ERROR("kv_set_thermal_temperature_range failed\n");
 1293 
			DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1281 
			return ret;
 1294 
			return ret;
1282 
		}
 1295 
		}
1283 
		rdev->irq.dpm_thermal = true;
 1296 
		kv_enable_thermal_int(rdev, true);
1284 
		radeon_irq_set(rdev);
 - 
 
1285 
	}
 1297 
	}
Line 1286... Line 1298...
1286 
 
 1298 
 
1287 
	/* powerdown unused blocks for now */
 1299 
	/* powerdown unused blocks for now */
1288 
	kv_dpm_powergate_acp(rdev, true);
 1300 
	kv_dpm_powergate_acp(rdev, true);
Line 1310... Line 1322...
1310 
	kv_enable_didt(rdev, false);
 1322 
	kv_enable_didt(rdev, false);
1311 
	kv_clear_vc(rdev);
 1323 
	kv_clear_vc(rdev);
1312 
	kv_stop_dpm(rdev);
 1324 
	kv_stop_dpm(rdev);
1313 
	kv_enable_ulv(rdev, false);
 1325 
	kv_enable_ulv(rdev, false);
1314 
	kv_reset_am(rdev);
 1326 
	kv_reset_am(rdev);
- 
 
 1327 
	kv_enable_thermal_int(rdev, false);
Line 1315... Line 1328...
1315 
 
 1328 
 
1316 
	kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
 1329 
	kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
Line 1317... Line 1330...
1317 
}
 1330 
}
Line 1923... Line 1936...
1923 
	sumo_take_smu_control(rdev, true);
 1936 
	sumo_take_smu_control(rdev, true);
1924 
	kv_init_powergate_state(rdev);
 1937 
	kv_init_powergate_state(rdev);
1925 
	kv_init_sclk_t(rdev);
 1938 
	kv_init_sclk_t(rdev);
1926 
}
 1939 
}
Line -... Line 1940...
- 
 
 1940 
 
1927 
 
 1941 
#if 0
1928 
void kv_dpm_reset_asic(struct radeon_device *rdev)
 1942 
void kv_dpm_reset_asic(struct radeon_device *rdev)
1929 
{
 1943 
{
Line 1930... Line 1944...
1930 
	struct kv_power_info *pi = kv_get_pi(rdev);
 1944 
	struct kv_power_info *pi = kv_get_pi(rdev);
Line 1943... Line 1957...
1943 
		kv_upload_dpm_settings(rdev);
 1957 
		kv_upload_dpm_settings(rdev);
1944 
		kv_freeze_sclk_dpm(rdev, false);
 1958 
		kv_freeze_sclk_dpm(rdev, false);
1945 
		kv_set_enabled_level(rdev, pi->graphics_boot_level);
 1959 
		kv_set_enabled_level(rdev, pi->graphics_boot_level);
1946 
	}
 1960 
	}
1947 
}
 1961 
}
- 
 
 1962 
#endif
Line 1948... Line 1963...
1948 
 
 1963 
 
Line 1949... Line 1964...
1949 
//XXX use sumo_dpm_display_configuration_changed
 1964 
//XXX use sumo_dpm_display_configuration_changed
1950 
 
 1965 
 
Line 2743... Line 2758...
2743 
 
 2758 
 
2744 
	pi->caps_sclk_ds = true;
 2759 
	pi->caps_sclk_ds = true;
2745 
	pi->enable_auto_thermal_throttling = true;
 2760 
	pi->enable_auto_thermal_throttling = true;
2746 
	pi->disable_nb_ps3_in_battery = false;
 2761 
	pi->disable_nb_ps3_in_battery = false;
2747 
	if (radeon_bapm == -1) {
 - 
 
2748 
		/* There are stability issues reported on with
 2762 
	if (radeon_bapm == -1) {
2749 
		 * bapm enabled on an asrock system.
 - 
 
2750 
		 */
 2763 
		/* only enable bapm on KB, ML by default */
2751 
		if (rdev->pdev->subsystem_vendor == 0x1849)
 - 
 
2752 
		pi->bapm_enable = false;
 - 
 
2753 
	else
 2764 
		if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
- 
 
 2765 
			pi->bapm_enable = true;
- 
 
 2766 
		else
2754 
	pi->bapm_enable = true;
 2767 
			pi->bapm_enable = false;
2755 
	} else if (radeon_bapm == 0) {
 2768 
	} else if (radeon_bapm == 0) {
2756 
		pi->bapm_enable = false;
 2769 
		pi->bapm_enable = false;
2757 
	} else {
 2770 
	} else {
2758 
		pi->bapm_enable = true;
 2771 
		pi->bapm_enable = true;
Line 2805... Line 2818...
2805 
		seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
 2818 
		seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
2806 
			   current_index, sclk, vddc);
 2819 
			   current_index, sclk, vddc);
2807 
	}
 2820 
	}
2808 
}
 2821 
}
Line -... Line 2822...
- 
 
 2822 
 
- 
 
 2823 
u32 kv_dpm_get_current_sclk(struct radeon_device *rdev)
- 
 
 2824 
{
- 
 
 2825 
	struct kv_power_info *pi = kv_get_pi(rdev);
- 
 
 2826 
	u32 current_index =
- 
 
 2827 
		(RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
- 
 
 2828 
		CURR_SCLK_INDEX_SHIFT;
- 
 
 2829 
	u32 sclk;
- 
 
 2830 
 
- 
 
 2831 
	if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
- 
 
 2832 
		return 0;
- 
 
 2833 
	} else {
- 
 
 2834 
		sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
- 
 
 2835 
		return sclk;
- 
 
 2836 
	}
- 
 
 2837 
}
- 
 
 2838 
 
- 
 
 2839 
u32 kv_dpm_get_current_mclk(struct radeon_device *rdev)
- 
 
 2840 
{
- 
 
 2841 
	struct kv_power_info *pi = kv_get_pi(rdev);
- 
 
 2842 
 
- 
 
 2843 
	return pi->sys_info.bootup_uma_clk;
- 
 
 2844 
}
2809 
 
 2845 
 
2810 
void kv_dpm_print_power_state(struct radeon_device *rdev,
 2846 
void kv_dpm_print_power_state(struct radeon_device *rdev,
2811 
			      struct radeon_ps *rps)
 2847 
			      struct radeon_ps *rps)
2812 
{
 2848 
{
2813 
	int i;
 2849 
	int i;