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Rev 5078 Rev 5139
Line 31... Line 31...
31 
 
 31 
 
32 
#define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
 32 
#define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
33 
#define KV_MINIMUM_ENGINE_CLOCK         800
 33 
#define KV_MINIMUM_ENGINE_CLOCK         800
Line -... Line 34...
- 
 
 34 
#define SMC_RAM_END                     0x40000
- 
 
 35 
 
34 
#define SMC_RAM_END                     0x40000
 36 
static int kv_enable_nb_dpm(struct radeon_device *rdev,
35 
 
 37 
			    bool enable);
36 
static void kv_init_graphics_levels(struct radeon_device *rdev);
 38 
static void kv_init_graphics_levels(struct radeon_device *rdev);
37 
static int kv_calculate_ds_divider(struct radeon_device *rdev);
 39 
static int kv_calculate_ds_divider(struct radeon_device *rdev);
38 
static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
 40 
static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
Line 1293... Line 1295...
1293 
 
 1295 
 
1294 
void kv_dpm_disable(struct radeon_device *rdev)
 1296 
void kv_dpm_disable(struct radeon_device *rdev)
1295 
{
 1297 
{
Line -... Line 1298...
- 
 
 1298 
	kv_smc_bapm_enable(rdev, false);
- 
 
 1299 
 
- 
 
 1300 
	if (rdev->family == CHIP_MULLINS)
1296 
	kv_smc_bapm_enable(rdev, false);
 1301 
		kv_enable_nb_dpm(rdev, false);
1297 
 
 1302 
 
1298 
	/* powerup blocks */
 1303 
	/* powerup blocks */
1299 
	kv_dpm_powergate_acp(rdev, false);
 1304 
	kv_dpm_powergate_acp(rdev, false);
1300 
	kv_dpm_powergate_samu(rdev, false);
 1305 
	kv_dpm_powergate_samu(rdev, false);
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1767 
	}
 1772 
	}
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1768 
 
 1773 
 
1769 
	return ret;
 1774 
	return ret;
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1770 
}
 1775 
}
- 
 
 1776 
 
1771 
 
 1777 
static int kv_enable_nb_dpm(struct radeon_device *rdev,
1772 
static int kv_enable_nb_dpm(struct radeon_device *rdev)
 1778 
			    bool enable)
1773 
{
 1779 
{
Line -... Line 1780...
- 
 
 1780 
	struct kv_power_info *pi = kv_get_pi(rdev);
1774 
	struct kv_power_info *pi = kv_get_pi(rdev);
 1781 
	int ret = 0;
1775 
	int ret = 0;
 1782 
 
1776 
 
 1783 
	if (enable) {
1777 
	if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
 1784 
	if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1778 
		ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
 1785 
		ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
- 
 
 1786 
		if (ret == 0)
- 
 
 1787 
			pi->nb_dpm_enabled = true;
- 
 
 1788 
	}
- 
 
 1789 
	} else {
- 
 
 1790 
		if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
- 
 
 1791 
			ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable);
- 
 
 1792 
			if (ret == 0)
Line 1779... Line 1793...
1779 
		if (ret == 0)
 1793 
				pi->nb_dpm_enabled = false;
1780 
			pi->nb_dpm_enabled = true;
 1794 
		}
Line 1781... Line 1795...
1781 
	}
 1795 
	}
Line 1862... Line 1876...
1862 
				DRM_ERROR("kv_update_vce_dpm failed\n");
 1876 
				DRM_ERROR("kv_update_vce_dpm failed\n");
1863 
				return ret;
 1877 
				return ret;
1864 
			}
 1878 
			}
1865 
			kv_update_sclk_t(rdev);
 1879 
			kv_update_sclk_t(rdev);
1866 
			if (rdev->family == CHIP_MULLINS)
 1880 
			if (rdev->family == CHIP_MULLINS)
1867 
				kv_enable_nb_dpm(rdev);
 1881 
				kv_enable_nb_dpm(rdev, true);
1868 
		}
 1882 
		}
1869 
	} else {
 1883 
	} else {
1870 
		if (pi->enable_dpm) {
 1884 
		if (pi->enable_dpm) {
1871 
			kv_set_valid_clock_range(rdev, new_ps);
 1885 
			kv_set_valid_clock_range(rdev, new_ps);
1872 
			kv_update_dfs_bypass_settings(rdev, new_ps);
 1886 
			kv_update_dfs_bypass_settings(rdev, new_ps);
Line 1887... Line 1901...
1887 
				DRM_ERROR("kv_update_vce_dpm failed\n");
 1901 
				DRM_ERROR("kv_update_vce_dpm failed\n");
1888 
				return ret;
 1902 
				return ret;
1889 
			}
 1903 
			}
1890 
			kv_update_acp_boot_level(rdev);
 1904 
			kv_update_acp_boot_level(rdev);
1891 
			kv_update_sclk_t(rdev);
 1905 
			kv_update_sclk_t(rdev);
1892 
			kv_enable_nb_dpm(rdev);
 1906 
			kv_enable_nb_dpm(rdev, true);
1893 
		}
 1907 
		}
1894 
	}
 1908 
	}
Line 1895... Line 1909...
1895 
 
 1909 
 
1896 
	return 0;
 1910 
	return 0;