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Line 46... | Line 46... | ||
46 | #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 |
46 | #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 |
47 | #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 |
47 | #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 |
48 | #define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
48 | #define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
49 | #define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
49 | #define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
Line -... | Line 50... | ||
- | 50 | ||
- | 51 | /* pm registers */ |
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- | 52 | #define SMC_MSG 0x20c |
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- | 53 | #define HOST_SMC_MSG(x) ((x) << 0) |
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- | 54 | #define HOST_SMC_MSG_MASK (0xff << 0) |
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- | 55 | #define HOST_SMC_MSG_SHIFT 0 |
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- | 56 | #define HOST_SMC_RESP(x) ((x) << 8) |
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- | 57 | #define HOST_SMC_RESP_MASK (0xff << 8) |
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- | 58 | #define HOST_SMC_RESP_SHIFT 8 |
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- | 59 | #define SMC_HOST_MSG(x) ((x) << 16) |
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- | 60 | #define SMC_HOST_MSG_MASK (0xff << 16) |
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- | 61 | #define SMC_HOST_MSG_SHIFT 16 |
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- | 62 | #define SMC_HOST_RESP(x) ((x) << 24) |
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- | 63 | #define SMC_HOST_RESP_MASK (0xff << 24) |
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- | 64 | #define SMC_HOST_RESP_SHIFT 24 |
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- | 65 | ||
- | 66 | #define DCCG_DISP_SLOW_SELECT_REG 0x4fc |
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- | 67 | #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) |
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- | 68 | #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) |
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- | 69 | #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 |
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- | 70 | #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) |
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- | 71 | #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) |
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- | 72 | #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 |
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- | 73 | ||
- | 74 | #define CG_SPLL_FUNC_CNTL 0x600 |
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- | 75 | #define SPLL_RESET (1 << 0) |
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- | 76 | #define SPLL_SLEEP (1 << 1) |
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- | 77 | #define SPLL_BYPASS_EN (1 << 3) |
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- | 78 | #define SPLL_REF_DIV(x) ((x) << 4) |
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- | 79 | #define SPLL_REF_DIV_MASK (0x3f << 4) |
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- | 80 | #define SPLL_PDIV_A(x) ((x) << 20) |
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- | 81 | #define SPLL_PDIV_A_MASK (0x7f << 20) |
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- | 82 | #define CG_SPLL_FUNC_CNTL_2 0x604 |
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- | 83 | #define SCLK_MUX_SEL(x) ((x) << 0) |
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- | 84 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) |
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- | 85 | #define SCLK_MUX_UPDATE (1 << 26) |
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- | 86 | #define CG_SPLL_FUNC_CNTL_3 0x608 |
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- | 87 | #define SPLL_FB_DIV(x) ((x) << 0) |
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- | 88 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) |
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- | 89 | #define SPLL_DITHEN (1 << 28) |
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- | 90 | #define CG_SPLL_STATUS 0x60c |
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- | 91 | #define SPLL_CHG_STATUS (1 << 1) |
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- | 92 | ||
- | 93 | #define MPLL_CNTL_MODE 0x61c |
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- | 94 | # define MPLL_MCLK_SEL (1 << 11) |
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- | 95 | # define SS_SSEN (1 << 24) |
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- | 96 | # define SS_DSMODE_EN (1 << 25) |
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- | 97 | ||
- | 98 | #define MPLL_AD_FUNC_CNTL 0x624 |
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- | 99 | #define CLKF(x) ((x) << 0) |
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- | 100 | #define CLKF_MASK (0x7f << 0) |
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- | 101 | #define CLKR(x) ((x) << 7) |
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- | 102 | #define CLKR_MASK (0x1f << 7) |
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- | 103 | #define CLKFRAC(x) ((x) << 12) |
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- | 104 | #define CLKFRAC_MASK (0x1f << 12) |
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- | 105 | #define YCLK_POST_DIV(x) ((x) << 17) |
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- | 106 | #define YCLK_POST_DIV_MASK (3 << 17) |
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- | 107 | #define IBIAS(x) ((x) << 20) |
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- | 108 | #define IBIAS_MASK (0x3ff << 20) |
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- | 109 | #define RESET (1 << 30) |
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- | 110 | #define PDNB (1 << 31) |
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- | 111 | #define MPLL_AD_FUNC_CNTL_2 0x628 |
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- | 112 | #define BYPASS (1 << 19) |
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- | 113 | #define BIAS_GEN_PDNB (1 << 24) |
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- | 114 | #define RESET_EN (1 << 25) |
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- | 115 | #define VCO_MODE (1 << 29) |
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- | 116 | #define MPLL_DQ_FUNC_CNTL 0x62c |
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- | 117 | #define MPLL_DQ_FUNC_CNTL_2 0x630 |
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- | 118 | ||
- | 119 | #define GENERAL_PWRMGT 0x63c |
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- | 120 | # define GLOBAL_PWRMGT_EN (1 << 0) |
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- | 121 | # define STATIC_PM_EN (1 << 1) |
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- | 122 | # define THERMAL_PROTECTION_DIS (1 << 2) |
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- | 123 | # define THERMAL_PROTECTION_TYPE (1 << 3) |
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- | 124 | # define ENABLE_GEN2PCIE (1 << 4) |
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- | 125 | # define ENABLE_GEN2XSP (1 << 5) |
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- | 126 | # define SW_SMIO_INDEX(x) ((x) << 6) |
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- | 127 | # define SW_SMIO_INDEX_MASK (3 << 6) |
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- | 128 | # define SW_SMIO_INDEX_SHIFT 6 |
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- | 129 | # define LOW_VOLT_D2_ACPI (1 << 8) |
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- | 130 | # define LOW_VOLT_D3_ACPI (1 << 9) |
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- | 131 | # define VOLT_PWRMGT_EN (1 << 10) |
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- | 132 | # define BACKBIAS_PAD_EN (1 << 18) |
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- | 133 | # define BACKBIAS_VALUE (1 << 19) |
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- | 134 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) |
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- | 135 | # define AC_DC_SW (1 << 24) |
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- | 136 | ||
- | 137 | #define SCLK_PWRMGT_CNTL 0x644 |
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- | 138 | # define SCLK_PWRMGT_OFF (1 << 0) |
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- | 139 | # define SCLK_LOW_D1 (1 << 1) |
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- | 140 | # define FIR_RESET (1 << 4) |
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- | 141 | # define FIR_FORCE_TREND_SEL (1 << 5) |
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- | 142 | # define FIR_TREND_MODE (1 << 6) |
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- | 143 | # define DYN_GFX_CLK_OFF_EN (1 << 7) |
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- | 144 | # define GFX_CLK_FORCE_ON (1 << 8) |
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- | 145 | # define GFX_CLK_REQUEST_OFF (1 << 9) |
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- | 146 | # define GFX_CLK_FORCE_OFF (1 << 10) |
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- | 147 | # define GFX_CLK_OFF_ACPI_D1 (1 << 11) |
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- | 148 | # define GFX_CLK_OFF_ACPI_D2 (1 << 12) |
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- | 149 | # define GFX_CLK_OFF_ACPI_D3 (1 << 13) |
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- | 150 | # define DYN_LIGHT_SLEEP_EN (1 << 14) |
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- | 151 | #define MCLK_PWRMGT_CNTL 0x648 |
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- | 152 | # define DLL_SPEED(x) ((x) << 0) |
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- | 153 | # define DLL_SPEED_MASK (0x1f << 0) |
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- | 154 | # define MPLL_PWRMGT_OFF (1 << 5) |
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- | 155 | # define DLL_READY (1 << 6) |
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- | 156 | # define MC_INT_CNTL (1 << 7) |
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- | 157 | # define MRDCKA0_PDNB (1 << 8) |
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- | 158 | # define MRDCKA1_PDNB (1 << 9) |
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- | 159 | # define MRDCKB0_PDNB (1 << 10) |
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- | 160 | # define MRDCKB1_PDNB (1 << 11) |
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- | 161 | # define MRDCKC0_PDNB (1 << 12) |
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- | 162 | # define MRDCKC1_PDNB (1 << 13) |
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- | 163 | # define MRDCKD0_PDNB (1 << 14) |
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- | 164 | # define MRDCKD1_PDNB (1 << 15) |
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- | 165 | # define MRDCKA0_RESET (1 << 16) |
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- | 166 | # define MRDCKA1_RESET (1 << 17) |
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- | 167 | # define MRDCKB0_RESET (1 << 18) |
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- | 168 | # define MRDCKB1_RESET (1 << 19) |
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- | 169 | # define MRDCKC0_RESET (1 << 20) |
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- | 170 | # define MRDCKC1_RESET (1 << 21) |
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- | 171 | # define MRDCKD0_RESET (1 << 22) |
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- | 172 | # define MRDCKD1_RESET (1 << 23) |
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- | 173 | # define DLL_READY_READ (1 << 24) |
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- | 174 | # define USE_DISPLAY_GAP (1 << 25) |
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- | 175 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) |
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- | 176 | # define MPLL_TURNOFF_D2 (1 << 28) |
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- | 177 | #define DLL_CNTL 0x64c |
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- | 178 | # define MRDCKA0_BYPASS (1 << 24) |
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- | 179 | # define MRDCKA1_BYPASS (1 << 25) |
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- | 180 | # define MRDCKB0_BYPASS (1 << 26) |
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- | 181 | # define MRDCKB1_BYPASS (1 << 27) |
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- | 182 | # define MRDCKC0_BYPASS (1 << 28) |
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- | 183 | # define MRDCKC1_BYPASS (1 << 29) |
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- | 184 | # define MRDCKD0_BYPASS (1 << 30) |
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- | 185 | # define MRDCKD1_BYPASS (1 << 31) |
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- | 186 | ||
- | 187 | #define CG_AT 0x6d4 |
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- | 188 | # define CG_R(x) ((x) << 0) |
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- | 189 | # define CG_R_MASK (0xffff << 0) |
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- | 190 | # define CG_L(x) ((x) << 16) |
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- | 191 | # define CG_L_MASK (0xffff << 16) |
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- | 192 | ||
- | 193 | #define CG_DISPLAY_GAP_CNTL 0x714 |
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- | 194 | # define DISP1_GAP(x) ((x) << 0) |
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- | 195 | # define DISP1_GAP_MASK (3 << 0) |
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- | 196 | # define DISP2_GAP(x) ((x) << 2) |
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- | 197 | # define DISP2_GAP_MASK (3 << 2) |
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- | 198 | # define VBI_TIMER_COUNT(x) ((x) << 4) |
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- | 199 | # define VBI_TIMER_COUNT_MASK (0x3fff << 4) |
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- | 200 | # define VBI_TIMER_UNIT(x) ((x) << 20) |
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- | 201 | # define VBI_TIMER_UNIT_MASK (7 << 20) |
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- | 202 | # define DISP1_GAP_MCHG(x) ((x) << 24) |
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- | 203 | # define DISP1_GAP_MCHG_MASK (3 << 24) |
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- | 204 | # define DISP2_GAP_MCHG(x) ((x) << 26) |
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- | 205 | # define DISP2_GAP_MCHG_MASK (3 << 26) |
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- | 206 | ||
- | 207 | #define CG_BIF_REQ_AND_RSP 0x7f4 |
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- | 208 | #define CG_CLIENT_REQ(x) ((x) << 0) |
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- | 209 | #define CG_CLIENT_REQ_MASK (0xff << 0) |
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- | 210 | #define CG_CLIENT_REQ_SHIFT 0 |
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- | 211 | #define CG_CLIENT_RESP(x) ((x) << 8) |
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- | 212 | #define CG_CLIENT_RESP_MASK (0xff << 8) |
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- | 213 | #define CG_CLIENT_RESP_SHIFT 8 |
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- | 214 | #define CLIENT_CG_REQ(x) ((x) << 16) |
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- | 215 | #define CLIENT_CG_REQ_MASK (0xff << 16) |
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- | 216 | #define CLIENT_CG_REQ_SHIFT 16 |
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- | 217 | #define CLIENT_CG_RESP(x) ((x) << 24) |
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- | 218 | #define CLIENT_CG_RESP_MASK (0xff << 24) |
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- | 219 | #define CLIENT_CG_RESP_SHIFT 24 |
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- | 220 | ||
- | 221 | #define CG_SPLL_SPREAD_SPECTRUM 0x790 |
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- | 222 | #define SSEN (1 << 0) |
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- | 223 | #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 |
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- | 224 | ||
- | 225 | #define MPLL_SS1 0x85c |
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- | 226 | #define CLKV(x) ((x) << 0) |
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- | 227 | #define CLKV_MASK (0x3ffffff << 0) |
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- | 228 | #define MPLL_SS2 0x860 |
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- | 229 | #define CLKS(x) ((x) << 0) |
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- | 230 | #define CLKS_MASK (0xfff << 0) |
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- | 231 | ||
- | 232 | #define CG_IND_ADDR 0x8f8 |
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- | 233 | #define CG_IND_DATA 0x8fc |
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- | 234 | /* CGIND regs */ |
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- | 235 | #define CG_CGTT_LOCAL_0 0x00 |
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- | 236 | #define CG_CGTT_LOCAL_1 0x01 |
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- | 237 | #define CG_CGTT_LOCAL_2 0x02 |
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- | 238 | #define CG_CGTT_LOCAL_3 0x03 |
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- | 239 | #define CG_CGLS_TILE_0 0x20 |
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- | 240 | #define CG_CGLS_TILE_1 0x21 |
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- | 241 | #define CG_CGLS_TILE_2 0x22 |
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- | 242 | #define CG_CGLS_TILE_3 0x23 |
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- | 243 | #define CG_CGLS_TILE_4 0x24 |
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- | 244 | #define CG_CGLS_TILE_5 0x25 |
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- | 245 | #define CG_CGLS_TILE_6 0x26 |
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- | 246 | #define CG_CGLS_TILE_7 0x27 |
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- | 247 | #define CG_CGLS_TILE_8 0x28 |
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- | 248 | #define CG_CGLS_TILE_9 0x29 |
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- | 249 | #define CG_CGLS_TILE_10 0x2a |
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- | 250 | #define CG_CGLS_TILE_11 0x2b |
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- | 251 | ||
- | 252 | #define VM_L2_CG 0x15c0 |
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- | 253 | ||
- | 254 | #define MC_CONFIG 0x2000 |
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- | 255 | ||
- | 256 | #define MC_CONFIG_MCD 0x20a0 |
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- | 257 | #define MC_CG_CONFIG_MCD 0x20a4 |
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- | 258 | #define MC_RD_ENABLE_MCD(x) ((x) << 8) |
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- | 259 | #define MC_RD_ENABLE_MCD_MASK (7 << 8) |
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- | 260 | ||
- | 261 | #define MC_HUB_MISC_HUB_CG 0x20b8 |
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- | 262 | #define MC_HUB_MISC_VM_CG 0x20bc |
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- | 263 | #define MC_HUB_MISC_SIP_CG 0x20c0 |
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- | 264 | ||
- | 265 | #define MC_XPB_CLK_GAT 0x2478 |
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- | 266 | ||
- | 267 | #define MC_CG_CONFIG 0x25bc |
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- | 268 | #define MC_RD_ENABLE(x) ((x) << 4) |
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- | 269 | #define MC_RD_ENABLE_MASK (3 << 4) |
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- | 270 | ||
- | 271 | #define MC_CITF_MISC_RD_CG 0x2648 |
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- | 272 | #define MC_CITF_MISC_WR_CG 0x264c |
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- | 273 | #define MC_CITF_MISC_VM_CG 0x2650 |
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- | 274 | # define MEM_LS_ENABLE (1 << 19) |
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- | 275 | ||
- | 276 | #define MC_ARB_BURST_TIME 0x2808 |
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- | 277 | #define STATE0(x) ((x) << 0) |
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- | 278 | #define STATE0_MASK (0x1f << 0) |
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- | 279 | #define STATE1(x) ((x) << 5) |
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- | 280 | #define STATE1_MASK (0x1f << 5) |
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- | 281 | #define STATE2(x) ((x) << 10) |
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- | 282 | #define STATE2_MASK (0x1f << 10) |
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- | 283 | #define STATE3(x) ((x) << 15) |
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- | 284 | #define STATE3_MASK (0x1f << 15) |
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- | 285 | ||
- | 286 | #define MC_SEQ_RAS_TIMING 0x28a0 |
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- | 287 | #define MC_SEQ_CAS_TIMING 0x28a4 |
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- | 288 | #define MC_SEQ_MISC_TIMING 0x28a8 |
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- | 289 | #define MC_SEQ_MISC_TIMING2 0x28ac |
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- | 290 | ||
- | 291 | #define MC_SEQ_RD_CTL_D0 0x28b4 |
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- | 292 | #define MC_SEQ_RD_CTL_D1 0x28b8 |
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- | 293 | #define MC_SEQ_WR_CTL_D0 0x28bc |
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- | 294 | #define MC_SEQ_WR_CTL_D1 0x28c0 |
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- | 295 | ||
- | 296 | #define MC_SEQ_STATUS_M 0x29f4 |
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- | 297 | # define PMG_PWRSTATE (1 << 16) |
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- | 298 | ||
- | 299 | #define MC_SEQ_MISC1 0x2a04 |
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- | 300 | #define MC_SEQ_RESERVE_M 0x2a08 |
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- | 301 | #define MC_PMG_CMD_EMRS 0x2a0c |
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- | 302 | ||
- | 303 | #define MC_SEQ_MISC3 0x2a2c |
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- | 304 | ||
- | 305 | #define MC_SEQ_MISC5 0x2a54 |
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- | 306 | #define MC_SEQ_MISC6 0x2a58 |
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- | 307 | ||
- | 308 | #define MC_SEQ_MISC7 0x2a64 |
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- | 309 | ||
- | 310 | #define MC_SEQ_CG 0x2a68 |
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- | 311 | #define CG_SEQ_REQ(x) ((x) << 0) |
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- | 312 | #define CG_SEQ_REQ_MASK (0xff << 0) |
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- | 313 | #define CG_SEQ_REQ_SHIFT 0 |
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- | 314 | #define CG_SEQ_RESP(x) ((x) << 8) |
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- | 315 | #define CG_SEQ_RESP_MASK (0xff << 8) |
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- | 316 | #define CG_SEQ_RESP_SHIFT 8 |
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- | 317 | #define SEQ_CG_REQ(x) ((x) << 16) |
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- | 318 | #define SEQ_CG_REQ_MASK (0xff << 16) |
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- | 319 | #define SEQ_CG_REQ_SHIFT 16 |
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- | 320 | #define SEQ_CG_RESP(x) ((x) << 24) |
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- | 321 | #define SEQ_CG_RESP_MASK (0xff << 24) |
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- | 322 | #define SEQ_CG_RESP_SHIFT 24 |
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- | 323 | #define MC_SEQ_RAS_TIMING_LP 0x2a6c |
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- | 324 | #define MC_SEQ_CAS_TIMING_LP 0x2a70 |
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- | 325 | #define MC_SEQ_MISC_TIMING_LP 0x2a74 |
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- | 326 | #define MC_SEQ_MISC_TIMING2_LP 0x2a78 |
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- | 327 | #define MC_SEQ_WR_CTL_D0_LP 0x2a7c |
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- | 328 | #define MC_SEQ_WR_CTL_D1_LP 0x2a80 |
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- | 329 | #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 |
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- | 330 | #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 |
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- | 331 | ||
- | 332 | #define MC_PMG_CMD_MRS 0x2aac |
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- | 333 | ||
- | 334 | #define MC_SEQ_RD_CTL_D0_LP 0x2b1c |
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- | 335 | #define MC_SEQ_RD_CTL_D1_LP 0x2b20 |
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- | 336 | ||
- | 337 | #define MC_PMG_CMD_MRS1 0x2b44 |
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- | 338 | #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 |
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- | 339 | ||
- | 340 | #define CGTS_SM_CTRL_REG 0x9150 |
|
50 | 341 | ||
Line 51... | Line 342... | ||
51 | /* Registers */ |
342 | /* Registers */ |
52 | 343 | ||
Line 88... | Line 379... | ||
88 | # define DCLK_STATUS (1 << 0) |
379 | # define DCLK_STATUS (1 << 0) |
89 | #define CG_VCLK_CNTL 0x618 |
380 | #define CG_VCLK_CNTL 0x618 |
90 | #define CG_VCLK_STATUS 0x61c |
381 | #define CG_VCLK_STATUS 0x61c |
91 | #define CG_SCRATCH1 0x820 |
382 | #define CG_SCRATCH1 0x820 |
Line -... | Line 383... | ||
- | 383 | ||
- | 384 | #define RLC_CNTL 0x3f00 |
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- | 385 | # define RLC_ENABLE (1 << 0) |
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- | 386 | # define GFX_POWER_GATING_ENABLE (1 << 7) |
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- | 387 | # define GFX_POWER_GATING_SRC (1 << 8) |
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- | 388 | # define DYN_PER_SIMD_PG_ENABLE (1 << 27) |
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- | 389 | # define LB_CNT_SPIM_ACTIVE (1 << 30) |
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- | 390 | # define LOAD_BALANCE_ENABLE (1 << 31) |
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- | 391 | ||
- | 392 | #define RLC_HB_BASE 0x3f10 |
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- | 393 | #define RLC_HB_CNTL 0x3f0c |
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- | 394 | #define RLC_HB_RPTR 0x3f20 |
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- | 395 | #define RLC_HB_WPTR 0x3f1c |
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- | 396 | #define RLC_HB_WPTR_LSB_ADDR 0x3f14 |
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- | 397 | #define RLC_HB_WPTR_MSB_ADDR 0x3f18 |
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- | 398 | #define RLC_MC_CNTL 0x3f44 |
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- | 399 | #define RLC_UCODE_CNTL 0x3f48 |
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- | 400 | #define RLC_UCODE_ADDR 0x3f2c |
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- | 401 | #define RLC_UCODE_DATA 0x3f30 |
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- | 402 | ||
- | 403 | /* new for TN */ |
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- | 404 | #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 |
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- | 405 | #define TN_RLC_LB_CNTR_MAX 0x3f14 |
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- | 406 | #define TN_RLC_LB_CNTR_INIT 0x3f18 |
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- | 407 | #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 |
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- | 408 | #define TN_RLC_LB_INIT_SIMD_MASK 0x3fe4 |
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- | 409 | #define TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK 0x3fe8 |
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- | 410 | #define TN_RLC_LB_PARAMS 0x3fec |
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92 | 411 | ||
93 | #define GRBM_GFX_INDEX 0x802C |
412 | #define GRBM_GFX_INDEX 0x802C |
94 | #define INSTANCE_INDEX(x) ((x) << 0) |
413 | #define INSTANCE_INDEX(x) ((x) << 0) |
95 | #define SE_INDEX(x) ((x) << 16) |
414 | #define SE_INDEX(x) ((x) << 16) |
96 | #define INSTANCE_BROADCAST_WRITES (1 << 30) |
415 | #define INSTANCE_BROADCAST_WRITES (1 << 30) |
Line 180... | Line 499... | ||
180 | 499 | ||
181 | #define DCCG_AUDIO_DTO0_PHASE 0x05b0 |
500 | #define DCCG_AUDIO_DTO0_PHASE 0x05b0 |
182 | #define DCCG_AUDIO_DTO0_MODULE 0x05b4 |
501 | #define DCCG_AUDIO_DTO0_MODULE 0x05b4 |
183 | #define DCCG_AUDIO_DTO0_LOAD 0x05b8 |
502 | #define DCCG_AUDIO_DTO0_LOAD 0x05b8 |
- | 503 | #define DCCG_AUDIO_DTO0_CNTL 0x05bc |
|
- | 504 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) |
|
- | 505 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 |
|
Line 184... | Line 506... | ||
184 | #define DCCG_AUDIO_DTO0_CNTL 0x05bc |
506 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 |
185 | 507 | ||
186 | #define DCCG_AUDIO_DTO1_PHASE 0x05c0 |
508 | #define DCCG_AUDIO_DTO1_PHASE 0x05c0 |
187 | #define DCCG_AUDIO_DTO1_MODULE 0x05c4 |
509 | #define DCCG_AUDIO_DTO1_MODULE 0x05c4 |
Line 193... | Line 515... | ||
193 | # define HDMI_KEEPOUT_MODE (1 << 0) |
515 | # define HDMI_KEEPOUT_MODE (1 << 0) |
194 | # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ |
516 | # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ |
195 | # define HDMI_ERROR_ACK (1 << 8) |
517 | # define HDMI_ERROR_ACK (1 << 8) |
196 | # define HDMI_ERROR_MASK (1 << 9) |
518 | # define HDMI_ERROR_MASK (1 << 9) |
197 | # define HDMI_DEEP_COLOR_ENABLE (1 << 24) |
519 | # define HDMI_DEEP_COLOR_ENABLE (1 << 24) |
198 | # define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28) |
520 | # define HDMI_DEEP_COLOR_DEPTH(x) (((x) & 3) << 28) |
199 | # define HDMI_24BIT_DEEP_COLOR 0 |
521 | # define HDMI_24BIT_DEEP_COLOR 0 |
200 | # define HDMI_30BIT_DEEP_COLOR 1 |
522 | # define HDMI_30BIT_DEEP_COLOR 1 |
201 | # define HDMI_36BIT_DEEP_COLOR 2 |
523 | # define HDMI_36BIT_DEEP_COLOR 2 |
- | 524 | # define HDMI_DEEP_COLOR_DEPTH_MASK (3 << 28) |
|
202 | #define HDMI_STATUS 0x7034 |
525 | #define HDMI_STATUS 0x7034 |
203 | # define HDMI_ACTIVE_AVMUTE (1 << 0) |
526 | # define HDMI_ACTIVE_AVMUTE (1 << 0) |
204 | # define HDMI_AUDIO_PACKET_ERROR (1 << 16) |
527 | # define HDMI_AUDIO_PACKET_ERROR (1 << 16) |
205 | # define HDMI_VBI_PACKET_ERROR (1 << 20) |
528 | # define HDMI_VBI_PACKET_ERROR (1 << 20) |
206 | #define HDMI_AUDIO_PACKET_CONTROL 0x7038 |
529 | #define HDMI_AUDIO_PACKET_CONTROL 0x7038 |
Line 394... | Line 717... | ||
394 | # define AFMT_AUDIO_INFO_UPDATE (1 << 7) |
717 | # define AFMT_AUDIO_INFO_UPDATE (1 << 7) |
395 | # define AFMT_MPEG_INFO_UPDATE (1 << 10) |
718 | # define AFMT_MPEG_INFO_UPDATE (1 << 10) |
396 | #define AFMT_GENERIC0_7 0x7138 |
719 | #define AFMT_GENERIC0_7 0x7138 |
Line 397... | Line 720... | ||
397 | 720 | ||
- | 721 | /* DCE4/5 ELD audio interface */ |
|
- | 722 | #define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x5f78 |
|
- | 723 | #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) |
|
- | 724 | #define SPEAKER_ALLOCATION_MASK (0x7f << 0) |
|
- | 725 | #define SPEAKER_ALLOCATION_SHIFT 0 |
|
- | 726 | #define HDMI_CONNECTION (1 << 16) |
|
- | 727 | #define DP_CONNECTION (1 << 17) |
|
398 | /* DCE4/5 ELD audio interface */ |
728 | |
399 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ |
729 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ |
400 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ |
730 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ |
401 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ |
731 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ |
402 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ |
732 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ |
Line 423... | Line 753... | ||
423 | * bit4 = 96 kHz |
753 | * bit4 = 96 kHz |
424 | * bit5 = 176.4 kHz |
754 | * bit5 = 176.4 kHz |
425 | * bit6 = 192 kHz |
755 | * bit6 = 192 kHz |
426 | */ |
756 | */ |
Line -... | Line 757... | ||
- | 757 | ||
- | 758 | #define AZ_CHANNEL_COUNT_CONTROL 0x5fe4 |
|
- | 759 | # define HBR_CHANNEL_COUNT(x) (((x) & 0x7) << 0) |
|
- | 760 | # define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) << 4) |
|
- | 761 | /* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT |
|
- | 762 | * 0 = use stream header |
|
- | 763 | * 1-7 = channel count - 1 |
|
- | 764 | */ |
|
- | 765 | #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8 |
|
- | 766 | # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) |
|
- | 767 | # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) |
|
- | 768 | /* VIDEO_LIPSYNC, AUDIO_LIPSYNC |
|
- | 769 | * 0 = invalid |
|
- | 770 | * x = legal delay value |
|
- | 771 | * 255 = sync not supported |
|
- | 772 | */ |
|
- | 773 | #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec |
|
- | 774 | # define HBR_CAPABLE (1 << 0) /* enabled by default */ |
|
- | 775 | ||
- | 776 | #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4 |
|
- | 777 | # define DISPLAY0_TYPE(x) (((x) & 0x3) << 0) |
|
- | 778 | # define DISPLAY_TYPE_NONE 0 |
|
- | 779 | # define DISPLAY_TYPE_HDMI 1 |
|
- | 780 | # define DISPLAY_TYPE_DP 2 |
|
- | 781 | # define DISPLAY0_ID(x) (((x) & 0x3f) << 2) |
|
- | 782 | # define DISPLAY1_TYPE(x) (((x) & 0x3) << 8) |
|
- | 783 | # define DISPLAY1_ID(x) (((x) & 0x3f) << 10) |
|
- | 784 | # define DISPLAY2_TYPE(x) (((x) & 0x3) << 16) |
|
- | 785 | # define DISPLAY2_ID(x) (((x) & 0x3f) << 18) |
|
- | 786 | # define DISPLAY3_TYPE(x) (((x) & 0x3) << 24) |
|
- | 787 | # define DISPLAY3_ID(x) (((x) & 0x3f) << 26) |
|
- | 788 | #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8 |
|
- | 789 | # define DISPLAY4_TYPE(x) (((x) & 0x3) << 0) |
|
- | 790 | # define DISPLAY4_ID(x) (((x) & 0x3f) << 2) |
|
- | 791 | # define DISPLAY5_TYPE(x) (((x) & 0x3) << 8) |
|
- | 792 | # define DISPLAY5_ID(x) (((x) & 0x3f) << 10) |
|
- | 793 | #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc |
|
- | 794 | # define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) << 0) |
|
427 | 795 | ||
428 | #define AZ_HOT_PLUG_CONTROL 0x5e78 |
796 | #define AZ_HOT_PLUG_CONTROL 0x5e78 |
429 | # define AZ_FORCE_CODEC_WAKE (1 << 0) |
797 | # define AZ_FORCE_CODEC_WAKE (1 << 0) |
430 | # define PIN0_JACK_DETECTION_ENABLE (1 << 4) |
798 | # define PIN0_JACK_DETECTION_ENABLE (1 << 4) |
431 | # define PIN1_JACK_DETECTION_ENABLE (1 << 5) |
799 | # define PIN1_JACK_DETECTION_ENABLE (1 << 5) |
Line 501... | Line 869... | ||
501 | #define SE_CB_BUSY (1 << 31) |
869 | #define SE_CB_BUSY (1 << 31) |
502 | /* evergreen */ |
870 | /* evergreen */ |
503 | #define CG_THERMAL_CTRL 0x72c |
871 | #define CG_THERMAL_CTRL 0x72c |
504 | #define TOFFSET_MASK 0x00003FE0 |
872 | #define TOFFSET_MASK 0x00003FE0 |
505 | #define TOFFSET_SHIFT 5 |
873 | #define TOFFSET_SHIFT 5 |
- | 874 | #define DIG_THERM_DPM(x) ((x) << 14) |
|
- | 875 | #define DIG_THERM_DPM_MASK 0x003FC000 |
|
- | 876 | #define DIG_THERM_DPM_SHIFT 14 |
|
- | 877 | ||
- | 878 | #define CG_THERMAL_INT 0x734 |
|
- | 879 | #define DIG_THERM_INTH(x) ((x) << 8) |
|
- | 880 | #define DIG_THERM_INTH_MASK 0x0000FF00 |
|
- | 881 | #define DIG_THERM_INTH_SHIFT 8 |
|
- | 882 | #define DIG_THERM_INTL(x) ((x) << 16) |
|
- | 883 | #define DIG_THERM_INTL_MASK 0x00FF0000 |
|
- | 884 | #define DIG_THERM_INTL_SHIFT 16 |
|
- | 885 | #define THERM_INT_MASK_HIGH (1 << 24) |
|
- | 886 | #define THERM_INT_MASK_LOW (1 << 25) |
|
- | 887 | ||
- | 888 | #define TN_CG_THERMAL_INT_CTRL 0x738 |
|
- | 889 | #define TN_DIG_THERM_INTH(x) ((x) << 0) |
|
- | 890 | #define TN_DIG_THERM_INTH_MASK 0x000000FF |
|
- | 891 | #define TN_DIG_THERM_INTH_SHIFT 0 |
|
- | 892 | #define TN_DIG_THERM_INTL(x) ((x) << 8) |
|
- | 893 | #define TN_DIG_THERM_INTL_MASK 0x0000FF00 |
|
- | 894 | #define TN_DIG_THERM_INTL_SHIFT 8 |
|
- | 895 | #define TN_THERM_INT_MASK_HIGH (1 << 24) |
|
- | 896 | #define TN_THERM_INT_MASK_LOW (1 << 25) |
|
- | 897 | ||
506 | #define CG_MULT_THERMAL_STATUS 0x740 |
898 | #define CG_MULT_THERMAL_STATUS 0x740 |
507 | #define ASIC_T(x) ((x) << 16) |
899 | #define ASIC_T(x) ((x) << 16) |
508 | #define ASIC_T_MASK 0x07FF0000 |
900 | #define ASIC_T_MASK 0x07FF0000 |
509 | #define ASIC_T_SHIFT 16 |
901 | #define ASIC_T_SHIFT 16 |
510 | #define CG_TS0_STATUS 0x760 |
902 | #define CG_TS0_STATUS 0x760 |
511 | #define TS0_ADC_DOUT_MASK 0x000003FF |
903 | #define TS0_ADC_DOUT_MASK 0x000003FF |
512 | #define TS0_ADC_DOUT_SHIFT 0 |
904 | #define TS0_ADC_DOUT_SHIFT 0 |
- | 905 | ||
513 | /* APU */ |
906 | /* APU */ |
514 | #define CG_THERMAL_STATUS 0x678 |
907 | #define CG_THERMAL_STATUS 0x678 |
Line 515... | Line 908... | ||
515 | 908 | ||
516 | #define HDP_HOST_PATH_CNTL 0x2C00 |
909 | #define HDP_HOST_PATH_CNTL 0x2C00 |
Line 808... | Line 1201... | ||
808 | # define LATENCY_WATERMARK_MASK(x) ((x) << 16) |
1201 | # define LATENCY_WATERMARK_MASK(x) ((x) << 16) |
809 | #define PIPE0_LATENCY_CONTROL 0x0bf4 |
1202 | #define PIPE0_LATENCY_CONTROL 0x0bf4 |
810 | # define LATENCY_LOW_WATERMARK(x) ((x) << 0) |
1203 | # define LATENCY_LOW_WATERMARK(x) ((x) << 0) |
811 | # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) |
1204 | # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) |
Line -... | Line 1205... | ||
- | 1205 | ||
- | 1206 | #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 |
|
- | 1207 | # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) |
|
- | 1208 | # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) |
|
812 | 1209 | ||
813 | #define IH_RB_CNTL 0x3e00 |
1210 | #define IH_RB_CNTL 0x3e00 |
814 | # define IH_RB_ENABLE (1 << 0) |
1211 | # define IH_RB_ENABLE (1 << 0) |
815 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ |
1212 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ |
816 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) |
1213 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) |
Line 956... | Line 1353... | ||
956 | #define DC_HPD6_CONTROL 0x6060 |
1353 | #define DC_HPD6_CONTROL 0x6060 |
957 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) |
1354 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) |
958 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
1355 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
959 | # define DC_HPDx_EN (1 << 28) |
1356 | # define DC_HPDx_EN (1 << 28) |
Line -... | Line 1357... | ||
- | 1357 | ||
- | 1358 | /* DCE4/5/6 FMT blocks */ |
|
- | 1359 | #define FMT_DYNAMIC_EXP_CNTL 0x6fb4 |
|
- | 1360 | # define FMT_DYNAMIC_EXP_EN (1 << 0) |
|
- | 1361 | # define FMT_DYNAMIC_EXP_MODE (1 << 4) |
|
- | 1362 | /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ |
|
- | 1363 | #define FMT_CONTROL 0x6fb8 |
|
- | 1364 | # define FMT_PIXEL_ENCODING (1 << 16) |
|
- | 1365 | /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ |
|
- | 1366 | #define FMT_BIT_DEPTH_CONTROL 0x6fc8 |
|
- | 1367 | # define FMT_TRUNCATE_EN (1 << 0) |
|
- | 1368 | # define FMT_TRUNCATE_DEPTH (1 << 4) |
|
- | 1369 | # define FMT_SPATIAL_DITHER_EN (1 << 8) |
|
- | 1370 | # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) |
|
- | 1371 | # define FMT_SPATIAL_DITHER_DEPTH (1 << 12) |
|
- | 1372 | # define FMT_FRAME_RANDOM_ENABLE (1 << 13) |
|
- | 1373 | # define FMT_RGB_RANDOM_ENABLE (1 << 14) |
|
- | 1374 | # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) |
|
- | 1375 | # define FMT_TEMPORAL_DITHER_EN (1 << 16) |
|
- | 1376 | # define FMT_TEMPORAL_DITHER_DEPTH (1 << 20) |
|
- | 1377 | # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) |
|
- | 1378 | # define FMT_TEMPORAL_LEVEL (1 << 24) |
|
- | 1379 | # define FMT_TEMPORAL_DITHER_RESET (1 << 25) |
|
- | 1380 | # define FMT_25FRC_SEL(x) ((x) << 26) |
|
- | 1381 | # define FMT_50FRC_SEL(x) ((x) << 28) |
|
- | 1382 | # define FMT_75FRC_SEL(x) ((x) << 30) |
|
- | 1383 | #define FMT_CLAMP_CONTROL 0x6fe4 |
|
- | 1384 | # define FMT_CLAMP_DATA_EN (1 << 0) |
|
- | 1385 | # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) |
|
- | 1386 | # define FMT_CLAMP_6BPC 0 |
|
- | 1387 | # define FMT_CLAMP_8BPC 1 |
|
- | 1388 | # define FMT_CLAMP_10BPC 2 |
|
960 | 1389 | ||
961 | /* ASYNC DMA */ |
1390 | /* ASYNC DMA */ |
962 | #define DMA_RB_RPTR 0xd008 |
1391 | #define DMA_RB_RPTR 0xd008 |
Line 963... | Line 1392... | ||
963 | #define DMA_RB_WPTR 0xd00c |
1392 | #define DMA_RB_WPTR 0xd00c |
Line 990... | Line 1419... | ||
990 | #define DMA_PACKET_TRAP 0x7 |
1419 | #define DMA_PACKET_TRAP 0x7 |
991 | #define DMA_PACKET_SRBM_WRITE 0x9 |
1420 | #define DMA_PACKET_SRBM_WRITE 0x9 |
992 | #define DMA_PACKET_CONSTANT_FILL 0xd |
1421 | #define DMA_PACKET_CONSTANT_FILL 0xd |
993 | #define DMA_PACKET_NOP 0xf |
1422 | #define DMA_PACKET_NOP 0xf |
Line -... | Line 1423... | ||
- | 1423 | ||
- | 1424 | /* PIF PHY0 indirect regs */ |
|
- | 1425 | #define PB0_PIF_CNTL 0x10 |
|
- | 1426 | # define LS2_EXIT_TIME(x) ((x) << 17) |
|
- | 1427 | # define LS2_EXIT_TIME_MASK (0x7 << 17) |
|
- | 1428 | # define LS2_EXIT_TIME_SHIFT 17 |
|
- | 1429 | #define PB0_PIF_PAIRING 0x11 |
|
- | 1430 | # define MULTI_PIF (1 << 25) |
|
- | 1431 | #define PB0_PIF_PWRDOWN_0 0x12 |
|
- | 1432 | # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) |
|
- | 1433 | # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) |
|
- | 1434 | # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 |
|
- | 1435 | # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) |
|
- | 1436 | # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) |
|
- | 1437 | # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 |
|
- | 1438 | # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) |
|
- | 1439 | # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) |
|
- | 1440 | # define PLL_RAMP_UP_TIME_0_SHIFT 24 |
|
- | 1441 | #define PB0_PIF_PWRDOWN_1 0x13 |
|
- | 1442 | # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) |
|
- | 1443 | # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) |
|
- | 1444 | # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 |
|
- | 1445 | # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) |
|
- | 1446 | # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) |
|
- | 1447 | # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 |
|
- | 1448 | # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) |
|
- | 1449 | # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) |
|
- | 1450 | # define PLL_RAMP_UP_TIME_1_SHIFT 24 |
|
- | 1451 | /* PIF PHY1 indirect regs */ |
|
- | 1452 | #define PB1_PIF_CNTL 0x10 |
|
- | 1453 | #define PB1_PIF_PAIRING 0x11 |
|
- | 1454 | #define PB1_PIF_PWRDOWN_0 0x12 |
|
994 | 1455 | #define PB1_PIF_PWRDOWN_1 0x13 |
|
- | 1456 | /* PCIE PORT indirect regs */ |
|
- | 1457 | #define PCIE_LC_CNTL 0xa0 |
|
- | 1458 | # define LC_L0S_INACTIVITY(x) ((x) << 8) |
|
- | 1459 | # define LC_L0S_INACTIVITY_MASK (0xf << 8) |
|
- | 1460 | # define LC_L0S_INACTIVITY_SHIFT 8 |
|
- | 1461 | # define LC_L1_INACTIVITY(x) ((x) << 12) |
|
- | 1462 | # define LC_L1_INACTIVITY_MASK (0xf << 12) |
|
- | 1463 | # define LC_L1_INACTIVITY_SHIFT 12 |
|
- | 1464 | # define LC_PMI_TO_L1_DIS (1 << 16) |
|
995 | /* PCIE link stuff */ |
1465 | # define LC_ASPM_TO_L1_DIS (1 << 24) |
996 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
1466 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
997 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
1467 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
998 | # define LC_LINK_WIDTH_SHIFT 0 |
1468 | # define LC_LINK_WIDTH_SHIFT 0 |
999 | # define LC_LINK_WIDTH_MASK 0x7 |
1469 | # define LC_LINK_WIDTH_MASK 0x7 |
Line 1010... | Line 1480... | ||
1010 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) |
1480 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) |
1011 | # define LC_RENEGOTIATE_EN (1 << 10) |
1481 | # define LC_RENEGOTIATE_EN (1 << 10) |
1012 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
1482 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
1013 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
1483 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
1014 | # define LC_UPCONFIGURE_DIS (1 << 13) |
1484 | # define LC_UPCONFIGURE_DIS (1 << 13) |
- | 1485 | # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) |
|
- | 1486 | # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) |
|
- | 1487 | # define LC_DYN_LANES_PWR_STATE_SHIFT 21 |
|
1015 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
1488 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
1016 | # define LC_GEN2_EN_STRAP (1 << 0) |
1489 | # define LC_GEN2_EN_STRAP (1 << 0) |
1017 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
1490 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
1018 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
1491 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
1019 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
1492 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
1020 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
1493 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
1021 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
1494 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
1022 | # define LC_CURRENT_DATA_RATE (1 << 11) |
1495 | # define LC_CURRENT_DATA_RATE (1 << 11) |
- | 1496 | # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) |
|
- | 1497 | # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) |
|
- | 1498 | # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 |
|
1023 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
1499 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
1024 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
1500 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
1025 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
1501 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
1026 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
1502 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
1027 | #define MM_CFGREGS_CNTL 0x544c |
1503 | #define MM_CFGREGS_CNTL 0x544c |
Line 1098... | Line 1574... | ||
1098 | * 4. DST_ADDR_LO [31:0] |
1574 | * 4. DST_ADDR_LO [31:0] |
1099 | * 5. DST_ADDR_HI [7:0] |
1575 | * 5. DST_ADDR_HI [7:0] |
1100 | * 6. COMMAND [29:22] | BYTE_COUNT [20:0] |
1576 | * 6. COMMAND [29:22] | BYTE_COUNT [20:0] |
1101 | */ |
1577 | */ |
1102 | # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) |
1578 | # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) |
1103 | /* 0 - SRC_ADDR |
1579 | /* 0 - DST_ADDR |
1104 | * 1 - GDS |
1580 | * 1 - GDS |
1105 | */ |
1581 | */ |
1106 | # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) |
1582 | # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) |
1107 | /* 0 - ME |
1583 | /* 0 - ME |
1108 | * 1 - PFP |
1584 | * 1 - PFP |
Line 1113... | Line 1589... | ||
1113 | * 2 - DATA |
1589 | * 2 - DATA |
1114 | */ |
1590 | */ |
1115 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) |
1591 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) |
1116 | /* COMMAND */ |
1592 | /* COMMAND */ |
1117 | # define PACKET3_CP_DMA_DIS_WC (1 << 21) |
1593 | # define PACKET3_CP_DMA_DIS_WC (1 << 21) |
1118 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) |
1594 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) |
1119 | /* 0 - none |
1595 | /* 0 - none |
1120 | * 1 - 8 in 16 |
1596 | * 1 - 8 in 16 |
1121 | * 2 - 8 in 32 |
1597 | * 2 - 8 in 32 |
1122 | * 3 - 8 in 64 |
1598 | * 3 - 8 in 64 |
1123 | */ |
1599 | */ |