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Line 248... | Line 248... | ||
248 | #define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 |
248 | #define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 |
249 | #define EVERGREEN_DC_GPIO_HPD_Y 0x64bc |
249 | #define EVERGREEN_DC_GPIO_HPD_Y 0x64bc |
Line 250... | Line 250... | ||
250 | 250 | ||
251 | /* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */ |
251 | /* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */ |
- | 252 | #define EVERGREEN_HDMI_BASE 0x7030 |
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- | 253 | /*DIG block*/ |
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- | 254 | #define NI_DIG0_REGISTER_OFFSET (0x7000 - 0x7000) |
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- | 255 | #define NI_DIG1_REGISTER_OFFSET (0x7C00 - 0x7000) |
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- | 256 | #define NI_DIG2_REGISTER_OFFSET (0x10800 - 0x7000) |
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- | 257 | #define NI_DIG3_REGISTER_OFFSET (0x11400 - 0x7000) |
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- | 258 | #define NI_DIG4_REGISTER_OFFSET (0x12000 - 0x7000) |
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- | 259 | #define NI_DIG5_REGISTER_OFFSET (0x12C00 - 0x7000) |
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- | 260 | ||
- | 261 | ||
- | 262 | #define NI_DIG_FE_CNTL 0x7000 |
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- | 263 | # define NI_DIG_FE_CNTL_SOURCE_SELECT(x) ((x) & 0x3) |
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- | 264 | # define NI_DIG_FE_CNTL_SYMCLK_FE_ON (1<<24) |
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- | 265 | ||
- | 266 | ||
- | 267 | #define NI_DIG_BE_CNTL 0x7140 |
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- | 268 | # define NI_DIG_BE_CNTL_FE_SOURCE_SELECT(x) (((x) >> 8 ) & 0x3F) |
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- | 269 | # define NI_DIG_FE_CNTL_MODE(x) (((x) >> 16) & 0x7 ) |
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- | 270 | ||
- | 271 | #define NI_DIG_BE_EN_CNTL 0x7144 |
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- | 272 | # define NI_DIG_BE_EN_CNTL_ENABLE (1 << 0) |
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- | 273 | # define NI_DIG_BE_EN_CNTL_SYMBCLK_ON (1 << 8) |
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Line 252... | Line 274... | ||
252 | #define EVERGREEN_HDMI_BASE 0x7030 |
274 | # define NI_DIG_BE_DPSST 0 |
- | 275 | ||
- | 276 | /* Display Port block */ |
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- | 277 | #define EVERGREEN_DP0_REGISTER_OFFSET (0x730C - 0x730C) |
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- | 278 | #define EVERGREEN_DP1_REGISTER_OFFSET (0x7F0C - 0x730C) |
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- | 279 | #define EVERGREEN_DP2_REGISTER_OFFSET (0x10B0C - 0x730C) |
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- | 280 | #define EVERGREEN_DP3_REGISTER_OFFSET (0x1170C - 0x730C) |
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- | 281 | #define EVERGREEN_DP4_REGISTER_OFFSET (0x1230C - 0x730C) |
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- | 282 | #define EVERGREEN_DP5_REGISTER_OFFSET (0x12F0C - 0x730C) |
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- | 283 | ||
- | 284 | ||
- | 285 | #define EVERGREEN_DP_VID_STREAM_CNTL 0x730C |
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- | 286 | # define EVERGREEN_DP_VID_STREAM_CNTL_ENABLE (1 << 0) |
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- | 287 | # define EVERGREEN_DP_VID_STREAM_STATUS (1 <<16) |
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253 | 288 | #define EVERGREEN_DP_STEER_FIFO 0x7310 |
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254 | /* Display Port block */ |
289 | # define EVERGREEN_DP_STEER_FIFO_RESET (1 << 0) |
255 | #define EVERGREEN_DP_SEC_CNTL 0x7280 |
290 | #define EVERGREEN_DP_SEC_CNTL 0x7280 |
256 | # define EVERGREEN_DP_SEC_STREAM_ENABLE (1 << 0) |
291 | # define EVERGREEN_DP_SEC_STREAM_ENABLE (1 << 0) |
257 | # define EVERGREEN_DP_SEC_ASP_ENABLE (1 << 4) |
292 | # define EVERGREEN_DP_SEC_ASP_ENABLE (1 << 4) |
Line 264... | Line 299... | ||
264 | # define EVERGREEN_DP_SEC_TIMESTAMP_MODE(x) (((x) & 0x3) << 0) |
299 | # define EVERGREEN_DP_SEC_TIMESTAMP_MODE(x) (((x) & 0x3) << 0) |
265 | #define EVERGREEN_DP_SEC_AUD_N 0x7294 |
300 | #define EVERGREEN_DP_SEC_AUD_N 0x7294 |
266 | # define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x) (((x) & 0xf) << 24) |
301 | # define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x) (((x) & 0xf) << 24) |
267 | # define EVERGREEN_DP_SEC_SS_EN (1 << 28) |
302 | # define EVERGREEN_DP_SEC_SS_EN (1 << 28) |
Line -... | Line 303... | ||
- | 303 | ||
- | 304 | /*DCIO_UNIPHY block*/ |
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- | 305 | #define NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1 (0x6600 -0x6600) |
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- | 306 | #define NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1 (0x6640 -0x6600) |
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- | 307 | #define NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1 (0x6680 - 0x6600) |
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- | 308 | #define NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1 (0x66C0 - 0x6600) |
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- | 309 | #define NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1 (0x6700 - 0x6600) |
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- | 310 | #define NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1 (0x6740 - 0x6600) |
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- | 311 | ||
- | 312 | #define NI_DCIO_UNIPHY0_PLL_CONTROL1 0x6618 |
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- | 313 | # define NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE (1 << 0) |
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268 | 314 |