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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Christian König. |
4 | * Copyright 2009 Christian König. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Christian König |
24 | * Authors: Christian König |
25 | * Rafał Miłecki |
25 | * Rafał Miłecki |
26 | */ |
26 | */ |
27 | #include |
27 | #include |
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include "radeon.h" |
30 | #include "radeon.h" |
31 | #include "radeon_asic.h" |
31 | #include "radeon_asic.h" |
32 | #include "radeon_audio.h" |
32 | #include "radeon_audio.h" |
33 | #include "evergreend.h" |
33 | #include "evergreend.h" |
34 | #include "atom.h" |
34 | #include "atom.h" |
35 | 35 | ||
36 | /* enable the audio stream */ |
36 | /* enable the audio stream */ |
37 | void dce4_audio_enable(struct radeon_device *rdev, |
37 | void dce4_audio_enable(struct radeon_device *rdev, |
38 | struct r600_audio_pin *pin, |
38 | struct r600_audio_pin *pin, |
39 | u8 enable_mask) |
39 | u8 enable_mask) |
40 | { |
40 | { |
41 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); |
41 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); |
42 | 42 | ||
43 | if (!pin) |
43 | if (!pin) |
44 | return; |
44 | return; |
45 | 45 | ||
46 | if (enable_mask) { |
46 | if (enable_mask) { |
47 | tmp |= AUDIO_ENABLED; |
47 | tmp |= AUDIO_ENABLED; |
48 | if (enable_mask & 1) |
48 | if (enable_mask & 1) |
49 | tmp |= PIN0_AUDIO_ENABLED; |
49 | tmp |= PIN0_AUDIO_ENABLED; |
50 | if (enable_mask & 2) |
50 | if (enable_mask & 2) |
51 | tmp |= PIN1_AUDIO_ENABLED; |
51 | tmp |= PIN1_AUDIO_ENABLED; |
52 | if (enable_mask & 4) |
52 | if (enable_mask & 4) |
53 | tmp |= PIN2_AUDIO_ENABLED; |
53 | tmp |= PIN2_AUDIO_ENABLED; |
54 | if (enable_mask & 8) |
54 | if (enable_mask & 8) |
55 | tmp |= PIN3_AUDIO_ENABLED; |
55 | tmp |= PIN3_AUDIO_ENABLED; |
56 | } else { |
56 | } else { |
57 | tmp &= ~(AUDIO_ENABLED | |
57 | tmp &= ~(AUDIO_ENABLED | |
58 | PIN0_AUDIO_ENABLED | |
58 | PIN0_AUDIO_ENABLED | |
59 | PIN1_AUDIO_ENABLED | |
59 | PIN1_AUDIO_ENABLED | |
60 | PIN2_AUDIO_ENABLED | |
60 | PIN2_AUDIO_ENABLED | |
61 | PIN3_AUDIO_ENABLED); |
61 | PIN3_AUDIO_ENABLED); |
62 | } |
62 | } |
63 | 63 | ||
64 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
64 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
65 | } |
65 | } |
66 | 66 | ||
67 | void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
67 | void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
68 | const struct radeon_hdmi_acr *acr) |
68 | const struct radeon_hdmi_acr *acr) |
69 | { |
69 | { |
70 | struct drm_device *dev = encoder->dev; |
70 | struct drm_device *dev = encoder->dev; |
71 | struct radeon_device *rdev = dev->dev_private; |
71 | struct radeon_device *rdev = dev->dev_private; |
72 | int bpc = 8; |
72 | int bpc = 8; |
73 | 73 | ||
74 | if (encoder->crtc) { |
74 | if (encoder->crtc) { |
75 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
75 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
76 | bpc = radeon_crtc->bpc; |
76 | bpc = radeon_crtc->bpc; |
77 | } |
77 | } |
78 | 78 | ||
79 | if (bpc > 8) |
79 | if (bpc > 8) |
80 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
80 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
81 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
81 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
82 | else |
82 | else |
83 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
83 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
84 | HDMI_ACR_SOURCE | /* select SW CTS value */ |
84 | HDMI_ACR_SOURCE | /* select SW CTS value */ |
85 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
85 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
86 | 86 | ||
87 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); |
87 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); |
88 | WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); |
88 | WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); |
89 | 89 | ||
90 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); |
90 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); |
91 | WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); |
91 | WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); |
92 | 92 | ||
93 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); |
93 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); |
94 | WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); |
94 | WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); |
95 | } |
95 | } |
96 | 96 | ||
97 | void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
97 | void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
98 | struct drm_connector *connector, struct drm_display_mode *mode) |
98 | struct drm_connector *connector, struct drm_display_mode *mode) |
99 | { |
99 | { |
100 | struct radeon_device *rdev = encoder->dev->dev_private; |
100 | struct radeon_device *rdev = encoder->dev->dev_private; |
101 | u32 tmp = 0; |
101 | u32 tmp = 0; |
102 | 102 | ||
103 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
103 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
104 | if (connector->latency_present[1]) |
104 | if (connector->latency_present[1]) |
105 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
105 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
106 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
106 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
107 | else |
107 | else |
108 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
108 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
109 | } else { |
109 | } else { |
110 | if (connector->latency_present[0]) |
110 | if (connector->latency_present[0]) |
111 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
111 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
112 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
112 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
113 | else |
113 | else |
114 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
114 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
115 | } |
115 | } |
116 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
116 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
117 | } |
117 | } |
118 | 118 | ||
119 | void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
119 | void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
120 | u8 *sadb, int sad_count) |
120 | u8 *sadb, int sad_count) |
121 | { |
121 | { |
122 | struct radeon_device *rdev = encoder->dev->dev_private; |
122 | struct radeon_device *rdev = encoder->dev->dev_private; |
123 | u32 tmp; |
123 | u32 tmp; |
124 | 124 | ||
125 | /* program the speaker allocation */ |
125 | /* program the speaker allocation */ |
126 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
126 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
127 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
127 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
128 | /* set HDMI mode */ |
128 | /* set HDMI mode */ |
129 | tmp |= HDMI_CONNECTION; |
129 | tmp |= HDMI_CONNECTION; |
130 | if (sad_count) |
130 | if (sad_count) |
131 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
131 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
132 | else |
132 | else |
133 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
133 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
134 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
134 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
135 | } |
135 | } |
136 | 136 | ||
137 | void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
137 | void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
138 | u8 *sadb, int sad_count) |
138 | u8 *sadb, int sad_count) |
139 | { |
139 | { |
140 | struct radeon_device *rdev = encoder->dev->dev_private; |
140 | struct radeon_device *rdev = encoder->dev->dev_private; |
141 | u32 tmp; |
141 | u32 tmp; |
142 | 142 | ||
143 | /* program the speaker allocation */ |
143 | /* program the speaker allocation */ |
144 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
144 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
145 | tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); |
145 | tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); |
146 | /* set DP mode */ |
146 | /* set DP mode */ |
147 | tmp |= DP_CONNECTION; |
147 | tmp |= DP_CONNECTION; |
148 | if (sad_count) |
148 | if (sad_count) |
149 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
149 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
150 | else |
150 | else |
151 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
151 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
152 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
152 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
153 | } |
153 | } |
154 | 154 | ||
155 | void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, |
155 | void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, |
156 | struct cea_sad *sads, int sad_count) |
156 | struct cea_sad *sads, int sad_count) |
157 | { |
157 | { |
158 | int i; |
158 | int i; |
159 | struct radeon_device *rdev = encoder->dev->dev_private; |
159 | struct radeon_device *rdev = encoder->dev->dev_private; |
160 | static const u16 eld_reg_to_type[][2] = { |
160 | static const u16 eld_reg_to_type[][2] = { |
161 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
161 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
162 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
162 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
163 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
163 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
164 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
164 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
165 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
165 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
166 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
166 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
167 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
167 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
168 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
168 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
169 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
169 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
170 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
170 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
171 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
171 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
172 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
172 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
173 | }; |
173 | }; |
174 | 174 | ||
175 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
175 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
176 | u32 value = 0; |
176 | u32 value = 0; |
177 | u8 stereo_freqs = 0; |
177 | u8 stereo_freqs = 0; |
178 | int max_channels = -1; |
178 | int max_channels = -1; |
179 | int j; |
179 | int j; |
180 | 180 | ||
181 | for (j = 0; j < sad_count; j++) { |
181 | for (j = 0; j < sad_count; j++) { |
182 | struct cea_sad *sad = &sads[j]; |
182 | struct cea_sad *sad = &sads[j]; |
183 | 183 | ||
184 | if (sad->format == eld_reg_to_type[i][1]) { |
184 | if (sad->format == eld_reg_to_type[i][1]) { |
185 | if (sad->channels > max_channels) { |
185 | if (sad->channels > max_channels) { |
186 | value = MAX_CHANNELS(sad->channels) | |
186 | value = MAX_CHANNELS(sad->channels) | |
187 | DESCRIPTOR_BYTE_2(sad->byte2) | |
187 | DESCRIPTOR_BYTE_2(sad->byte2) | |
188 | SUPPORTED_FREQUENCIES(sad->freq); |
188 | SUPPORTED_FREQUENCIES(sad->freq); |
189 | max_channels = sad->channels; |
189 | max_channels = sad->channels; |
190 | } |
190 | } |
191 | 191 | ||
192 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
192 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
193 | stereo_freqs |= sad->freq; |
193 | stereo_freqs |= sad->freq; |
194 | else |
194 | else |
195 | break; |
195 | break; |
196 | } |
196 | } |
197 | } |
197 | } |
198 | 198 | ||
199 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
199 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
200 | 200 | ||
201 | WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); |
201 | WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); |
202 | } |
202 | } |
203 | } |
203 | } |
204 | 204 | ||
205 | /* |
205 | /* |
206 | * build a AVI Info Frame |
206 | * build a AVI Info Frame |
207 | */ |
207 | */ |
208 | void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, |
208 | void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, |
209 | unsigned char *buffer, size_t size) |
209 | unsigned char *buffer, size_t size) |
210 | { |
210 | { |
211 | uint8_t *frame = buffer + 3; |
211 | uint8_t *frame = buffer + 3; |
212 | 212 | ||
213 | WREG32(AFMT_AVI_INFO0 + offset, |
213 | WREG32(AFMT_AVI_INFO0 + offset, |
214 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
214 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
215 | WREG32(AFMT_AVI_INFO1 + offset, |
215 | WREG32(AFMT_AVI_INFO1 + offset, |
216 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
216 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
217 | WREG32(AFMT_AVI_INFO2 + offset, |
217 | WREG32(AFMT_AVI_INFO2 + offset, |
218 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
218 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
219 | WREG32(AFMT_AVI_INFO3 + offset, |
219 | WREG32(AFMT_AVI_INFO3 + offset, |
220 | frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); |
220 | frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); |
221 | 221 | ||
222 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
222 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
223 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
223 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
224 | ~HDMI_AVI_INFO_LINE_MASK); |
224 | ~HDMI_AVI_INFO_LINE_MASK); |
225 | } |
225 | } |
226 | 226 | ||
227 | void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, |
227 | void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, |
228 | struct radeon_crtc *crtc, unsigned int clock) |
228 | struct radeon_crtc *crtc, unsigned int clock) |
229 | { |
229 | { |
230 | unsigned int max_ratio = clock / 24000; |
230 | unsigned int max_ratio = clock / 24000; |
231 | u32 dto_phase; |
231 | u32 dto_phase; |
232 | u32 wallclock_ratio; |
232 | u32 wallclock_ratio; |
233 | u32 value; |
233 | u32 value; |
234 | 234 | ||
235 | if (max_ratio >= 8) { |
235 | if (max_ratio >= 8) { |
236 | dto_phase = 192 * 1000; |
236 | dto_phase = 192 * 1000; |
237 | wallclock_ratio = 3; |
237 | wallclock_ratio = 3; |
238 | } else if (max_ratio >= 4) { |
238 | } else if (max_ratio >= 4) { |
239 | dto_phase = 96 * 1000; |
239 | dto_phase = 96 * 1000; |
240 | wallclock_ratio = 2; |
240 | wallclock_ratio = 2; |
241 | } else if (max_ratio >= 2) { |
241 | } else if (max_ratio >= 2) { |
242 | dto_phase = 48 * 1000; |
242 | dto_phase = 48 * 1000; |
243 | wallclock_ratio = 1; |
243 | wallclock_ratio = 1; |
244 | } else { |
244 | } else { |
245 | dto_phase = 24 * 1000; |
245 | dto_phase = 24 * 1000; |
246 | wallclock_ratio = 0; |
246 | wallclock_ratio = 0; |
247 | } |
247 | } |
248 | 248 | ||
249 | value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
249 | value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
250 | value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
250 | value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
251 | value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO; |
251 | value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO; |
252 | WREG32(DCCG_AUDIO_DTO0_CNTL, value); |
252 | WREG32(DCCG_AUDIO_DTO0_CNTL, value); |
253 | 253 | ||
254 | /* Two dtos; generally use dto0 for HDMI */ |
254 | /* Two dtos; generally use dto0 for HDMI */ |
255 | value = 0; |
255 | value = 0; |
256 | 256 | ||
257 | if (crtc) |
257 | if (crtc) |
258 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
258 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
259 | 259 | ||
260 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
260 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
261 | 261 | ||
262 | /* Express [24MHz / target pixel clock] as an exact rational |
262 | /* Express [24MHz / target pixel clock] as an exact rational |
263 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
263 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
264 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
264 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
265 | */ |
265 | */ |
266 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
266 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
267 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); |
267 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); |
268 | } |
268 | } |
269 | 269 | ||
270 | void dce4_dp_audio_set_dto(struct radeon_device *rdev, |
270 | void dce4_dp_audio_set_dto(struct radeon_device *rdev, |
271 | struct radeon_crtc *crtc, unsigned int clock) |
271 | struct radeon_crtc *crtc, unsigned int clock) |
272 | { |
272 | { |
273 | u32 value; |
273 | u32 value; |
274 | 274 | ||
275 | value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
275 | value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
276 | value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO; |
276 | value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO; |
277 | WREG32(DCCG_AUDIO_DTO1_CNTL, value); |
277 | WREG32(DCCG_AUDIO_DTO1_CNTL, value); |
278 | 278 | ||
279 | /* Two dtos; generally use dto1 for DP */ |
279 | /* Two dtos; generally use dto1 for DP */ |
280 | value = 0; |
280 | value = 0; |
281 | value |= DCCG_AUDIO_DTO_SEL; |
281 | value |= DCCG_AUDIO_DTO_SEL; |
282 | 282 | ||
283 | if (crtc) |
283 | if (crtc) |
284 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
284 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
285 | 285 | ||
286 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
286 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
287 | 287 | ||
288 | /* Express [24MHz / target pixel clock] as an exact rational |
288 | /* Express [24MHz / target pixel clock] as an exact rational |
289 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
289 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
290 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
290 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
291 | */ |
291 | */ |
- | 292 | if (ASIC_IS_DCE41(rdev)) { |
|
- | 293 | unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) & |
|
- | 294 | DENTIST_DPREFCLK_WDIVIDER_MASK) >> |
|
- | 295 | DENTIST_DPREFCLK_WDIVIDER_SHIFT; |
|
- | 296 | div = radeon_audio_decode_dfs_div(div); |
|
- | 297 | ||
- | 298 | if (div) |
|
- | 299 | clock = 100 * clock / div; |
|
- | 300 | } |
|
- | 301 | ||
292 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
302 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
293 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
303 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
294 | } |
304 | } |
295 | 305 | ||
296 | void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset) |
306 | void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset) |
297 | { |
307 | { |
298 | struct drm_device *dev = encoder->dev; |
308 | struct drm_device *dev = encoder->dev; |
299 | struct radeon_device *rdev = dev->dev_private; |
309 | struct radeon_device *rdev = dev->dev_private; |
300 | 310 | ||
301 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
311 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
302 | HDMI_NULL_SEND | /* send null packets when required */ |
312 | HDMI_NULL_SEND | /* send null packets when required */ |
303 | HDMI_GC_SEND | /* send general control packets */ |
313 | HDMI_GC_SEND | /* send general control packets */ |
304 | HDMI_GC_CONT); /* send general control packets every frame */ |
314 | HDMI_GC_CONT); /* send general control packets every frame */ |
305 | } |
315 | } |
306 | 316 | ||
307 | void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc) |
317 | void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc) |
308 | { |
318 | { |
309 | struct drm_device *dev = encoder->dev; |
319 | struct drm_device *dev = encoder->dev; |
310 | struct radeon_device *rdev = dev->dev_private; |
320 | struct radeon_device *rdev = dev->dev_private; |
311 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
321 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
312 | uint32_t val; |
322 | uint32_t val; |
313 | 323 | ||
314 | val = RREG32(HDMI_CONTROL + offset); |
324 | val = RREG32(HDMI_CONTROL + offset); |
315 | val &= ~HDMI_DEEP_COLOR_ENABLE; |
325 | val &= ~HDMI_DEEP_COLOR_ENABLE; |
316 | val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; |
326 | val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; |
317 | 327 | ||
318 | switch (bpc) { |
328 | switch (bpc) { |
319 | case 0: |
329 | case 0: |
320 | case 6: |
330 | case 6: |
321 | case 8: |
331 | case 8: |
322 | case 16: |
332 | case 16: |
323 | default: |
333 | default: |
324 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", |
334 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", |
325 | connector->name, bpc); |
335 | connector->name, bpc); |
326 | break; |
336 | break; |
327 | case 10: |
337 | case 10: |
328 | val |= HDMI_DEEP_COLOR_ENABLE; |
338 | val |= HDMI_DEEP_COLOR_ENABLE; |
329 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); |
339 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); |
330 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", |
340 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", |
331 | connector->name); |
341 | connector->name); |
332 | break; |
342 | break; |
333 | case 12: |
343 | case 12: |
334 | val |= HDMI_DEEP_COLOR_ENABLE; |
344 | val |= HDMI_DEEP_COLOR_ENABLE; |
335 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); |
345 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); |
336 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", |
346 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", |
337 | connector->name); |
347 | connector->name); |
338 | break; |
348 | break; |
339 | } |
349 | } |
340 | 350 | ||
341 | WREG32(HDMI_CONTROL + offset, val); |
351 | WREG32(HDMI_CONTROL + offset, val); |
342 | } |
352 | } |
343 | 353 | ||
344 | void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset) |
354 | void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset) |
345 | { |
355 | { |
346 | struct drm_device *dev = encoder->dev; |
356 | struct drm_device *dev = encoder->dev; |
347 | struct radeon_device *rdev = dev->dev_private; |
357 | struct radeon_device *rdev = dev->dev_private; |
348 | 358 | ||
349 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
359 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
350 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
360 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
351 | 361 | ||
352 | WREG32(AFMT_60958_0 + offset, |
362 | WREG32(AFMT_60958_0 + offset, |
353 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); |
363 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); |
354 | 364 | ||
355 | WREG32(AFMT_60958_1 + offset, |
365 | WREG32(AFMT_60958_1 + offset, |
356 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); |
366 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); |
357 | 367 | ||
358 | WREG32(AFMT_60958_2 + offset, |
368 | WREG32(AFMT_60958_2 + offset, |
359 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | |
369 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | |
360 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | |
370 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | |
361 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | |
371 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | |
362 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | |
372 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | |
363 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | |
373 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | |
364 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); |
374 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); |
365 | 375 | ||
366 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
376 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
367 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
377 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
368 | 378 | ||
369 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
379 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
370 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
380 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
371 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
381 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
372 | 382 | ||
373 | /* allow 60958 channel status and send audio packets fields to be updated */ |
383 | /* allow 60958 channel status and send audio packets fields to be updated */ |
374 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
384 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
375 | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE); |
385 | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE); |
376 | } |
386 | } |
377 | 387 | ||
378 | 388 | ||
379 | void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) |
389 | void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) |
380 | { |
390 | { |
381 | struct drm_device *dev = encoder->dev; |
391 | struct drm_device *dev = encoder->dev; |
382 | struct radeon_device *rdev = dev->dev_private; |
392 | struct radeon_device *rdev = dev->dev_private; |
383 | 393 | ||
384 | if (mute) |
394 | if (mute) |
385 | WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE); |
395 | WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE); |
386 | else |
396 | else |
387 | WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE); |
397 | WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE); |
388 | } |
398 | } |
389 | 399 | ||
390 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
400 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
391 | { |
401 | { |
392 | struct drm_device *dev = encoder->dev; |
402 | struct drm_device *dev = encoder->dev; |
393 | struct radeon_device *rdev = dev->dev_private; |
403 | struct radeon_device *rdev = dev->dev_private; |
394 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
404 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
395 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
405 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
396 | 406 | ||
397 | if (!dig || !dig->afmt) |
407 | if (!dig || !dig->afmt) |
398 | return; |
408 | return; |
399 | 409 | ||
400 | if (enable) { |
410 | if (enable) { |
401 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
411 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
402 | 412 | ||
403 | if (connector && drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
413 | if (connector && drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
404 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
414 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
405 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
415 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
406 | HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */ |
416 | HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */ |
407 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
417 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
408 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
418 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
409 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
419 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
410 | AFMT_AUDIO_SAMPLE_SEND); |
420 | AFMT_AUDIO_SAMPLE_SEND); |
411 | } else { |
421 | } else { |
412 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
422 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
413 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
423 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
414 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ |
424 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ |
415 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
425 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
416 | ~AFMT_AUDIO_SAMPLE_SEND); |
426 | ~AFMT_AUDIO_SAMPLE_SEND); |
417 | } |
427 | } |
418 | } else { |
428 | } else { |
419 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
429 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
420 | ~AFMT_AUDIO_SAMPLE_SEND); |
430 | ~AFMT_AUDIO_SAMPLE_SEND); |
421 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); |
431 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); |
422 | } |
432 | } |
423 | 433 | ||
424 | dig->afmt->enabled = enable; |
434 | dig->afmt->enabled = enable; |
425 | 435 | ||
426 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
436 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
427 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
437 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
428 | } |
438 | } |
429 | 439 | ||
430 | void evergreen_dp_enable(struct drm_encoder *encoder, bool enable) |
440 | void evergreen_dp_enable(struct drm_encoder *encoder, bool enable) |
431 | { |
441 | { |
432 | struct drm_device *dev = encoder->dev; |
442 | struct drm_device *dev = encoder->dev; |
433 | struct radeon_device *rdev = dev->dev_private; |
443 | struct radeon_device *rdev = dev->dev_private; |
434 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
444 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
435 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
445 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
436 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
446 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
437 | 447 | ||
438 | if (!dig || !dig->afmt) |
448 | if (!dig || !dig->afmt) |
439 | return; |
449 | return; |
440 | 450 | ||
441 | if (enable && connector && |
451 | if (enable && connector && |
442 | drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
452 | drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
443 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
453 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
444 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
454 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
445 | struct radeon_connector_atom_dig *dig_connector; |
455 | struct radeon_connector_atom_dig *dig_connector; |
446 | uint32_t val; |
456 | uint32_t val; |
447 | 457 | ||
448 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
458 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
449 | AFMT_AUDIO_SAMPLE_SEND); |
459 | AFMT_AUDIO_SAMPLE_SEND); |
450 | 460 | ||
451 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, |
461 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, |
452 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); |
462 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); |
453 | 463 | ||
454 | if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) { |
464 | if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) { |
455 | dig_connector = radeon_connector->con_priv; |
465 | dig_connector = radeon_connector->con_priv; |
456 | val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); |
466 | val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); |
457 | val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); |
467 | val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); |
458 | 468 | ||
459 | if (dig_connector->dp_clock == 162000) |
469 | if (dig_connector->dp_clock == 162000) |
460 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3); |
470 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3); |
461 | else |
471 | else |
462 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); |
472 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); |
463 | 473 | ||
464 | WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); |
474 | WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); |
465 | } |
475 | } |
466 | 476 | ||
467 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, |
477 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, |
468 | EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ |
478 | EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ |
469 | EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ |
479 | EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ |
470 | EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ |
480 | EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ |
471 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ |
481 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ |
472 | } else { |
482 | } else { |
473 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); |
483 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); |
474 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
484 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
475 | ~AFMT_AUDIO_SAMPLE_SEND); |
485 | ~AFMT_AUDIO_SAMPLE_SEND); |
476 | } |
486 | } |
477 | 487 | ||
478 | dig->afmt->enabled = enable; |
488 | dig->afmt->enabled = enable; |
479 | }><>><>><>><>><>><>><>><>><>><>><>>> |
489 | }><>><>><>><>><>><>><>><>><>><>><>>> |