WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/evergreen_blit_kms.c


/*
 * Copyright 2010 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     Alex Deucher 
 */
 
#include 
#include 
#include "radeon.h"
 
#include "evergreend.h"
#include "evergreen_blit_shaders.h"
#include "cayman_blit_shaders.h"
#include "radeon_blit_common.h"
 
/* emits 17 */
static void
set_render_target(struct radeon_device *rdev, int format,
		  int w, int h, u64 gpu_addr)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
	u32 cb_color_info;
	int pitch, slice;
 
	h = ALIGN(h, 8);
	if (h < 8)
		h = 8;
 
	cb_color_info = CB_FORMAT(format) |
		CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
		CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
	pitch = (w / 8) - 1;
	slice = ((w * h) / 64) - 1;
 
	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
	radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
	radeon_ring_write(ring, gpu_addr >> 8);
	radeon_ring_write(ring, pitch);
	radeon_ring_write(ring, slice);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, cb_color_info);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, (w - 1) | ((h - 1) << 16));
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 0);
}
 
/* emits 5dw */
static void
cp_set_surface_sync(struct radeon_device *rdev,
		    u32 sync_type, u32 size,
		    u64 mc_addr)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
	u32 cp_coher_size;
 
	if (size == 0xffffffff)
		cp_coher_size = 0xffffffff;
	else
		cp_coher_size = ((size + 255) >> 8);
 
	if (rdev->family >= CHIP_CAYMAN) {
		/* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync
		 * to the RB directly. For IBs, the CP programs this as part of the
		 * surface_sync packet.
		 */
		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
		radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
		radeon_ring_write(ring, 0); /* CP_COHER_CNTL2 */
	}
	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
	radeon_ring_write(ring, sync_type);
	radeon_ring_write(ring, cp_coher_size);
	radeon_ring_write(ring, mc_addr >> 8);
	radeon_ring_write(ring, 10); /* poll interval */
}
 
/* emits 11dw + 1 surface sync = 16dw */
static void
set_shaders(struct radeon_device *rdev)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
	u64 gpu_addr;
 
	/* VS */
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
	radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
	radeon_ring_write(ring, gpu_addr >> 8);
	radeon_ring_write(ring, 2);
	radeon_ring_write(ring, 0);
 
	/* PS */
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
	radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
	radeon_ring_write(ring, gpu_addr >> 8);
	radeon_ring_write(ring, 1);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 2);
 
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
}
 
/* emits 10 + 1 sync (5) = 15 */
static void
set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
	u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
 
	/* high addr, stride */
	sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
		SQ_VTXC_STRIDE(16);
#ifdef __BIG_ENDIAN
	sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
#endif
	/* xyzw swizzles */
	sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) |
		SQ_VTCX_SEL_Y(SQ_SEL_Y) |
		SQ_VTCX_SEL_Z(SQ_SEL_Z) |
		SQ_VTCX_SEL_W(SQ_SEL_W);
 
	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
	radeon_ring_write(ring, 0x580);
	radeon_ring_write(ring, gpu_addr & 0xffffffff);
	radeon_ring_write(ring, 48 - 1); /* size */
	radeon_ring_write(ring, sq_vtx_constant_word2);
	radeon_ring_write(ring, sq_vtx_constant_word3);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
 
	if ((rdev->family == CHIP_CEDAR) ||
	    (rdev->family == CHIP_PALM) ||
	    (rdev->family == CHIP_SUMO) ||
	    (rdev->family == CHIP_SUMO2) ||
	    (rdev->family == CHIP_CAICOS))
		cp_set_surface_sync(rdev,
				    PACKET3_TC_ACTION_ENA, 48, gpu_addr);
	else
		cp_set_surface_sync(rdev,
				    PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 
}
 
/* emits 10 */
static void
set_tex_resource(struct radeon_device *rdev,
		 int format, int w, int h, int pitch,
		 u64 gpu_addr, u32 size)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
	u32 sq_tex_resource_word0, sq_tex_resource_word1;
	u32 sq_tex_resource_word4, sq_tex_resource_word7;
 
	if (h < 1)
		h = 1;
 
	sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);
	sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
				  ((w - 1) << 18));
	sq_tex_resource_word1 = ((h - 1) << 0) |
				TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
	/* xyzw swizzles */
	sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) |
				TEX_DST_SEL_Y(SQ_SEL_Y) |
				TEX_DST_SEL_Z(SQ_SEL_Z) |
				TEX_DST_SEL_W(SQ_SEL_W);
 
	sq_tex_resource_word7 = format |
		S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
 
	cp_set_surface_sync(rdev,
			    PACKET3_TC_ACTION_ENA, size, gpu_addr);
 
	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, sq_tex_resource_word0);
	radeon_ring_write(ring, sq_tex_resource_word1);
	radeon_ring_write(ring, gpu_addr >> 8);
	radeon_ring_write(ring, gpu_addr >> 8);
	radeon_ring_write(ring, sq_tex_resource_word4);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, sq_tex_resource_word7);
}
 
/* emits 12 */
static void
set_scissors(struct radeon_device *rdev, int x1, int y1,
	     int x2, int y2)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
	/* workaround some hw bugs */
	if (x2 == 0)
		x1 = 1;
	if (y2 == 0)
		y1 = 1;
	if (rdev->family >= CHIP_CAYMAN) {
		if ((x2 == 1) && (y2 == 1))
			x2 = 2;
	}
 
	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
	radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
	radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
 
	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
	radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
	radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
 
	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
	radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
	radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
}
 
/* emits 10 */
static void
draw_auto(struct radeon_device *rdev)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
	radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
	radeon_ring_write(ring, DI_PT_RECTLIST);
 
	radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
	radeon_ring_write(ring,
#ifdef __BIG_ENDIAN
			  (2 << 2) |
#endif
			  DI_INDEX_SIZE_16_BIT);
 
	radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
	radeon_ring_write(ring, 1);
 
	radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
	radeon_ring_write(ring, 3);
	radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
 
}
 
/* emits 39 */
static void
set_default_state(struct radeon_device *rdev)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
	u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
	u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
	int num_ps_gprs, num_vs_gprs, num_temp_gprs;
	int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
	int num_hs_threads, num_ls_threads;
	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
	int num_hs_stack_entries, num_ls_stack_entries;
	u64 gpu_addr;
	int dwords;
 
	/* set clear context state */
	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
	radeon_ring_write(ring, 0);
 
	if (rdev->family < CHIP_CAYMAN) {
		switch (rdev->family) {
		case CHIP_CEDAR:
		default:
			num_ps_gprs = 93;
			num_vs_gprs = 46;
			num_temp_gprs = 4;
			num_gs_gprs = 31;
			num_es_gprs = 31;
			num_hs_gprs = 23;
			num_ls_gprs = 23;
			num_ps_threads = 96;
			num_vs_threads = 16;
			num_gs_threads = 16;
			num_es_threads = 16;
			num_hs_threads = 16;
			num_ls_threads = 16;
			num_ps_stack_entries = 42;
			num_vs_stack_entries = 42;
			num_gs_stack_entries = 42;
			num_es_stack_entries = 42;
			num_hs_stack_entries = 42;
			num_ls_stack_entries = 42;
			break;
		case CHIP_REDWOOD:
			num_ps_gprs = 93;
			num_vs_gprs = 46;
			num_temp_gprs = 4;
			num_gs_gprs = 31;
			num_es_gprs = 31;
			num_hs_gprs = 23;
			num_ls_gprs = 23;
			num_ps_threads = 128;
			num_vs_threads = 20;
			num_gs_threads = 20;
			num_es_threads = 20;
			num_hs_threads = 20;
			num_ls_threads = 20;
			num_ps_stack_entries = 42;
			num_vs_stack_entries = 42;
			num_gs_stack_entries = 42;
			num_es_stack_entries = 42;
			num_hs_stack_entries = 42;
			num_ls_stack_entries = 42;
			break;
		case CHIP_JUNIPER:
			num_ps_gprs = 93;
			num_vs_gprs = 46;
			num_temp_gprs = 4;
			num_gs_gprs = 31;
			num_es_gprs = 31;
			num_hs_gprs = 23;
			num_ls_gprs = 23;
			num_ps_threads = 128;
			num_vs_threads = 20;
			num_gs_threads = 20;
			num_es_threads = 20;
			num_hs_threads = 20;
			num_ls_threads = 20;
			num_ps_stack_entries = 85;
			num_vs_stack_entries = 85;
			num_gs_stack_entries = 85;
			num_es_stack_entries = 85;
			num_hs_stack_entries = 85;
			num_ls_stack_entries = 85;
			break;
		case CHIP_CYPRESS:
		case CHIP_HEMLOCK:
			num_ps_gprs = 93;
			num_vs_gprs = 46;
			num_temp_gprs = 4;
			num_gs_gprs = 31;
			num_es_gprs = 31;
			num_hs_gprs = 23;
			num_ls_gprs = 23;
			num_ps_threads = 128;
			num_vs_threads = 20;
			num_gs_threads = 20;
			num_es_threads = 20;
			num_hs_threads = 20;
			num_ls_threads = 20;
			num_ps_stack_entries = 85;
			num_vs_stack_entries = 85;
			num_gs_stack_entries = 85;
			num_es_stack_entries = 85;
			num_hs_stack_entries = 85;
			num_ls_stack_entries = 85;
			break;
		case CHIP_PALM:
			num_ps_gprs = 93;
			num_vs_gprs = 46;
			num_temp_gprs = 4;
			num_gs_gprs = 31;
			num_es_gprs = 31;
			num_hs_gprs = 23;
			num_ls_gprs = 23;
			num_ps_threads = 96;
			num_vs_threads = 16;
			num_gs_threads = 16;
			num_es_threads = 16;
			num_hs_threads = 16;
			num_ls_threads = 16;
			num_ps_stack_entries = 42;
			num_vs_stack_entries = 42;
			num_gs_stack_entries = 42;
			num_es_stack_entries = 42;
			num_hs_stack_entries = 42;
			num_ls_stack_entries = 42;
			break;
		case CHIP_SUMO:
			num_ps_gprs = 93;
			num_vs_gprs = 46;
			num_temp_gprs = 4;
			num_gs_gprs = 31;
			num_es_gprs = 31;
			num_hs_gprs = 23;
			num_ls_gprs = 23;
			num_ps_threads = 96;
			num_vs_threads = 25;
			num_gs_threads = 25;
			num_es_threads = 25;
			num_hs_threads = 25;
			num_ls_threads = 25;
			num_ps_stack_entries = 42;
			num_vs_stack_entries = 42;
			num_gs_stack_entries = 42;
			num_es_stack_entries = 42;
			num_hs_stack_entries = 42;
			num_ls_stack_entries = 42;
			break;
		case CHIP_SUMO2:
			num_ps_gprs = 93;
			num_vs_gprs = 46;
			num_temp_gprs = 4;
			num_gs_gprs = 31;
			num_es_gprs = 31;
			num_hs_gprs = 23;
			num_ls_gprs = 23;
			num_ps_threads = 96;
			num_vs_threads = 25;
			num_gs_threads = 25;
			num_es_threads = 25;
			num_hs_threads = 25;
			num_ls_threads = 25;
			num_ps_stack_entries = 85;
			num_vs_stack_entries = 85;
			num_gs_stack_entries = 85;
			num_es_stack_entries = 85;
			num_hs_stack_entries = 85;
			num_ls_stack_entries = 85;
			break;
		case CHIP_BARTS:
			num_ps_gprs = 93;
			num_vs_gprs = 46;
			num_temp_gprs = 4;
			num_gs_gprs = 31;
			num_es_gprs = 31;
			num_hs_gprs = 23;
			num_ls_gprs = 23;
			num_ps_threads = 128;
			num_vs_threads = 20;
			num_gs_threads = 20;
			num_es_threads = 20;
			num_hs_threads = 20;
			num_ls_threads = 20;
			num_ps_stack_entries = 85;
			num_vs_stack_entries = 85;
			num_gs_stack_entries = 85;
			num_es_stack_entries = 85;
			num_hs_stack_entries = 85;
			num_ls_stack_entries = 85;
			break;
		case CHIP_TURKS:
			num_ps_gprs = 93;
			num_vs_gprs = 46;
			num_temp_gprs = 4;
			num_gs_gprs = 31;
			num_es_gprs = 31;
			num_hs_gprs = 23;
			num_ls_gprs = 23;
			num_ps_threads = 128;
			num_vs_threads = 20;
			num_gs_threads = 20;
			num_es_threads = 20;
			num_hs_threads = 20;
			num_ls_threads = 20;
			num_ps_stack_entries = 42;
			num_vs_stack_entries = 42;
			num_gs_stack_entries = 42;
			num_es_stack_entries = 42;
			num_hs_stack_entries = 42;
			num_ls_stack_entries = 42;
			break;
		case CHIP_CAICOS:
			num_ps_gprs = 93;
			num_vs_gprs = 46;
			num_temp_gprs = 4;
			num_gs_gprs = 31;
			num_es_gprs = 31;
			num_hs_gprs = 23;
			num_ls_gprs = 23;
			num_ps_threads = 128;
			num_vs_threads = 10;
			num_gs_threads = 10;
			num_es_threads = 10;
			num_hs_threads = 10;
			num_ls_threads = 10;
			num_ps_stack_entries = 42;
			num_vs_stack_entries = 42;
			num_gs_stack_entries = 42;
			num_es_stack_entries = 42;
			num_hs_stack_entries = 42;
			num_ls_stack_entries = 42;
			break;
		}
 
		if ((rdev->family == CHIP_CEDAR) ||
		    (rdev->family == CHIP_PALM) ||
		    (rdev->family == CHIP_SUMO) ||
		    (rdev->family == CHIP_SUMO2) ||
		    (rdev->family == CHIP_CAICOS))
			sq_config = 0;
		else
			sq_config = VC_ENABLE;
 
		sq_config |= (EXPORT_SRC_C |
			      CS_PRIO(0) |
			      LS_PRIO(0) |
			      HS_PRIO(0) |
			      PS_PRIO(0) |
			      VS_PRIO(1) |
			      GS_PRIO(2) |
			      ES_PRIO(3));
 
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
					  NUM_VS_GPRS(num_vs_gprs) |
					  NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
					  NUM_ES_GPRS(num_es_gprs));
		sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
					  NUM_LS_GPRS(num_ls_gprs));
		sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
					   NUM_VS_THREADS(num_vs_threads) |
					   NUM_GS_THREADS(num_gs_threads) |
					   NUM_ES_THREADS(num_es_threads));
		sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
					     NUM_LS_THREADS(num_ls_threads));
		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
					    NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
					    NUM_ES_STACK_ENTRIES(num_es_stack_entries));
		sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
					    NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
 
		/* disable dyn gprs */
		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
		radeon_ring_write(ring, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
		radeon_ring_write(ring, 0);
 
		/* setup LDS */
		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
		radeon_ring_write(ring, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
		radeon_ring_write(ring, 0x10001000);
 
		/* SQ config */
		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 11));
		radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
		radeon_ring_write(ring, sq_config);
		radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
		radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
		radeon_ring_write(ring, sq_gpr_resource_mgmt_3);
		radeon_ring_write(ring, 0);
		radeon_ring_write(ring, 0);
		radeon_ring_write(ring, sq_thread_resource_mgmt);
		radeon_ring_write(ring, sq_thread_resource_mgmt_2);
		radeon_ring_write(ring, sq_stack_resource_mgmt_1);
		radeon_ring_write(ring, sq_stack_resource_mgmt_2);
		radeon_ring_write(ring, sq_stack_resource_mgmt_3);
	}
 
	/* CONTEXT_CONTROL */
	radeon_ring_write(ring, 0xc0012800);
	radeon_ring_write(ring, 0x80000000);
	radeon_ring_write(ring, 0x80000000);
 
	/* SQ_VTX_BASE_VTX_LOC */
	radeon_ring_write(ring, 0xc0026f00);
	radeon_ring_write(ring, 0x00000000);
	radeon_ring_write(ring, 0x00000000);
	radeon_ring_write(ring, 0x00000000);
 
	/* SET_SAMPLER */
	radeon_ring_write(ring, 0xc0036e00);
	radeon_ring_write(ring, 0x00000000);
	radeon_ring_write(ring, 0x00000012);
	radeon_ring_write(ring, 0x00000000);
	radeon_ring_write(ring, 0x00000000);
 
	/* set to DX10/11 mode */
	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
	radeon_ring_write(ring, 1);
 
	/* emit an IB pointing at default state */
	dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
	radeon_ring_write(ring, gpu_addr & 0xFFFFFFFC);
	radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
	radeon_ring_write(ring, dwords);
 
}
 
int evergreen_blit_init(struct radeon_device *rdev)
{
	u32 obj_size;
	int i, r, dwords;
	void *ptr;
	u32 packet2s[16];
	int num_packet2s = 0;
#if 0
	rdev->r600_blit.primitives.set_render_target = set_render_target;
	rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
	rdev->r600_blit.primitives.set_shaders = set_shaders;
	rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
	rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
	rdev->r600_blit.primitives.set_scissors = set_scissors;
	rdev->r600_blit.primitives.draw_auto = draw_auto;
	rdev->r600_blit.primitives.set_default_state = set_default_state;
 
	rdev->r600_blit.ring_size_common = 8; /* sync semaphore */
	rdev->r600_blit.ring_size_common += 55; /* shaders + def state */
	rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
	rdev->r600_blit.ring_size_common += 5; /* done copy */
	rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
 
	rdev->r600_blit.ring_size_per_loop = 74;
	if (rdev->family >= CHIP_CAYMAN)
		rdev->r600_blit.ring_size_per_loop += 9; /* additional DWs for surface sync */
 
	rdev->r600_blit.max_dim = 16384;
 
 
 
 
 
 
	rdev->r600_blit.state_offset = 0;
 
	if (rdev->family < CHIP_CAYMAN)
		rdev->r600_blit.state_len = evergreen_default_size;
	else
		rdev->r600_blit.state_len = cayman_default_size;
 
	dwords = rdev->r600_blit.state_len;
	while (dwords & 0xf) {
		packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
		dwords++;
	}
 
	obj_size = dwords * 4;
	obj_size = ALIGN(obj_size, 256);
 
	rdev->r600_blit.vs_offset = obj_size;
	if (rdev->family < CHIP_CAYMAN)
		obj_size += evergreen_vs_size * 4;
	else
		obj_size += cayman_vs_size * 4;
	obj_size = ALIGN(obj_size, 256);
 
	rdev->r600_blit.ps_offset = obj_size;
	if (rdev->family < CHIP_CAYMAN)
		obj_size += evergreen_ps_size * 4;
	else
		obj_size += cayman_ps_size * 4;
	obj_size = ALIGN(obj_size, 256);
 
	/* pin copy shader into vram if not already initialized */
	if (!rdev->r600_blit.shader_obj) {
		r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
				     RADEON_GEM_DOMAIN_VRAM,
				     NULL, &rdev->r600_blit.shader_obj);
	if (r) {
		DRM_ERROR("evergreen failed to allocate shader\n");
		return r;
	}
 
		r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
		if (unlikely(r != 0))
			return r;
		r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
				  &rdev->r600_blit.shader_gpu_addr);
		radeon_bo_unreserve(rdev->r600_blit.shader_obj);
	if (r) {
			dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
		return r;
	}
	}
 
	DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
		  obj_size,
		  rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
	if (r) {
		DRM_ERROR("failed to map blit object %d\n", r);
		return r;
	}
 
	if (rdev->family < CHIP_CAYMAN) {
        memcpy(ptr + rdev->r600_blit.state_offset,
			    evergreen_default_state, rdev->r600_blit.state_len * 4);
 
		if (num_packet2s)
            memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
				    packet2s, num_packet2s * 4);
		for (i = 0; i < evergreen_vs_size; i++)
			*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
		for (i = 0; i < evergreen_ps_size; i++)
			*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
	} else {
        memcpy(ptr + rdev->r600_blit.state_offset,
			    cayman_default_state, rdev->r600_blit.state_len * 4);
 
		if (num_packet2s)
            memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
				    packet2s, num_packet2s * 4);
		for (i = 0; i < cayman_vs_size; i++)
			*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
		for (i = 0; i < cayman_ps_size; i++)
			*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
	}
	radeon_bo_kunmap(rdev->r600_blit.shader_obj);
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 
 
 
 
 
 
 
 
 
 
 
 
//   radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 
#endif
 
	return 0;
}

Rev 2997	Rev 3192
1	/*	1	/*
2	* Copyright 2010 Advanced Micro Devices, Inc.	2	* Copyright 2010 Advanced Micro Devices, Inc.
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR	18	* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21	* DEALINGS IN THE SOFTWARE.	21	* DEALINGS IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Alex Deucher	24	* Alex Deucher
25	*/	25	*/
26		26
27	#include	27	#include
28	#include	28	#include
29	#include "radeon.h"	29	#include "radeon.h"
30		30
31	#include "evergreend.h"	31	#include "evergreend.h"
32	#include "evergreen_blit_shaders.h"	32	#include "evergreen_blit_shaders.h"
33	#include "cayman_blit_shaders.h"	33	#include "cayman_blit_shaders.h"
34	#include "radeon_blit_common.h"	34	#include "radeon_blit_common.h"
35		35
36	/* emits 17 */	36	/* emits 17 */
37	static void	37	static void
38	set_render_target(struct radeon_device *rdev, int format,	38	set_render_target(struct radeon_device *rdev, int format,
39	int w, int h, u64 gpu_addr)	39	int w, int h, u64 gpu_addr)
40	{	40	{
41	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	41	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
42	u32 cb_color_info;	42	u32 cb_color_info;
43	int pitch, slice;	43	int pitch, slice;
44		44
45	h = ALIGN(h, 8);	45	h = ALIGN(h, 8);
46	if (h < 8)	46	if (h < 8)
47	h = 8;	47	h = 8;
48		48
49	cb_color_info = CB_FORMAT(format) \|	49	cb_color_info = CB_FORMAT(format) \|
50	CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) \|	50	CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) \|
51	CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);	51	CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
52	pitch = (w / 8) - 1;	52	pitch = (w / 8) - 1;
53	slice = ((w * h) / 64) - 1;	53	slice = ((w * h) / 64) - 1;
54		54
55	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15));	55	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
56	radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);	56	radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
57	radeon_ring_write(ring, gpu_addr >> 8);	57	radeon_ring_write(ring, gpu_addr >> 8);
58	radeon_ring_write(ring, pitch);	58	radeon_ring_write(ring, pitch);
59	radeon_ring_write(ring, slice);	59	radeon_ring_write(ring, slice);
60	radeon_ring_write(ring, 0);	60	radeon_ring_write(ring, 0);
61	radeon_ring_write(ring, cb_color_info);	61	radeon_ring_write(ring, cb_color_info);
62	radeon_ring_write(ring, 0);	62	radeon_ring_write(ring, 0);
63	radeon_ring_write(ring, (w - 1) \| ((h - 1) << 16));	63	radeon_ring_write(ring, (w - 1) \| ((h - 1) << 16));
64	radeon_ring_write(ring, 0);	64	radeon_ring_write(ring, 0);
65	radeon_ring_write(ring, 0);	65	radeon_ring_write(ring, 0);
66	radeon_ring_write(ring, 0);	66	radeon_ring_write(ring, 0);
67	radeon_ring_write(ring, 0);	67	radeon_ring_write(ring, 0);
68	radeon_ring_write(ring, 0);	68	radeon_ring_write(ring, 0);
69	radeon_ring_write(ring, 0);	69	radeon_ring_write(ring, 0);
70	radeon_ring_write(ring, 0);	70	radeon_ring_write(ring, 0);
71	radeon_ring_write(ring, 0);	71	radeon_ring_write(ring, 0);
72	}	72	}
73		73
74	/* emits 5dw */	74	/* emits 5dw */
75	static void	75	static void
76	cp_set_surface_sync(struct radeon_device *rdev,	76	cp_set_surface_sync(struct radeon_device *rdev,
77	u32 sync_type, u32 size,	77	u32 sync_type, u32 size,
78	u64 mc_addr)	78	u64 mc_addr)
79	{	79	{
80	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	80	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
81	u32 cp_coher_size;	81	u32 cp_coher_size;
82		82
83	if (size == 0xffffffff)	83	if (size == 0xffffffff)
84	cp_coher_size = 0xffffffff;	84	cp_coher_size = 0xffffffff;
85	else	85	else
86	cp_coher_size = ((size + 255) >> 8);	86	cp_coher_size = ((size + 255) >> 8);
87		87
88	if (rdev->family >= CHIP_CAYMAN) {	88	if (rdev->family >= CHIP_CAYMAN) {
89	/* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync	89	/* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync
90	* to the RB directly. For IBs, the CP programs this as part of the	90	* to the RB directly. For IBs, the CP programs this as part of the
91	* surface_sync packet.	91	* surface_sync packet.
92	*/	92	*/
93	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));	93	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
94	radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);	94	radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
95	radeon_ring_write(ring, 0); /* CP_COHER_CNTL2 */	95	radeon_ring_write(ring, 0); /* CP_COHER_CNTL2 */
96	}	96	}
97	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));	97	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
98	radeon_ring_write(ring, sync_type);	98	radeon_ring_write(ring, sync_type);
99	radeon_ring_write(ring, cp_coher_size);	99	radeon_ring_write(ring, cp_coher_size);
100	radeon_ring_write(ring, mc_addr >> 8);	100	radeon_ring_write(ring, mc_addr >> 8);
101	radeon_ring_write(ring, 10); /* poll interval */	101	radeon_ring_write(ring, 10); /* poll interval */
102	}	102	}
103		103
104	/* emits 11dw + 1 surface sync = 16dw */	104	/* emits 11dw + 1 surface sync = 16dw */
105	static void	105	static void
106	set_shaders(struct radeon_device *rdev)	106	set_shaders(struct radeon_device *rdev)
107	{	107	{
108	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	108	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
109	u64 gpu_addr;	109	u64 gpu_addr;
110		110
111	/* VS */	111	/* VS */
112	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;	112	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
113	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3));	113	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
114	radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);	114	radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
115	radeon_ring_write(ring, gpu_addr >> 8);	115	radeon_ring_write(ring, gpu_addr >> 8);
116	radeon_ring_write(ring, 2);	116	radeon_ring_write(ring, 2);
117	radeon_ring_write(ring, 0);	117	radeon_ring_write(ring, 0);
118		118
119	/* PS */	119	/* PS */
120	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;	120	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
121	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4));	121	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
122	radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);	122	radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
123	radeon_ring_write(ring, gpu_addr >> 8);	123	radeon_ring_write(ring, gpu_addr >> 8);
124	radeon_ring_write(ring, 1);	124	radeon_ring_write(ring, 1);
125	radeon_ring_write(ring, 0);	125	radeon_ring_write(ring, 0);
126	radeon_ring_write(ring, 2);	126	radeon_ring_write(ring, 2);
127		127
128	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;	128	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
129	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);	129	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
130	}	130	}
131		131
132	/* emits 10 + 1 sync (5) = 15 */	132	/* emits 10 + 1 sync (5) = 15 */
133	static void	133	static void
134	set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)	134	set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
135	{	135	{
136	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	136	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
137	u32 sq_vtx_constant_word2, sq_vtx_constant_word3;	137	u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
138		138
139	/* high addr, stride */	139	/* high addr, stride */
140	sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) \|	140	sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) \|
141	SQ_VTXC_STRIDE(16);	141	SQ_VTXC_STRIDE(16);
142	#ifdef __BIG_ENDIAN	142	#ifdef __BIG_ENDIAN
143	sq_vtx_constant_word2 \|= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);	143	sq_vtx_constant_word2 \|= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
144	#endif	144	#endif
145	/* xyzw swizzles */	145	/* xyzw swizzles */
146	sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) \|	146	sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) \|
147	SQ_VTCX_SEL_Y(SQ_SEL_Y) \|	147	SQ_VTCX_SEL_Y(SQ_SEL_Y) \|
148	SQ_VTCX_SEL_Z(SQ_SEL_Z) \|	148	SQ_VTCX_SEL_Z(SQ_SEL_Z) \|
149	SQ_VTCX_SEL_W(SQ_SEL_W);	149	SQ_VTCX_SEL_W(SQ_SEL_W);
150		150
151	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));	151	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
152	radeon_ring_write(ring, 0x580);	152	radeon_ring_write(ring, 0x580);
153	radeon_ring_write(ring, gpu_addr & 0xffffffff);	153	radeon_ring_write(ring, gpu_addr & 0xffffffff);
154	radeon_ring_write(ring, 48 - 1); /* size */	154	radeon_ring_write(ring, 48 - 1); /* size */
155	radeon_ring_write(ring, sq_vtx_constant_word2);	155	radeon_ring_write(ring, sq_vtx_constant_word2);
156	radeon_ring_write(ring, sq_vtx_constant_word3);	156	radeon_ring_write(ring, sq_vtx_constant_word3);
157	radeon_ring_write(ring, 0);	157	radeon_ring_write(ring, 0);
158	radeon_ring_write(ring, 0);	158	radeon_ring_write(ring, 0);
159	radeon_ring_write(ring, 0);	159	radeon_ring_write(ring, 0);
160	radeon_ring_write(ring, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));	160	radeon_ring_write(ring, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
161		161
162	if ((rdev->family == CHIP_CEDAR) \|\|	162	if ((rdev->family == CHIP_CEDAR) \|\|
163	(rdev->family == CHIP_PALM) \|\|	163	(rdev->family == CHIP_PALM) \|\|
164	(rdev->family == CHIP_SUMO) \|\|	164	(rdev->family == CHIP_SUMO) \|\|
165	(rdev->family == CHIP_SUMO2) \|\|	165	(rdev->family == CHIP_SUMO2) \|\|
166	(rdev->family == CHIP_CAICOS))	166	(rdev->family == CHIP_CAICOS))
167	cp_set_surface_sync(rdev,	167	cp_set_surface_sync(rdev,
168	PACKET3_TC_ACTION_ENA, 48, gpu_addr);	168	PACKET3_TC_ACTION_ENA, 48, gpu_addr);
169	else	169	else
170	cp_set_surface_sync(rdev,	170	cp_set_surface_sync(rdev,
171	PACKET3_VC_ACTION_ENA, 48, gpu_addr);	171	PACKET3_VC_ACTION_ENA, 48, gpu_addr);
172		172
173	}	173	}
174		174
175	/* emits 10 */	175	/* emits 10 */
176	static void	176	static void
177	set_tex_resource(struct radeon_device *rdev,	177	set_tex_resource(struct radeon_device *rdev,
178	int format, int w, int h, int pitch,	178	int format, int w, int h, int pitch,
179	u64 gpu_addr, u32 size)	179	u64 gpu_addr, u32 size)
180	{	180	{
181	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	181	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
182	u32 sq_tex_resource_word0, sq_tex_resource_word1;	182	u32 sq_tex_resource_word0, sq_tex_resource_word1;
183	u32 sq_tex_resource_word4, sq_tex_resource_word7;	183	u32 sq_tex_resource_word4, sq_tex_resource_word7;
184		184
185	if (h < 1)	185	if (h < 1)
186	h = 1;	186	h = 1;
187		187
188	sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);	188	sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);
189	sq_tex_resource_word0 \|= ((((pitch >> 3) - 1) << 6) \|	189	sq_tex_resource_word0 \|= ((((pitch >> 3) - 1) << 6) \|
190	((w - 1) << 18));	190	((w - 1) << 18));
191	sq_tex_resource_word1 = ((h - 1) << 0) \|	191	sq_tex_resource_word1 = ((h - 1) << 0) \|
192	TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);	192	TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
193	/* xyzw swizzles */	193	/* xyzw swizzles */
194	sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) \|	194	sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) \|
195	TEX_DST_SEL_Y(SQ_SEL_Y) \|	195	TEX_DST_SEL_Y(SQ_SEL_Y) \|
196	TEX_DST_SEL_Z(SQ_SEL_Z) \|	196	TEX_DST_SEL_Z(SQ_SEL_Z) \|
197	TEX_DST_SEL_W(SQ_SEL_W);	197	TEX_DST_SEL_W(SQ_SEL_W);
198		198
199	sq_tex_resource_word7 = format \|	199	sq_tex_resource_word7 = format \|
200	S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);	200	S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
201		201
202	cp_set_surface_sync(rdev,	202	cp_set_surface_sync(rdev,
203	PACKET3_TC_ACTION_ENA, size, gpu_addr);	203	PACKET3_TC_ACTION_ENA, size, gpu_addr);
204		204
205	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));	205	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
206	radeon_ring_write(ring, 0);	206	radeon_ring_write(ring, 0);
207	radeon_ring_write(ring, sq_tex_resource_word0);	207	radeon_ring_write(ring, sq_tex_resource_word0);
208	radeon_ring_write(ring, sq_tex_resource_word1);	208	radeon_ring_write(ring, sq_tex_resource_word1);
209	radeon_ring_write(ring, gpu_addr >> 8);	209	radeon_ring_write(ring, gpu_addr >> 8);
210	radeon_ring_write(ring, gpu_addr >> 8);	210	radeon_ring_write(ring, gpu_addr >> 8);
211	radeon_ring_write(ring, sq_tex_resource_word4);	211	radeon_ring_write(ring, sq_tex_resource_word4);
212	radeon_ring_write(ring, 0);	212	radeon_ring_write(ring, 0);
213	radeon_ring_write(ring, 0);	213	radeon_ring_write(ring, 0);
214	radeon_ring_write(ring, sq_tex_resource_word7);	214	radeon_ring_write(ring, sq_tex_resource_word7);
215	}	215	}
216		216
217	/* emits 12 */	217	/* emits 12 */
218	static void	218	static void
219	set_scissors(struct radeon_device *rdev, int x1, int y1,	219	set_scissors(struct radeon_device *rdev, int x1, int y1,
220	int x2, int y2)	220	int x2, int y2)
221	{	221	{
222	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	222	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
223	/* workaround some hw bugs */	223	/* workaround some hw bugs */
224	if (x2 == 0)	224	if (x2 == 0)
225	x1 = 1;	225	x1 = 1;
226	if (y2 == 0)	226	if (y2 == 0)
227	y1 = 1;	227	y1 = 1;
228	if (rdev->family >= CHIP_CAYMAN) {	228	if (rdev->family >= CHIP_CAYMAN) {
229	if ((x2 == 1) && (y2 == 1))	229	if ((x2 == 1) && (y2 == 1))
230	x2 = 2;	230	x2 = 2;
231	}	231	}
232		232
233	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));	233	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
234	radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);	234	radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
235	radeon_ring_write(ring, (x1 << 0) \| (y1 << 16));	235	radeon_ring_write(ring, (x1 << 0) \| (y1 << 16));
236	radeon_ring_write(ring, (x2 << 0) \| (y2 << 16));	236	radeon_ring_write(ring, (x2 << 0) \| (y2 << 16));
237		237
238	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));	238	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
239	radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);	239	radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
240	radeon_ring_write(ring, (x1 << 0) \| (y1 << 16) \| (1 << 31));	240	radeon_ring_write(ring, (x1 << 0) \| (y1 << 16) \| (1 << 31));
241	radeon_ring_write(ring, (x2 << 0) \| (y2 << 16));	241	radeon_ring_write(ring, (x2 << 0) \| (y2 << 16));
242		242
243	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));	243	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
244	radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);	244	radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
245	radeon_ring_write(ring, (x1 << 0) \| (y1 << 16) \| (1 << 31));	245	radeon_ring_write(ring, (x1 << 0) \| (y1 << 16) \| (1 << 31));
246	radeon_ring_write(ring, (x2 << 0) \| (y2 << 16));	246	radeon_ring_write(ring, (x2 << 0) \| (y2 << 16));
247	}	247	}
248		248
249	/* emits 10 */	249	/* emits 10 */
250	static void	250	static void
251	draw_auto(struct radeon_device *rdev)	251	draw_auto(struct radeon_device *rdev)
252	{	252	{
253	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	253	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
254	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));	254	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
255	radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);	255	radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
256	radeon_ring_write(ring, DI_PT_RECTLIST);	256	radeon_ring_write(ring, DI_PT_RECTLIST);
257		257
258	radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));	258	radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
259	radeon_ring_write(ring,	259	radeon_ring_write(ring,
260	#ifdef __BIG_ENDIAN	260	#ifdef __BIG_ENDIAN
261	(2 << 2) \|	261	(2 << 2) \|
262	#endif	262	#endif
263	DI_INDEX_SIZE_16_BIT);	263	DI_INDEX_SIZE_16_BIT);
264		264
265	radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));	265	radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
266	radeon_ring_write(ring, 1);	266	radeon_ring_write(ring, 1);
267		267
268	radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));	268	radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
269	radeon_ring_write(ring, 3);	269	radeon_ring_write(ring, 3);
270	radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);	270	radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
271		271
272	}	272	}
273		273
274	/* emits 39 */	274	/* emits 39 */
275	static void	275	static void
276	set_default_state(struct radeon_device *rdev)	276	set_default_state(struct radeon_device *rdev)
277	{	277	{
278	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	278	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
279	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;	279	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
280	u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;	280	u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
281	u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;	281	u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
282	int num_ps_gprs, num_vs_gprs, num_temp_gprs;	282	int num_ps_gprs, num_vs_gprs, num_temp_gprs;
283	int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;	283	int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
284	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;	284	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
285	int num_hs_threads, num_ls_threads;	285	int num_hs_threads, num_ls_threads;
286	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;	286	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
287	int num_hs_stack_entries, num_ls_stack_entries;	287	int num_hs_stack_entries, num_ls_stack_entries;
288	u64 gpu_addr;	288	u64 gpu_addr;
289	int dwords;	289	int dwords;
290		290
291	/* set clear context state */	291	/* set clear context state */
292	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));	292	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
293	radeon_ring_write(ring, 0);	293	radeon_ring_write(ring, 0);
294		294
295	if (rdev->family < CHIP_CAYMAN) {	295	if (rdev->family < CHIP_CAYMAN) {
296	switch (rdev->family) {	296	switch (rdev->family) {
297	case CHIP_CEDAR:	297	case CHIP_CEDAR:
298	default:	298	default:
299	num_ps_gprs = 93;	299	num_ps_gprs = 93;
300	num_vs_gprs = 46;	300	num_vs_gprs = 46;
301	num_temp_gprs = 4;	301	num_temp_gprs = 4;
302	num_gs_gprs = 31;	302	num_gs_gprs = 31;
303	num_es_gprs = 31;	303	num_es_gprs = 31;
304	num_hs_gprs = 23;	304	num_hs_gprs = 23;
305	num_ls_gprs = 23;	305	num_ls_gprs = 23;
306	num_ps_threads = 96;	306	num_ps_threads = 96;
307	num_vs_threads = 16;	307	num_vs_threads = 16;
308	num_gs_threads = 16;	308	num_gs_threads = 16;
309	num_es_threads = 16;	309	num_es_threads = 16;
310	num_hs_threads = 16;	310	num_hs_threads = 16;
311	num_ls_threads = 16;	311	num_ls_threads = 16;
312	num_ps_stack_entries = 42;	312	num_ps_stack_entries = 42;
313	num_vs_stack_entries = 42;	313	num_vs_stack_entries = 42;
314	num_gs_stack_entries = 42;	314	num_gs_stack_entries = 42;
315	num_es_stack_entries = 42;	315	num_es_stack_entries = 42;
316	num_hs_stack_entries = 42;	316	num_hs_stack_entries = 42;
317	num_ls_stack_entries = 42;	317	num_ls_stack_entries = 42;
318	break;	318	break;
319	case CHIP_REDWOOD:	319	case CHIP_REDWOOD:
320	num_ps_gprs = 93;	320	num_ps_gprs = 93;
321	num_vs_gprs = 46;	321	num_vs_gprs = 46;
322	num_temp_gprs = 4;	322	num_temp_gprs = 4;
323	num_gs_gprs = 31;	323	num_gs_gprs = 31;
324	num_es_gprs = 31;	324	num_es_gprs = 31;
325	num_hs_gprs = 23;	325	num_hs_gprs = 23;
326	num_ls_gprs = 23;	326	num_ls_gprs = 23;
327	num_ps_threads = 128;	327	num_ps_threads = 128;
328	num_vs_threads = 20;	328	num_vs_threads = 20;
329	num_gs_threads = 20;	329	num_gs_threads = 20;
330	num_es_threads = 20;	330	num_es_threads = 20;
331	num_hs_threads = 20;	331	num_hs_threads = 20;
332	num_ls_threads = 20;	332	num_ls_threads = 20;
333	num_ps_stack_entries = 42;	333	num_ps_stack_entries = 42;
334	num_vs_stack_entries = 42;	334	num_vs_stack_entries = 42;
335	num_gs_stack_entries = 42;	335	num_gs_stack_entries = 42;
336	num_es_stack_entries = 42;	336	num_es_stack_entries = 42;
337	num_hs_stack_entries = 42;	337	num_hs_stack_entries = 42;
338	num_ls_stack_entries = 42;	338	num_ls_stack_entries = 42;
339	break;	339	break;
340	case CHIP_JUNIPER:	340	case CHIP_JUNIPER:
341	num_ps_gprs = 93;	341	num_ps_gprs = 93;
342	num_vs_gprs = 46;	342	num_vs_gprs = 46;
343	num_temp_gprs = 4;	343	num_temp_gprs = 4;
344	num_gs_gprs = 31;	344	num_gs_gprs = 31;
345	num_es_gprs = 31;	345	num_es_gprs = 31;
346	num_hs_gprs = 23;	346	num_hs_gprs = 23;
347	num_ls_gprs = 23;	347	num_ls_gprs = 23;
348	num_ps_threads = 128;	348	num_ps_threads = 128;
349	num_vs_threads = 20;	349	num_vs_threads = 20;
350	num_gs_threads = 20;	350	num_gs_threads = 20;
351	num_es_threads = 20;	351	num_es_threads = 20;
352	num_hs_threads = 20;	352	num_hs_threads = 20;
353	num_ls_threads = 20;	353	num_ls_threads = 20;
354	num_ps_stack_entries = 85;	354	num_ps_stack_entries = 85;
355	num_vs_stack_entries = 85;	355	num_vs_stack_entries = 85;
356	num_gs_stack_entries = 85;	356	num_gs_stack_entries = 85;
357	num_es_stack_entries = 85;	357	num_es_stack_entries = 85;
358	num_hs_stack_entries = 85;	358	num_hs_stack_entries = 85;
359	num_ls_stack_entries = 85;	359	num_ls_stack_entries = 85;
360	break;	360	break;
361	case CHIP_CYPRESS:	361	case CHIP_CYPRESS:
362	case CHIP_HEMLOCK:	362	case CHIP_HEMLOCK:
363	num_ps_gprs = 93;	363	num_ps_gprs = 93;
364	num_vs_gprs = 46;	364	num_vs_gprs = 46;
365	num_temp_gprs = 4;	365	num_temp_gprs = 4;
366	num_gs_gprs = 31;	366	num_gs_gprs = 31;
367	num_es_gprs = 31;	367	num_es_gprs = 31;
368	num_hs_gprs = 23;	368	num_hs_gprs = 23;
369	num_ls_gprs = 23;	369	num_ls_gprs = 23;
370	num_ps_threads = 128;	370	num_ps_threads = 128;
371	num_vs_threads = 20;	371	num_vs_threads = 20;
372	num_gs_threads = 20;	372	num_gs_threads = 20;
373	num_es_threads = 20;	373	num_es_threads = 20;
374	num_hs_threads = 20;	374	num_hs_threads = 20;
375	num_ls_threads = 20;	375	num_ls_threads = 20;
376	num_ps_stack_entries = 85;	376	num_ps_stack_entries = 85;
377	num_vs_stack_entries = 85;	377	num_vs_stack_entries = 85;
378	num_gs_stack_entries = 85;	378	num_gs_stack_entries = 85;
379	num_es_stack_entries = 85;	379	num_es_stack_entries = 85;
380	num_hs_stack_entries = 85;	380	num_hs_stack_entries = 85;
381	num_ls_stack_entries = 85;	381	num_ls_stack_entries = 85;
382	break;	382	break;
383	case CHIP_PALM:	383	case CHIP_PALM:
384	num_ps_gprs = 93;	384	num_ps_gprs = 93;
385	num_vs_gprs = 46;	385	num_vs_gprs = 46;
386	num_temp_gprs = 4;	386	num_temp_gprs = 4;
387	num_gs_gprs = 31;	387	num_gs_gprs = 31;
388	num_es_gprs = 31;	388	num_es_gprs = 31;
389	num_hs_gprs = 23;	389	num_hs_gprs = 23;
390	num_ls_gprs = 23;	390	num_ls_gprs = 23;
391	num_ps_threads = 96;	391	num_ps_threads = 96;
392	num_vs_threads = 16;	392	num_vs_threads = 16;
393	num_gs_threads = 16;	393	num_gs_threads = 16;
394	num_es_threads = 16;	394	num_es_threads = 16;
395	num_hs_threads = 16;	395	num_hs_threads = 16;
396	num_ls_threads = 16;	396	num_ls_threads = 16;
397	num_ps_stack_entries = 42;	397	num_ps_stack_entries = 42;
398	num_vs_stack_entries = 42;	398	num_vs_stack_entries = 42;
399	num_gs_stack_entries = 42;	399	num_gs_stack_entries = 42;
400	num_es_stack_entries = 42;	400	num_es_stack_entries = 42;
401	num_hs_stack_entries = 42;	401	num_hs_stack_entries = 42;
402	num_ls_stack_entries = 42;	402	num_ls_stack_entries = 42;
403	break;	403	break;
404	case CHIP_SUMO:	404	case CHIP_SUMO:
405	num_ps_gprs = 93;	405	num_ps_gprs = 93;
406	num_vs_gprs = 46;	406	num_vs_gprs = 46;
407	num_temp_gprs = 4;	407	num_temp_gprs = 4;
408	num_gs_gprs = 31;	408	num_gs_gprs = 31;
409	num_es_gprs = 31;	409	num_es_gprs = 31;
410	num_hs_gprs = 23;	410	num_hs_gprs = 23;
411	num_ls_gprs = 23;	411	num_ls_gprs = 23;
412	num_ps_threads = 96;	412	num_ps_threads = 96;
413	num_vs_threads = 25;	413	num_vs_threads = 25;
414	num_gs_threads = 25;	414	num_gs_threads = 25;
415	num_es_threads = 25;	415	num_es_threads = 25;
416	num_hs_threads = 25;	416	num_hs_threads = 25;
417	num_ls_threads = 25;	417	num_ls_threads = 25;
418	num_ps_stack_entries = 42;	418	num_ps_stack_entries = 42;
419	num_vs_stack_entries = 42;	419	num_vs_stack_entries = 42;
420	num_gs_stack_entries = 42;	420	num_gs_stack_entries = 42;
421	num_es_stack_entries = 42;	421	num_es_stack_entries = 42;
422	num_hs_stack_entries = 42;	422	num_hs_stack_entries = 42;
423	num_ls_stack_entries = 42;	423	num_ls_stack_entries = 42;
424	break;	424	break;
425	case CHIP_SUMO2:	425	case CHIP_SUMO2:
426	num_ps_gprs = 93;	426	num_ps_gprs = 93;
427	num_vs_gprs = 46;	427	num_vs_gprs = 46;
428	num_temp_gprs = 4;	428	num_temp_gprs = 4;
429	num_gs_gprs = 31;	429	num_gs_gprs = 31;
430	num_es_gprs = 31;	430	num_es_gprs = 31;
431	num_hs_gprs = 23;	431	num_hs_gprs = 23;
432	num_ls_gprs = 23;	432	num_ls_gprs = 23;
433	num_ps_threads = 96;	433	num_ps_threads = 96;
434	num_vs_threads = 25;	434	num_vs_threads = 25;
435	num_gs_threads = 25;	435	num_gs_threads = 25;
436	num_es_threads = 25;	436	num_es_threads = 25;
437	num_hs_threads = 25;	437	num_hs_threads = 25;
438	num_ls_threads = 25;	438	num_ls_threads = 25;
439	num_ps_stack_entries = 85;	439	num_ps_stack_entries = 85;
440	num_vs_stack_entries = 85;	440	num_vs_stack_entries = 85;
441	num_gs_stack_entries = 85;	441	num_gs_stack_entries = 85;
442	num_es_stack_entries = 85;	442	num_es_stack_entries = 85;
443	num_hs_stack_entries = 85;	443	num_hs_stack_entries = 85;
444	num_ls_stack_entries = 85;	444	num_ls_stack_entries = 85;
445	break;	445	break;
446	case CHIP_BARTS:	446	case CHIP_BARTS:
447	num_ps_gprs = 93;	447	num_ps_gprs = 93;
448	num_vs_gprs = 46;	448	num_vs_gprs = 46;
449	num_temp_gprs = 4;	449	num_temp_gprs = 4;
450	num_gs_gprs = 31;	450	num_gs_gprs = 31;
451	num_es_gprs = 31;	451	num_es_gprs = 31;
452	num_hs_gprs = 23;	452	num_hs_gprs = 23;
453	num_ls_gprs = 23;	453	num_ls_gprs = 23;
454	num_ps_threads = 128;	454	num_ps_threads = 128;
455	num_vs_threads = 20;	455	num_vs_threads = 20;
456	num_gs_threads = 20;	456	num_gs_threads = 20;
457	num_es_threads = 20;	457	num_es_threads = 20;
458	num_hs_threads = 20;	458	num_hs_threads = 20;
459	num_ls_threads = 20;	459	num_ls_threads = 20;
460	num_ps_stack_entries = 85;	460	num_ps_stack_entries = 85;
461	num_vs_stack_entries = 85;	461	num_vs_stack_entries = 85;
462	num_gs_stack_entries = 85;	462	num_gs_stack_entries = 85;
463	num_es_stack_entries = 85;	463	num_es_stack_entries = 85;
464	num_hs_stack_entries = 85;	464	num_hs_stack_entries = 85;
465	num_ls_stack_entries = 85;	465	num_ls_stack_entries = 85;
466	break;	466	break;
467	case CHIP_TURKS:	467	case CHIP_TURKS:
468	num_ps_gprs = 93;	468	num_ps_gprs = 93;
469	num_vs_gprs = 46;	469	num_vs_gprs = 46;
470	num_temp_gprs = 4;	470	num_temp_gprs = 4;
471	num_gs_gprs = 31;	471	num_gs_gprs = 31;
472	num_es_gprs = 31;	472	num_es_gprs = 31;
473	num_hs_gprs = 23;	473	num_hs_gprs = 23;
474	num_ls_gprs = 23;	474	num_ls_gprs = 23;
475	num_ps_threads = 128;	475	num_ps_threads = 128;
476	num_vs_threads = 20;	476	num_vs_threads = 20;
477	num_gs_threads = 20;	477	num_gs_threads = 20;
478	num_es_threads = 20;	478	num_es_threads = 20;
479	num_hs_threads = 20;	479	num_hs_threads = 20;
480	num_ls_threads = 20;	480	num_ls_threads = 20;
481	num_ps_stack_entries = 42;	481	num_ps_stack_entries = 42;
482	num_vs_stack_entries = 42;	482	num_vs_stack_entries = 42;
483	num_gs_stack_entries = 42;	483	num_gs_stack_entries = 42;
484	num_es_stack_entries = 42;	484	num_es_stack_entries = 42;
485	num_hs_stack_entries = 42;	485	num_hs_stack_entries = 42;
486	num_ls_stack_entries = 42;	486	num_ls_stack_entries = 42;
487	break;	487	break;
488	case CHIP_CAICOS:	488	case CHIP_CAICOS:
489	num_ps_gprs = 93;	489	num_ps_gprs = 93;
490	num_vs_gprs = 46;	490	num_vs_gprs = 46;
491	num_temp_gprs = 4;	491	num_temp_gprs = 4;
492	num_gs_gprs = 31;	492	num_gs_gprs = 31;
493	num_es_gprs = 31;	493	num_es_gprs = 31;
494	num_hs_gprs = 23;	494	num_hs_gprs = 23;
495	num_ls_gprs = 23;	495	num_ls_gprs = 23;
496	num_ps_threads = 128;	496	num_ps_threads = 128;
497	num_vs_threads = 10;	497	num_vs_threads = 10;
498	num_gs_threads = 10;	498	num_gs_threads = 10;
499	num_es_threads = 10;	499	num_es_threads = 10;
500	num_hs_threads = 10;	500	num_hs_threads = 10;

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(root)/drivers/video/drm/radeon/evergreen_blit_kms.c – Rev 2997 → 3192