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| Rev 5271 | Rev 6104 | ||
|---|---|---|---|
| Line 24... | Line 24... | ||
| 24 | #include |
24 | #include |
| 25 | #include |
25 | #include |
| 26 | #include |
26 | #include |
| 27 | #include "radeon.h" |
27 | #include "radeon.h" |
| 28 | #include "radeon_asic.h" |
28 | #include "radeon_asic.h" |
| - | 29 | #include "radeon_audio.h" |
|
| 29 | #include |
30 | #include |
| 30 | #include "evergreend.h" |
31 | #include "evergreend.h" |
| 31 | #include "atom.h" |
32 | #include "atom.h" |
| 32 | #include "avivod.h" |
33 | #include "avivod.h" |
| 33 | #include "evergreen_reg.h" |
34 | #include "evergreen_reg.h" |
| 34 | #include "evergreen_blit_shaders.h" |
35 | #include "evergreen_blit_shaders.h" |
| 35 | #include "radeon_ucode.h" |
36 | #include "radeon_ucode.h" |
| Line -... | Line 37... | ||
| - | 37 | ||
| - | 38 | /* |
|
| - | 39 | * Indirect registers accessor |
|
| - | 40 | */ |
|
| - | 41 | u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) |
|
| - | 42 | { |
|
| - | 43 | unsigned long flags; |
|
| - | 44 | u32 r; |
|
| - | 45 | ||
| - | 46 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
|
| - | 47 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
|
| - | 48 | r = RREG32(EVERGREEN_CG_IND_DATA); |
|
| - | 49 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
|
| - | 50 | return r; |
|
| - | 51 | } |
|
| - | 52 | ||
| - | 53 | void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
|
| - | 54 | { |
|
| - | 55 | unsigned long flags; |
|
| - | 56 | ||
| - | 57 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
|
| - | 58 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
|
| - | 59 | WREG32(EVERGREEN_CG_IND_DATA, (v)); |
|
| - | 60 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
|
| - | 61 | } |
|
| - | 62 | ||
| - | 63 | u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) |
|
| - | 64 | { |
|
| - | 65 | unsigned long flags; |
|
| - | 66 | u32 r; |
|
| - | 67 | ||
| - | 68 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
|
| - | 69 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
|
| - | 70 | r = RREG32(EVERGREEN_PIF_PHY0_DATA); |
|
| - | 71 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
|
| - | 72 | return r; |
|
| - | 73 | } |
|
| - | 74 | ||
| - | 75 | void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
|
| - | 76 | { |
|
| - | 77 | unsigned long flags; |
|
| - | 78 | ||
| - | 79 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
|
| - | 80 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
|
| - | 81 | WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); |
|
| - | 82 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
|
| - | 83 | } |
|
| - | 84 | ||
| - | 85 | u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) |
|
| - | 86 | { |
|
| - | 87 | unsigned long flags; |
|
| - | 88 | u32 r; |
|
| - | 89 | ||
| - | 90 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
|
| - | 91 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
|
| - | 92 | r = RREG32(EVERGREEN_PIF_PHY1_DATA); |
|
| - | 93 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
|
| - | 94 | return r; |
|
| - | 95 | } |
|
| - | 96 | ||
| - | 97 | void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
|
| - | 98 | { |
|
| - | 99 | unsigned long flags; |
|
| - | 100 | ||
| - | 101 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
|
| - | 102 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
|
| - | 103 | WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); |
|
| - | 104 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
|
| - | 105 | } |
|
| 36 | 106 | ||
| 37 | static const u32 crtc_offsets[6] = |
107 | static const u32 crtc_offsets[6] = |
| 38 | { |
108 | { |
| 39 | EVERGREEN_CRTC0_REGISTER_OFFSET, |
109 | EVERGREEN_CRTC0_REGISTER_OFFSET, |
| 40 | EVERGREEN_CRTC1_REGISTER_OFFSET, |
110 | EVERGREEN_CRTC1_REGISTER_OFFSET, |
| Line 1003... | Line 1073... | ||
| 1003 | default: |
1073 | default: |
| 1004 | break; |
1074 | break; |
| 1005 | } |
1075 | } |
| 1006 | } |
1076 | } |
| Line -... | Line 1077... | ||
| - | 1077 | ||
| - | 1078 | /** |
|
| - | 1079 | * evergreen_get_allowed_info_register - fetch the register for the info ioctl |
|
| - | 1080 | * |
|
| - | 1081 | * @rdev: radeon_device pointer |
|
| - | 1082 | * @reg: register offset in bytes |
|
| - | 1083 | * @val: register value |
|
| - | 1084 | * |
|
| - | 1085 | * Returns 0 for success or -EINVAL for an invalid register |
|
| - | 1086 | * |
|
| - | 1087 | */ |
|
| - | 1088 | int evergreen_get_allowed_info_register(struct radeon_device *rdev, |
|
| - | 1089 | u32 reg, u32 *val) |
|
| - | 1090 | { |
|
| - | 1091 | switch (reg) { |
|
| - | 1092 | case GRBM_STATUS: |
|
| - | 1093 | case GRBM_STATUS_SE0: |
|
| - | 1094 | case GRBM_STATUS_SE1: |
|
| - | 1095 | case SRBM_STATUS: |
|
| - | 1096 | case SRBM_STATUS2: |
|
| - | 1097 | case DMA_STATUS_REG: |
|
| - | 1098 | case UVD_STATUS: |
|
| - | 1099 | *val = RREG32(reg); |
|
| - | 1100 | return 0; |
|
| - | 1101 | default: |
|
| - | 1102 | return -EINVAL; |
|
| - | 1103 | } |
|
| - | 1104 | } |
|
| 1007 | 1105 | ||
| 1008 | void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
1106 | void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
| 1009 | unsigned *bankh, unsigned *mtaspect, |
1107 | unsigned *bankh, unsigned *mtaspect, |
| 1010 | unsigned *tile_split) |
1108 | unsigned *tile_split) |
| 1011 | { |
1109 | { |
| Line 1101... | Line 1199... | ||
| 1101 | /* keep the Bypass mode, put PLL to sleep */ |
1199 | /* keep the Bypass mode, put PLL to sleep */ |
| 1102 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); |
1200 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); |
| 1103 | return 0; |
1201 | return 0; |
| 1104 | } |
1202 | } |
| Line 1105... | Line 1203... | ||
| 1105 | 1203 | ||
| 1106 | // r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000, |
1204 | r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000, |
| 1107 | // 16384, 0x03FFFFFF, 0, 128, 5, |
1205 | 16384, 0x03FFFFFF, 0, 128, 5, |
| 1108 | // &fb_div, &vclk_div, &dclk_div); |
1206 | &fb_div, &vclk_div, &dclk_div); |
| 1109 | if (r) |
1207 | if (r) |
| Line 1110... | Line 1208... | ||
| 1110 | return r; |
1208 | return r; |
| 1111 | 1209 | ||
| Line 1119... | Line 1217... | ||
| 1119 | /* deassert UPLL_RESET */ |
1217 | /* deassert UPLL_RESET */ |
| 1120 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); |
1218 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); |
| Line 1121... | Line 1219... | ||
| 1121 | 1219 | ||
| Line 1122... | Line 1220... | ||
| 1122 | mdelay(1); |
1220 | mdelay(1); |
| 1123 | 1221 | ||
| 1124 | // r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
1222 | r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
| Line 1125... | Line 1223... | ||
| 1125 | // if (r) |
1223 | if (r) |
| 1126 | // return r; |
1224 | return r; |
| Line 1127... | Line 1225... | ||
| 1127 | 1225 | ||
| Line 1156... | Line 1254... | ||
| 1156 | mdelay(15); |
1254 | mdelay(15); |
| Line 1157... | Line 1255... | ||
| 1157 | 1255 | ||
| 1158 | /* switch from bypass mode to normal mode */ |
1256 | /* switch from bypass mode to normal mode */ |
| Line 1159... | Line 1257... | ||
| 1159 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); |
1257 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); |
| 1160 | 1258 | ||
| 1161 | // r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
1259 | r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
| Line 1162... | Line 1260... | ||
| 1162 | // if (r) |
1260 | if (r) |
| 1163 | // return r; |
1261 | return r; |
| 1164 | 1262 | ||
| 1165 | /* switch VCLK and DCLK selection */ |
1263 | /* switch VCLK and DCLK selection */ |
| Line 1304... | Line 1402... | ||
| 1304 | * |
1402 | * |
| 1305 | * @rdev: radeon_device pointer |
1403 | * @rdev: radeon_device pointer |
| 1306 | * @crtc_id: crtc to cleanup pageflip on |
1404 | * @crtc_id: crtc to cleanup pageflip on |
| 1307 | * @crtc_base: new address of the crtc (GPU MC address) |
1405 | * @crtc_base: new address of the crtc (GPU MC address) |
| 1308 | * |
1406 | * |
| 1309 | * Does the actual pageflip (evergreen+). |
1407 | * Triggers the actual pageflip by updating the primary |
| 1310 | * During vblank we take the crtc lock and wait for the update_pending |
- | |
| 1311 | * bit to go high, when it does, we release the lock, and allow the |
- | |
| 1312 | * double buffered update to take place. |
1408 | * surface base address (evergreen+). |
| 1313 | * Returns the current update pending status. |
- | |
| 1314 | */ |
1409 | */ |
| 1315 | void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
1410 | void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
| 1316 | { |
1411 | { |
| 1317 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
1412 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
| 1318 | u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); |
- | |
| 1319 | int i; |
- | |
| 1320 | - | ||
| 1321 | /* Lock the graphics update lock */ |
- | |
| 1322 | tmp |= EVERGREEN_GRPH_UPDATE_LOCK; |
- | |
| 1323 | WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
- | |
| Line 1324... | Line 1413... | ||
| 1324 | 1413 | ||
| 1325 | /* update the scanout addresses */ |
- | |
| 1326 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
- | |
| 1327 | upper_32_bits(crtc_base)); |
- | |
| 1328 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
- | |
| 1329 | (u32)crtc_base); |
- | |
| 1330 | 1414 | /* update the scanout addresses */ |
|
| 1331 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
1415 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
| 1332 | upper_32_bits(crtc_base)); |
1416 | upper_32_bits(crtc_base)); |
| 1333 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1417 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 1334 | (u32)crtc_base); |
- | |
| 1335 | 1418 | (u32)crtc_base); |
|
| 1336 | /* Wait for update_pending to go high. */ |
- | |
| 1337 | for (i = 0; i < rdev->usec_timeout; i++) { |
- | |
| 1338 | if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) |
- | |
| 1339 | break; |
- | |
| 1340 | udelay(1); |
- | |
| 1341 | } |
- | |
| 1342 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
- | |
| 1343 | - | ||
| 1344 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
- | |
| 1345 | tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; |
1419 | /* post the write */ |
| 1346 | WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
1420 | RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset); |
| Line 1347... | Line 1421... | ||
| 1347 | } |
1421 | } |
| 1348 | 1422 | ||
| 1349 | /** |
1423 | /** |
| Line 2296... | Line 2370... | ||
| 2296 | c.full = dfixed_div(c, a); |
2370 | c.full = dfixed_div(c, a); |
| 2297 | a.full = dfixed_const(16); |
2371 | a.full = dfixed_const(16); |
| 2298 | c.full = dfixed_div(c, a); |
2372 | c.full = dfixed_div(c, a); |
| 2299 | priority_b_mark = dfixed_trunc(c); |
2373 | priority_b_mark = dfixed_trunc(c); |
| 2300 | priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; |
2374 | priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; |
| - | 2375 | ||
| - | 2376 | /* Save number of lines the linebuffer leads before the scanout */ |
|
| - | 2377 | radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); |
|
| 2301 | } |
2378 | } |
| Line 2302... | Line 2379... | ||
| 2302 | 2379 | ||
| 2303 | /* select wm A */ |
2380 | /* select wm A */ |
| 2304 | arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); |
2381 | arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); |
| Line 3250... | Line 3327... | ||
| 3250 | WREG32((0x2c20 + j), 0x00000000); |
3327 | WREG32((0x2c20 + j), 0x00000000); |
| 3251 | WREG32((0x2c24 + j), 0x00000000); |
3328 | WREG32((0x2c24 + j), 0x00000000); |
| 3252 | } |
3329 | } |
| Line 3253... | Line 3330... | ||
| 3253 | 3330 | ||
| - | 3331 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
|
| - | 3332 | WREG32(SRBM_INT_CNTL, 0x1); |
|
| Line 3254... | Line 3333... | ||
| 3254 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
3333 | WREG32(SRBM_INT_ACK, 0x1); |
| Line 3255... | Line 3334... | ||
| 3255 | 3334 | ||
| 3256 | evergreen_fix_pci_max_read_req_size(rdev); |
3335 | evergreen_fix_pci_max_read_req_size(rdev); |
| Line 4321... | Line 4400... | ||
| 4321 | } else |
4400 | } else |
| 4322 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
4401 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
| 4323 | tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
4402 | tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
| 4324 | WREG32(DMA_CNTL, tmp); |
4403 | WREG32(DMA_CNTL, tmp); |
| 4325 | WREG32(GRBM_INT_CNTL, 0); |
4404 | WREG32(GRBM_INT_CNTL, 0); |
| - | 4405 | WREG32(SRBM_INT_CNTL, 0); |
|
| 4326 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
4406 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
| 4327 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
4407 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
| 4328 | if (rdev->num_crtc >= 4) { |
4408 | if (rdev->num_crtc >= 4) { |
| 4329 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
4409 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
| 4330 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
4410 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
| Line 4386... | Line 4466... | ||
| 4386 | /* force the active interrupt state to all disabled */ |
4466 | /* force the active interrupt state to all disabled */ |
| 4387 | evergreen_disable_interrupt_state(rdev); |
4467 | evergreen_disable_interrupt_state(rdev); |
| 4388 | return 0; |
4468 | return 0; |
| 4389 | } |
4469 | } |
| Line 4390... | Line 4470... | ||
| 4390 | 4470 | ||
| 4391 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4471 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 4392 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4472 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 4393 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4473 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 4394 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4474 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 4395 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4475 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 4396 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4476 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 4397 | if (rdev->family == CHIP_ARUBA) |
4477 | if (rdev->family == CHIP_ARUBA) |
| 4398 | thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) & |
4478 | thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) & |
| 4399 | ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); |
4479 | ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); |
| 4400 | else |
4480 | else |
| Line 4480... | Line 4560... | ||
| 4480 | DRM_DEBUG("evergreen_irq_set: vblank 5\n"); |
4560 | DRM_DEBUG("evergreen_irq_set: vblank 5\n"); |
| 4481 | crtc6 |= VBLANK_INT_MASK; |
4561 | crtc6 |= VBLANK_INT_MASK; |
| 4482 | } |
4562 | } |
| 4483 | if (rdev->irq.hpd[0]) { |
4563 | if (rdev->irq.hpd[0]) { |
| 4484 | DRM_DEBUG("evergreen_irq_set: hpd 1\n"); |
4564 | DRM_DEBUG("evergreen_irq_set: hpd 1\n"); |
| 4485 | hpd1 |= DC_HPDx_INT_EN; |
4565 | hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 4486 | } |
4566 | } |
| 4487 | if (rdev->irq.hpd[1]) { |
4567 | if (rdev->irq.hpd[1]) { |
| 4488 | DRM_DEBUG("evergreen_irq_set: hpd 2\n"); |
4568 | DRM_DEBUG("evergreen_irq_set: hpd 2\n"); |
| 4489 | hpd2 |= DC_HPDx_INT_EN; |
4569 | hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 4490 | } |
4570 | } |
| 4491 | if (rdev->irq.hpd[2]) { |
4571 | if (rdev->irq.hpd[2]) { |
| 4492 | DRM_DEBUG("evergreen_irq_set: hpd 3\n"); |
4572 | DRM_DEBUG("evergreen_irq_set: hpd 3\n"); |
| 4493 | hpd3 |= DC_HPDx_INT_EN; |
4573 | hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 4494 | } |
4574 | } |
| 4495 | if (rdev->irq.hpd[3]) { |
4575 | if (rdev->irq.hpd[3]) { |
| 4496 | DRM_DEBUG("evergreen_irq_set: hpd 4\n"); |
4576 | DRM_DEBUG("evergreen_irq_set: hpd 4\n"); |
| 4497 | hpd4 |= DC_HPDx_INT_EN; |
4577 | hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 4498 | } |
4578 | } |
| 4499 | if (rdev->irq.hpd[4]) { |
4579 | if (rdev->irq.hpd[4]) { |
| 4500 | DRM_DEBUG("evergreen_irq_set: hpd 5\n"); |
4580 | DRM_DEBUG("evergreen_irq_set: hpd 5\n"); |
| 4501 | hpd5 |= DC_HPDx_INT_EN; |
4581 | hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 4502 | } |
4582 | } |
| 4503 | if (rdev->irq.hpd[5]) { |
4583 | if (rdev->irq.hpd[5]) { |
| 4504 | DRM_DEBUG("evergreen_irq_set: hpd 6\n"); |
4584 | DRM_DEBUG("evergreen_irq_set: hpd 6\n"); |
| 4505 | hpd6 |= DC_HPDx_INT_EN; |
4585 | hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 4506 | } |
4586 | } |
| 4507 | if (rdev->irq.afmt[0]) { |
4587 | if (rdev->irq.afmt[0]) { |
| 4508 | DRM_DEBUG("evergreen_irq_set: hdmi 0\n"); |
4588 | DRM_DEBUG("evergreen_irq_set: hdmi 0\n"); |
| 4509 | afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK; |
4589 | afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK; |
| 4510 | } |
4590 | } |
| Line 4587... | Line 4667... | ||
| 4587 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); |
4667 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); |
| 4588 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4); |
4668 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4); |
| 4589 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); |
4669 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); |
| 4590 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); |
4670 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); |
| Line -... | Line 4671... | ||
| - | 4671 | ||
| - | 4672 | /* posting read */ |
|
| - | 4673 | RREG32(SRBM_STATUS); |
|
| 4591 | 4674 | ||
| 4592 | return 0; |
4675 | return 0; |
| Line 4593... | Line 4676... | ||
| 4593 | } |
4676 | } |
| 4594 | 4677 | ||
| Line 4691... | Line 4774... | ||
| 4691 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
4774 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
| 4692 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
4775 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
| 4693 | tmp |= DC_HPDx_INT_ACK; |
4776 | tmp |= DC_HPDx_INT_ACK; |
| 4694 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
4777 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
| 4695 | } |
4778 | } |
| - | 4779 | ||
| - | 4780 | if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { |
|
| - | 4781 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
|
| - | 4782 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 4783 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
|
| - | 4784 | } |
|
| - | 4785 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { |
|
| - | 4786 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
|
| - | 4787 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 4788 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
|
| - | 4789 | } |
|
| - | 4790 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { |
|
| - | 4791 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
|
| - | 4792 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 4793 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
|
| - | 4794 | } |
|
| - | 4795 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { |
|
| - | 4796 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
|
| - | 4797 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 4798 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
|
| - | 4799 | } |
|
| - | 4800 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { |
|
| - | 4801 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
|
| - | 4802 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 4803 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
|
| - | 4804 | } |
|
| - | 4805 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { |
|
| - | 4806 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
|
| - | 4807 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 4808 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
|
| - | 4809 | } |
|
| - | 4810 | ||
| 4696 | if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { |
4811 | if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { |
| 4697 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); |
4812 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); |
| 4698 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
4813 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
| 4699 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); |
4814 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); |
| 4700 | } |
4815 | } |
| Line 4771... | Line 4886... | ||
| 4771 | u32 rptr; |
4886 | u32 rptr; |
| 4772 | u32 src_id, src_data; |
4887 | u32 src_id, src_data; |
| 4773 | u32 ring_index; |
4888 | u32 ring_index; |
| 4774 | bool queue_hotplug = false; |
4889 | bool queue_hotplug = false; |
| 4775 | bool queue_hdmi = false; |
4890 | bool queue_hdmi = false; |
| - | 4891 | bool queue_dp = false; |
|
| 4776 | bool queue_thermal = false; |
4892 | bool queue_thermal = false; |
| 4777 | u32 status, addr; |
4893 | u32 status, addr; |
| Line 4778... | Line 4894... | ||
| 4778 | 4894 | ||
| 4779 | if (!rdev->ih.enabled || rdev->shutdown) |
4895 | if (!rdev->ih.enabled || rdev->shutdown) |
| Line 4785... | Line 4901... | ||
| 4785 | /* is somebody else already processing irqs? */ |
4901 | /* is somebody else already processing irqs? */ |
| 4786 | if (atomic_xchg(&rdev->ih.lock, 1)) |
4902 | if (atomic_xchg(&rdev->ih.lock, 1)) |
| 4787 | return IRQ_NONE; |
4903 | return IRQ_NONE; |
| Line 4788... | Line 4904... | ||
| 4788 | 4904 | ||
| 4789 | rptr = rdev->ih.rptr; |
4905 | rptr = rdev->ih.rptr; |
| Line 4790... | Line 4906... | ||
| 4790 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
4906 | DRM_DEBUG("evergreen_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
| 4791 | 4907 | ||
| Line 4792... | Line 4908... | ||
| 4792 | /* Order reading of wptr vs. reading of IH ring data */ |
4908 | /* Order reading of wptr vs. reading of IH ring data */ |
| Line 4803... | Line 4919... | ||
| 4803 | 4919 | ||
| 4804 | switch (src_id) { |
4920 | switch (src_id) { |
| 4805 | case 1: /* D1 vblank/vline */ |
4921 | case 1: /* D1 vblank/vline */ |
| 4806 | switch (src_data) { |
4922 | switch (src_data) { |
| 4807 | case 0: /* D1 vblank */ |
4923 | case 0: /* D1 vblank */ |
| - | 4924 | if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)) |
|
| - | 4925 | DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); |
|
| 4808 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { |
4926 | |
| 4809 | if (rdev->irq.crtc_vblank_int[0]) { |
4927 | if (rdev->irq.crtc_vblank_int[0]) { |
| 4810 | // drm_handle_vblank(rdev->ddev, 0); |
4928 | drm_handle_vblank(rdev->ddev, 0); |
| 4811 | rdev->pm.vblank_sync = true; |
4929 | rdev->pm.vblank_sync = true; |
| 4812 | // wake_up(&rdev->irq.vblank_queue); |
4930 | wake_up(&rdev->irq.vblank_queue); |
| 4813 | } |
4931 | } |
| 4814 | // if (rdev->irq.pflip[0]) |
4932 | if (atomic_read(&rdev->irq.pflip[0])) |
| 4815 | // radeon_crtc_handle_flip(rdev, 0); |
4933 | radeon_crtc_handle_vblank(rdev, 0); |
| 4816 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
4934 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
| 4817 | DRM_DEBUG("IH: D1 vblank\n"); |
4935 | DRM_DEBUG("IH: D1 vblank\n"); |
| 4818 | } |
4936 | |
| 4819 | break; |
4937 | break; |
| 4820 | case 1: /* D1 vline */ |
4938 | case 1: /* D1 vline */ |
| - | 4939 | if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)) |
|
| - | 4940 | DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); |
|
| 4821 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { |
4941 | |
| 4822 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; |
4942 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; |
| 4823 | DRM_DEBUG("IH: D1 vline\n"); |
4943 | DRM_DEBUG("IH: D1 vline\n"); |
| 4824 | } |
4944 | |
| 4825 | break; |
4945 | break; |
| 4826 | default: |
4946 | default: |
| 4827 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
4947 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 4828 | break; |
4948 | break; |
| 4829 | } |
4949 | } |
| 4830 | break; |
4950 | break; |
| 4831 | case 2: /* D2 vblank/vline */ |
4951 | case 2: /* D2 vblank/vline */ |
| 4832 | switch (src_data) { |
4952 | switch (src_data) { |
| 4833 | case 0: /* D2 vblank */ |
4953 | case 0: /* D2 vblank */ |
| - | 4954 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) |
|
| - | 4955 | DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); |
|
| 4834 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { |
4956 | |
| 4835 | if (rdev->irq.crtc_vblank_int[1]) { |
4957 | if (rdev->irq.crtc_vblank_int[1]) { |
| 4836 | // drm_handle_vblank(rdev->ddev, 1); |
4958 | drm_handle_vblank(rdev->ddev, 1); |
| 4837 | rdev->pm.vblank_sync = true; |
4959 | rdev->pm.vblank_sync = true; |
| 4838 | // wake_up(&rdev->irq.vblank_queue); |
4960 | wake_up(&rdev->irq.vblank_queue); |
| 4839 | } |
4961 | } |
| 4840 | // if (rdev->irq.pflip[1]) |
4962 | if (atomic_read(&rdev->irq.pflip[1])) |
| 4841 | // radeon_crtc_handle_flip(rdev, 1); |
4963 | radeon_crtc_handle_vblank(rdev, 1); |
| 4842 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; |
4964 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; |
| 4843 | DRM_DEBUG("IH: D2 vblank\n"); |
4965 | DRM_DEBUG("IH: D2 vblank\n"); |
| 4844 | } |
4966 | |
| 4845 | break; |
4967 | break; |
| 4846 | case 1: /* D2 vline */ |
4968 | case 1: /* D2 vline */ |
| - | 4969 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)) |
|
| - | 4970 | DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); |
|
| 4847 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { |
4971 | |
| 4848 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; |
4972 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; |
| 4849 | DRM_DEBUG("IH: D2 vline\n"); |
4973 | DRM_DEBUG("IH: D2 vline\n"); |
| 4850 | } |
4974 | |
| 4851 | break; |
4975 | break; |
| 4852 | default: |
4976 | default: |
| 4853 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
4977 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 4854 | break; |
4978 | break; |
| 4855 | } |
4979 | } |
| 4856 | break; |
4980 | break; |
| 4857 | case 3: /* D3 vblank/vline */ |
4981 | case 3: /* D3 vblank/vline */ |
| 4858 | switch (src_data) { |
4982 | switch (src_data) { |
| 4859 | case 0: /* D3 vblank */ |
4983 | case 0: /* D3 vblank */ |
| - | 4984 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) |
|
| - | 4985 | DRM_DEBUG("IH: D3 vblank - IH event w/o asserted irq bit?\n"); |
|
| 4860 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { |
4986 | |
| 4861 | if (rdev->irq.crtc_vblank_int[2]) { |
4987 | if (rdev->irq.crtc_vblank_int[2]) { |
| 4862 | // drm_handle_vblank(rdev->ddev, 2); |
4988 | drm_handle_vblank(rdev->ddev, 2); |
| 4863 | rdev->pm.vblank_sync = true; |
4989 | rdev->pm.vblank_sync = true; |
| 4864 | // wake_up(&rdev->irq.vblank_queue); |
4990 | wake_up(&rdev->irq.vblank_queue); |
| 4865 | } |
4991 | } |
| 4866 | // if (rdev->irq.pflip[2]) |
4992 | if (atomic_read(&rdev->irq.pflip[2])) |
| 4867 | // radeon_crtc_handle_flip(rdev, 2); |
4993 | radeon_crtc_handle_vblank(rdev, 2); |
| 4868 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; |
4994 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; |
| 4869 | DRM_DEBUG("IH: D3 vblank\n"); |
4995 | DRM_DEBUG("IH: D3 vblank\n"); |
| 4870 | } |
4996 | |
| 4871 | break; |
4997 | break; |
| 4872 | case 1: /* D3 vline */ |
4998 | case 1: /* D3 vline */ |
| - | 4999 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) |
|
| - | 5000 | DRM_DEBUG("IH: D3 vline - IH event w/o asserted irq bit?\n"); |
|
| 4873 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { |
5001 | |
| 4874 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; |
5002 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; |
| 4875 | DRM_DEBUG("IH: D3 vline\n"); |
5003 | DRM_DEBUG("IH: D3 vline\n"); |
| 4876 | } |
5004 | |
| 4877 | break; |
5005 | break; |
| 4878 | default: |
5006 | default: |
| 4879 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
5007 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 4880 | break; |
5008 | break; |
| 4881 | } |
5009 | } |
| 4882 | break; |
5010 | break; |
| 4883 | case 4: /* D4 vblank/vline */ |
5011 | case 4: /* D4 vblank/vline */ |
| 4884 | switch (src_data) { |
5012 | switch (src_data) { |
| 4885 | case 0: /* D4 vblank */ |
5013 | case 0: /* D4 vblank */ |
| - | 5014 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) |
|
| - | 5015 | DRM_DEBUG("IH: D4 vblank - IH event w/o asserted irq bit?\n"); |
|
| 4886 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { |
5016 | |
| 4887 | if (rdev->irq.crtc_vblank_int[3]) { |
5017 | if (rdev->irq.crtc_vblank_int[3]) { |
| 4888 | // drm_handle_vblank(rdev->ddev, 3); |
5018 | drm_handle_vblank(rdev->ddev, 3); |
| 4889 | rdev->pm.vblank_sync = true; |
5019 | rdev->pm.vblank_sync = true; |
| 4890 | // wake_up(&rdev->irq.vblank_queue); |
5020 | wake_up(&rdev->irq.vblank_queue); |
| 4891 | } |
5021 | } |
| 4892 | // if (rdev->irq.pflip[3]) |
5022 | if (atomic_read(&rdev->irq.pflip[3])) |
| 4893 | // radeon_crtc_handle_flip(rdev, 3); |
5023 | radeon_crtc_handle_vblank(rdev, 3); |
| 4894 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; |
5024 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; |
| 4895 | DRM_DEBUG("IH: D4 vblank\n"); |
5025 | DRM_DEBUG("IH: D4 vblank\n"); |
| 4896 | } |
5026 | |
| 4897 | break; |
5027 | break; |
| 4898 | case 1: /* D4 vline */ |
5028 | case 1: /* D4 vline */ |
| - | 5029 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) |
|
| - | 5030 | DRM_DEBUG("IH: D4 vline - IH event w/o asserted irq bit?\n"); |
|
| 4899 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { |
5031 | |
| 4900 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; |
5032 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; |
| 4901 | DRM_DEBUG("IH: D4 vline\n"); |
5033 | DRM_DEBUG("IH: D4 vline\n"); |
| 4902 | } |
5034 | |
| 4903 | break; |
5035 | break; |
| 4904 | default: |
5036 | default: |
| 4905 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
5037 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 4906 | break; |
5038 | break; |
| 4907 | } |
5039 | } |
| 4908 | break; |
5040 | break; |
| 4909 | case 5: /* D5 vblank/vline */ |
5041 | case 5: /* D5 vblank/vline */ |
| 4910 | switch (src_data) { |
5042 | switch (src_data) { |
| 4911 | case 0: /* D5 vblank */ |
5043 | case 0: /* D5 vblank */ |
| - | 5044 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) |
|
| - | 5045 | DRM_DEBUG("IH: D5 vblank - IH event w/o asserted irq bit?\n"); |
|
| 4912 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { |
5046 | |
| 4913 | if (rdev->irq.crtc_vblank_int[4]) { |
5047 | if (rdev->irq.crtc_vblank_int[4]) { |
| 4914 | // drm_handle_vblank(rdev->ddev, 4); |
5048 | drm_handle_vblank(rdev->ddev, 4); |
| 4915 | rdev->pm.vblank_sync = true; |
5049 | rdev->pm.vblank_sync = true; |
| 4916 | // wake_up(&rdev->irq.vblank_queue); |
5050 | wake_up(&rdev->irq.vblank_queue); |
| 4917 | } |
5051 | } |
| 4918 | // if (rdev->irq.pflip[4]) |
5052 | if (atomic_read(&rdev->irq.pflip[4])) |
| 4919 | // radeon_crtc_handle_flip(rdev, 4); |
5053 | radeon_crtc_handle_vblank(rdev, 4); |
| 4920 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; |
5054 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; |
| 4921 | DRM_DEBUG("IH: D5 vblank\n"); |
5055 | DRM_DEBUG("IH: D5 vblank\n"); |
| 4922 | } |
5056 | |
| 4923 | break; |
5057 | break; |
| 4924 | case 1: /* D5 vline */ |
5058 | case 1: /* D5 vline */ |
| - | 5059 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) |
|
| - | 5060 | DRM_DEBUG("IH: D5 vline - IH event w/o asserted irq bit?\n"); |
|
| 4925 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { |
5061 | |
| 4926 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; |
5062 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; |
| 4927 | DRM_DEBUG("IH: D5 vline\n"); |
5063 | DRM_DEBUG("IH: D5 vline\n"); |
| 4928 | } |
5064 | |
| 4929 | break; |
5065 | break; |
| 4930 | default: |
5066 | default: |
| 4931 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
5067 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 4932 | break; |
5068 | break; |
| 4933 | } |
5069 | } |
| 4934 | break; |
5070 | break; |
| 4935 | case 6: /* D6 vblank/vline */ |
5071 | case 6: /* D6 vblank/vline */ |
| 4936 | switch (src_data) { |
5072 | switch (src_data) { |
| 4937 | case 0: /* D6 vblank */ |
5073 | case 0: /* D6 vblank */ |
| - | 5074 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) |
|
| - | 5075 | DRM_DEBUG("IH: D6 vblank - IH event w/o asserted irq bit?\n"); |
|
| 4938 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { |
5076 | |
| 4939 | if (rdev->irq.crtc_vblank_int[5]) { |
5077 | if (rdev->irq.crtc_vblank_int[5]) { |
| 4940 | // drm_handle_vblank(rdev->ddev, 5); |
5078 | drm_handle_vblank(rdev->ddev, 5); |
| 4941 | rdev->pm.vblank_sync = true; |
5079 | rdev->pm.vblank_sync = true; |
| 4942 | // wake_up(&rdev->irq.vblank_queue); |
5080 | wake_up(&rdev->irq.vblank_queue); |
| 4943 | } |
5081 | } |
| 4944 | // if (rdev->irq.pflip[5]) |
5082 | if (atomic_read(&rdev->irq.pflip[5])) |
| 4945 | // radeon_crtc_handle_flip(rdev, 5); |
5083 | radeon_crtc_handle_vblank(rdev, 5); |
| 4946 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; |
5084 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; |
| 4947 | DRM_DEBUG("IH: D6 vblank\n"); |
5085 | DRM_DEBUG("IH: D6 vblank\n"); |
| 4948 | } |
5086 | |
| 4949 | break; |
5087 | break; |
| 4950 | case 1: /* D6 vline */ |
5088 | case 1: /* D6 vline */ |
| - | 5089 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) |
|
| - | 5090 | DRM_DEBUG("IH: D6 vline - IH event w/o asserted irq bit?\n"); |
|
| 4951 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { |
5091 | |
| 4952 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; |
5092 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; |
| 4953 | DRM_DEBUG("IH: D6 vline\n"); |
5093 | DRM_DEBUG("IH: D6 vline\n"); |
| 4954 | } |
5094 | |
| 4955 | break; |
5095 | break; |
| 4956 | default: |
5096 | default: |
| 4957 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
5097 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 4958 | break; |
5098 | break; |
| Line 4967... | Line 5107... | ||
| 4967 | DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); |
5107 | DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); |
| 4968 | break; |
5108 | break; |
| 4969 | case 42: /* HPD hotplug */ |
5109 | case 42: /* HPD hotplug */ |
| 4970 | switch (src_data) { |
5110 | switch (src_data) { |
| 4971 | case 0: |
5111 | case 0: |
| 4972 | if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { |
5112 | if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT)) |
| - | 5113 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5114 | ||
| 4973 | rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; |
5115 | rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; |
| 4974 | queue_hotplug = true; |
5116 | queue_hotplug = true; |
| 4975 | DRM_DEBUG("IH: HPD1\n"); |
5117 | DRM_DEBUG("IH: HPD1\n"); |
| 4976 | } |
- | |
| 4977 | break; |
5118 | break; |
| 4978 | case 1: |
5119 | case 1: |
| 4979 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { |
5120 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT)) |
| - | 5121 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5122 | ||
| 4980 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; |
5123 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; |
| 4981 | queue_hotplug = true; |
5124 | queue_hotplug = true; |
| 4982 | DRM_DEBUG("IH: HPD2\n"); |
5125 | DRM_DEBUG("IH: HPD2\n"); |
| 4983 | } |
- | |
| 4984 | break; |
5126 | break; |
| 4985 | case 2: |
5127 | case 2: |
| 4986 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { |
5128 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT)) |
| - | 5129 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5130 | ||
| 4987 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; |
5131 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; |
| 4988 | queue_hotplug = true; |
5132 | queue_hotplug = true; |
| 4989 | DRM_DEBUG("IH: HPD3\n"); |
5133 | DRM_DEBUG("IH: HPD3\n"); |
| 4990 | } |
- | |
| 4991 | break; |
5134 | break; |
| 4992 | case 3: |
5135 | case 3: |
| 4993 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { |
5136 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT)) |
| - | 5137 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5138 | ||
| 4994 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; |
5139 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; |
| 4995 | queue_hotplug = true; |
5140 | queue_hotplug = true; |
| 4996 | DRM_DEBUG("IH: HPD4\n"); |
5141 | DRM_DEBUG("IH: HPD4\n"); |
| 4997 | } |
- | |
| 4998 | break; |
5142 | break; |
| 4999 | case 4: |
5143 | case 4: |
| 5000 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { |
5144 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT)) |
| - | 5145 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5146 | ||
| 5001 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; |
5147 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; |
| 5002 | queue_hotplug = true; |
5148 | queue_hotplug = true; |
| 5003 | DRM_DEBUG("IH: HPD5\n"); |
5149 | DRM_DEBUG("IH: HPD5\n"); |
| 5004 | } |
- | |
| 5005 | break; |
5150 | break; |
| 5006 | case 5: |
5151 | case 5: |
| 5007 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
5152 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT)) |
| - | 5153 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5154 | ||
| 5008 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; |
5155 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; |
| 5009 | queue_hotplug = true; |
5156 | queue_hotplug = true; |
| 5010 | DRM_DEBUG("IH: HPD6\n"); |
5157 | DRM_DEBUG("IH: HPD6\n"); |
| - | 5158 | break; |
|
| - | 5159 | case 6: |
|
| - | 5160 | if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT)) |
|
| - | 5161 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5162 | ||
| - | 5163 | rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; |
|
| - | 5164 | queue_dp = true; |
|
| - | 5165 | DRM_DEBUG("IH: HPD_RX 1\n"); |
|
| - | 5166 | break; |
|
| - | 5167 | case 7: |
|
| - | 5168 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT)) |
|
| - | 5169 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5170 | ||
| - | 5171 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; |
|
| - | 5172 | queue_dp = true; |
|
| - | 5173 | DRM_DEBUG("IH: HPD_RX 2\n"); |
|
| - | 5174 | break; |
|
| - | 5175 | case 8: |
|
| - | 5176 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) |
|
| - | 5177 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5178 | ||
| - | 5179 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; |
|
| - | 5180 | queue_dp = true; |
|
| - | 5181 | DRM_DEBUG("IH: HPD_RX 3\n"); |
|
| - | 5182 | break; |
|
| - | 5183 | case 9: |
|
| - | 5184 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) |
|
| - | 5185 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5186 | ||
| - | 5187 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; |
|
| - | 5188 | queue_dp = true; |
|
| - | 5189 | DRM_DEBUG("IH: HPD_RX 4\n"); |
|
| - | 5190 | break; |
|
| - | 5191 | case 10: |
|
| - | 5192 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) |
|
| - | 5193 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5194 | ||
| - | 5195 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; |
|
| - | 5196 | queue_dp = true; |
|
| - | 5197 | DRM_DEBUG("IH: HPD_RX 5\n"); |
|
| 5011 | } |
5198 | break; |
| - | 5199 | case 11: |
|
| - | 5200 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) |
|
| - | 5201 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5202 | ||
| - | 5203 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; |
|
| - | 5204 | queue_dp = true; |
|
| - | 5205 | DRM_DEBUG("IH: HPD_RX 6\n"); |
|
| 5012 | break; |
5206 | break; |
| 5013 | default: |
5207 | default: |
| 5014 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
5208 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 5015 | break; |
5209 | break; |
| 5016 | } |
5210 | } |
| 5017 | break; |
5211 | break; |
| 5018 | case 44: /* hdmi */ |
5212 | case 44: /* hdmi */ |
| 5019 | switch (src_data) { |
5213 | switch (src_data) { |
| 5020 | case 0: |
5214 | case 0: |
| 5021 | if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { |
5215 | if (!(rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG)) |
| - | 5216 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5217 | ||
| 5022 | rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; |
5218 | rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; |
| 5023 | queue_hdmi = true; |
5219 | queue_hdmi = true; |
| 5024 | DRM_DEBUG("IH: HDMI0\n"); |
5220 | DRM_DEBUG("IH: HDMI0\n"); |
| 5025 | } |
- | |
| 5026 | break; |
5221 | break; |
| 5027 | case 1: |
5222 | case 1: |
| 5028 | if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { |
5223 | if (!(rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG)) |
| - | 5224 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5225 | ||
| 5029 | rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; |
5226 | rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; |
| 5030 | queue_hdmi = true; |
5227 | queue_hdmi = true; |
| 5031 | DRM_DEBUG("IH: HDMI1\n"); |
5228 | DRM_DEBUG("IH: HDMI1\n"); |
| 5032 | } |
- | |
| 5033 | break; |
5229 | break; |
| 5034 | case 2: |
5230 | case 2: |
| 5035 | if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { |
5231 | if (!(rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG)) |
| - | 5232 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5233 | ||
| 5036 | rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; |
5234 | rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; |
| 5037 | queue_hdmi = true; |
5235 | queue_hdmi = true; |
| 5038 | DRM_DEBUG("IH: HDMI2\n"); |
5236 | DRM_DEBUG("IH: HDMI2\n"); |
| 5039 | } |
- | |
| 5040 | break; |
5237 | break; |
| 5041 | case 3: |
5238 | case 3: |
| 5042 | if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { |
5239 | if (!(rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG)) |
| - | 5240 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5241 | ||
| 5043 | rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; |
5242 | rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; |
| 5044 | queue_hdmi = true; |
5243 | queue_hdmi = true; |
| 5045 | DRM_DEBUG("IH: HDMI3\n"); |
5244 | DRM_DEBUG("IH: HDMI3\n"); |
| 5046 | } |
- | |
| 5047 | break; |
5245 | break; |
| 5048 | case 4: |
5246 | case 4: |
| 5049 | if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { |
5247 | if (!(rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG)) |
| - | 5248 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5249 | ||
| 5050 | rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; |
5250 | rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; |
| 5051 | queue_hdmi = true; |
5251 | queue_hdmi = true; |
| 5052 | DRM_DEBUG("IH: HDMI4\n"); |
5252 | DRM_DEBUG("IH: HDMI4\n"); |
| 5053 | } |
- | |
| 5054 | break; |
5253 | break; |
| 5055 | case 5: |
5254 | case 5: |
| 5056 | if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { |
5255 | if (!(rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG)) |
| - | 5256 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 5257 | ||
| 5057 | rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; |
5258 | rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; |
| 5058 | queue_hdmi = true; |
5259 | queue_hdmi = true; |
| 5059 | DRM_DEBUG("IH: HDMI5\n"); |
5260 | DRM_DEBUG("IH: HDMI5\n"); |
| 5060 | } |
- | |
| 5061 | break; |
5261 | break; |
| 5062 | default: |
5262 | default: |
| 5063 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); |
5263 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 5064 | break; |
5264 | break; |
| 5065 | } |
5265 | } |
| - | 5266 | case 96: |
|
| - | 5267 | DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); |
|
| - | 5268 | WREG32(SRBM_INT_ACK, 0x1); |
|
| - | 5269 | break; |
|
| 5066 | case 124: /* UVD */ |
5270 | case 124: /* UVD */ |
| 5067 | DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); |
5271 | DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); |
| 5068 | radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); |
5272 | radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); |
| 5069 | break; |
5273 | break; |
| 5070 | case 146: |
5274 | case 146: |
| Line 5211... | Line 5415... | ||
| 5211 | if (r) { |
5415 | if (r) { |
| 5212 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
5416 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
| 5213 | return r; |
5417 | return r; |
| 5214 | } |
5418 | } |
| Line 5215... | Line 5419... | ||
| 5215 | 5419 | ||
| 5216 | // r = rv770_uvd_resume(rdev); |
5420 | r = uvd_v2_2_resume(rdev); |
| 5217 | // if (!r) { |
5421 | if (!r) { |
| 5218 | // r = radeon_fence_driver_start_ring(rdev, |
5422 | r = radeon_fence_driver_start_ring(rdev, |
| 5219 | // R600_RING_TYPE_UVD_INDEX); |
5423 | R600_RING_TYPE_UVD_INDEX); |
| 5220 | // if (r) |
5424 | if (r) |
| 5221 | // dev_err(rdev->dev, "UVD fences init error (%d).\n", r); |
5425 | dev_err(rdev->dev, "UVD fences init error (%d).\n", r); |
| Line 5222... | Line 5426... | ||
| 5222 | // } |
5426 | } |
| 5223 | 5427 | ||
| Line 5224... | Line 5428... | ||
| 5224 | if (r) |
5428 | if (r) |
| Line 5232... | Line 5436... | ||
| 5232 | } |
5436 | } |
| Line 5233... | Line 5437... | ||
| 5233 | 5437 | ||
| 5234 | r = r600_irq_init(rdev); |
5438 | r = r600_irq_init(rdev); |
| 5235 | if (r) { |
5439 | if (r) { |
| 5236 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
5440 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
| 5237 | // radeon_irq_kms_fini(rdev); |
5441 | radeon_irq_kms_fini(rdev); |
| 5238 | return r; |
5442 | return r; |
| 5239 | } |
5443 | } |
| Line 5240... | Line 5444... | ||
| 5240 | evergreen_irq_set(rdev); |
5444 | evergreen_irq_set(rdev); |
| Line 5259... | Line 5463... | ||
| 5259 | return r; |
5463 | return r; |
| 5260 | r = r600_dma_resume(rdev); |
5464 | r = r600_dma_resume(rdev); |
| 5261 | if (r) |
5465 | if (r) |
| 5262 | return r; |
5466 | return r; |
| Line -... | Line 5467... | ||
| - | 5467 | ||
| - | 5468 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
|
| - | 5469 | if (ring->ring_size) { |
|
| - | 5470 | r = radeon_ring_init(rdev, ring, ring->ring_size, 0, |
|
| - | 5471 | RADEON_CP_PACKET2); |
|
| - | 5472 | if (!r) |
|
| - | 5473 | r = uvd_v1_0_init(rdev); |
|
| - | 5474 | ||
| - | 5475 | if (r) |
|
| - | 5476 | DRM_ERROR("radeon: error initializing UVD (%d).\n", r); |
|
| Line 5263... | Line 5477... | ||
| 5263 | 5477 | } |
|
| 5264 | 5478 | ||
| 5265 | r = radeon_ib_pool_init(rdev); |
5479 | r = radeon_ib_pool_init(rdev); |
| 5266 | if (r) { |
5480 | if (r) { |
| Line 5363... | Line 5577... | ||
| 5363 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
5577 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
| Line 5364... | Line 5578... | ||
| 5364 | 5578 | ||
| 5365 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
5579 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
| Line 5366... | Line 5580... | ||
| 5366 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
5580 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
| 5367 | 5581 | ||
| 5368 | // r = radeon_uvd_init(rdev); |
5582 | r = radeon_uvd_init(rdev); |
| 5369 | // if (!r) { |
5583 | if (!r) { |
| 5370 | // rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; |
5584 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; |
| 5371 | // r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], |
5585 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], |
| Line 5372... | Line 5586... | ||
| 5372 | // 4096); |
5586 | 4096); |
| 5373 | // } |
5587 | } |
| Line 5374... | Line 5588... | ||
| 5374 | 5588 | ||
| Line 5381... | Line 5595... | ||
| 5381 | 5595 | ||
| 5382 | rdev->accel_working = true; |
5596 | rdev->accel_working = true; |
| 5383 | r = evergreen_startup(rdev); |
5597 | r = evergreen_startup(rdev); |
| 5384 | if (r) { |
5598 | if (r) { |
| - | 5599 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
|
| - | 5600 | r700_cp_fini(rdev); |
|
| - | 5601 | r600_dma_fini(rdev); |
|
| - | 5602 | r600_irq_fini(rdev); |
|
| - | 5603 | if (rdev->flags & RADEON_IS_IGP) |
|
| - | 5604 | sumo_rlc_fini(rdev); |
|
| - | 5605 | radeon_wb_fini(rdev); |
|
| - | 5606 | radeon_ib_pool_fini(rdev); |
|
| - | 5607 | radeon_irq_kms_fini(rdev); |
|
| 5385 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
5608 | evergreen_pcie_gart_fini(rdev); |
| 5386 | rdev->accel_working = false; |
5609 | rdev->accel_working = false; |
| Line 5387... | Line 5610... | ||
| 5387 | } |
5610 | } |
| 5388 | 5611 | ||
| Line 5398... | Line 5621... | ||
| 5398 | } |
5621 | } |
| Line 5399... | Line 5622... | ||
| 5399 | 5622 | ||
| 5400 | return 0; |
5623 | return 0; |
| Line -... | Line 5624... | ||
| - | 5624 | } |
|
| - | 5625 | ||
| - | 5626 | void evergreen_fini(struct radeon_device *rdev) |
|
| - | 5627 | { |
|
| - | 5628 | radeon_pm_fini(rdev); |
|
| - | 5629 | radeon_audio_fini(rdev); |
|
| - | 5630 | r700_cp_fini(rdev); |
|
| - | 5631 | r600_dma_fini(rdev); |
|
| - | 5632 | r600_irq_fini(rdev); |
|
| - | 5633 | if (rdev->flags & RADEON_IS_IGP) |
|
| - | 5634 | sumo_rlc_fini(rdev); |
|
| - | 5635 | radeon_wb_fini(rdev); |
|
| - | 5636 | radeon_ib_pool_fini(rdev); |
|
| - | 5637 | radeon_irq_kms_fini(rdev); |
|
| - | 5638 | uvd_v1_0_fini(rdev); |
|
| - | 5639 | radeon_uvd_fini(rdev); |
|
| - | 5640 | evergreen_pcie_gart_fini(rdev); |
|
| - | 5641 | r600_vram_scratch_fini(rdev); |
|
| - | 5642 | radeon_gem_fini(rdev); |
|
| - | 5643 | radeon_fence_driver_fini(rdev); |
|
| - | 5644 | radeon_agp_fini(rdev); |
|
| - | 5645 | radeon_bo_fini(rdev); |
|
| - | 5646 | radeon_atombios_fini(rdev); |
|
| - | 5647 | kfree(rdev->bios); |
|
| Line 5401... | Line 5648... | ||
| 5401 | } |
5648 | rdev->bios = NULL; |
| 5402 | 5649 | } |
|
| 5403 | 5650 | ||