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Rev 3192 Rev 3764
Line 51... Line 51...
51 
void evergreen_fini(struct radeon_device *rdev);
 51 
void evergreen_fini(struct radeon_device *rdev);
52 
void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
 52 
void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
53 
extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
 53 
extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
54 
				     int ring, u32 cp_int_cntl);
 54 
				     int ring, u32 cp_int_cntl);
Line -... Line 55...
- 
 
 55 
 
- 
 
 56 
static const u32 evergreen_golden_registers[] =
- 
 
 57 
{
- 
 
 58 
	0x3f90, 0xffff0000, 0xff000000,
- 
 
 59 
	0x9148, 0xffff0000, 0xff000000,
- 
 
 60 
	0x3f94, 0xffff0000, 0xff000000,
- 
 
 61 
	0x914c, 0xffff0000, 0xff000000,
- 
 
 62 
	0x9b7c, 0xffffffff, 0x00000000,
- 
 
 63 
	0x8a14, 0xffffffff, 0x00000007,
- 
 
 64 
	0x8b10, 0xffffffff, 0x00000000,
- 
 
 65 
	0x960c, 0xffffffff, 0x54763210,
- 
 
 66 
	0x88c4, 0xffffffff, 0x000000c2,
- 
 
 67 
	0x88d4, 0xffffffff, 0x00000010,
- 
 
 68 
	0x8974, 0xffffffff, 0x00000000,
- 
 
 69 
	0xc78, 0x00000080, 0x00000080,
- 
 
 70 
	0x5eb4, 0xffffffff, 0x00000002,
- 
 
 71 
	0x5e78, 0xffffffff, 0x001000f0,
- 
 
 72 
	0x6104, 0x01000300, 0x00000000,
- 
 
 73 
	0x5bc0, 0x00300000, 0x00000000,
- 
 
 74 
	0x7030, 0xffffffff, 0x00000011,
- 
 
 75 
	0x7c30, 0xffffffff, 0x00000011,
- 
 
 76 
	0x10830, 0xffffffff, 0x00000011,
- 
 
 77 
	0x11430, 0xffffffff, 0x00000011,
- 
 
 78 
	0x12030, 0xffffffff, 0x00000011,
- 
 
 79 
	0x12c30, 0xffffffff, 0x00000011,
- 
 
 80 
	0xd02c, 0xffffffff, 0x08421000,
- 
 
 81 
	0x240c, 0xffffffff, 0x00000380,
- 
 
 82 
	0x8b24, 0xffffffff, 0x00ff0fff,
- 
 
 83 
	0x28a4c, 0x06000000, 0x06000000,
- 
 
 84 
	0x10c, 0x00000001, 0x00000001,
- 
 
 85 
	0x8d00, 0xffffffff, 0x100e4848,
- 
 
 86 
	0x8d04, 0xffffffff, 0x00164745,
- 
 
 87 
	0x8c00, 0xffffffff, 0xe4000003,
- 
 
 88 
	0x8c04, 0xffffffff, 0x40600060,
- 
 
 89 
	0x8c08, 0xffffffff, 0x001c001c,
- 
 
 90 
	0x8cf0, 0xffffffff, 0x08e00620,
- 
 
 91 
	0x8c20, 0xffffffff, 0x00800080,
- 
 
 92 
	0x8c24, 0xffffffff, 0x00800080,
- 
 
 93 
	0x8c18, 0xffffffff, 0x20202078,
- 
 
 94 
	0x8c1c, 0xffffffff, 0x00001010,
- 
 
 95 
	0x28350, 0xffffffff, 0x00000000,
- 
 
 96 
	0xa008, 0xffffffff, 0x00010000,
- 
 
 97 
	0x5cc, 0xffffffff, 0x00000001,
- 
 
 98 
	0x9508, 0xffffffff, 0x00000002,
- 
 
 99 
	0x913c, 0x0000000f, 0x0000000a
- 
 
 100 
};
- 
 
 101 
 
- 
 
 102 
static const u32 evergreen_golden_registers2[] =
- 
 
 103 
{
- 
 
 104 
	0x2f4c, 0xffffffff, 0x00000000,
- 
 
 105 
	0x54f4, 0xffffffff, 0x00000000,
- 
 
 106 
	0x54f0, 0xffffffff, 0x00000000,
- 
 
 107 
	0x5498, 0xffffffff, 0x00000000,
- 
 
 108 
	0x549c, 0xffffffff, 0x00000000,
- 
 
 109 
	0x5494, 0xffffffff, 0x00000000,
- 
 
 110 
	0x53cc, 0xffffffff, 0x00000000,
- 
 
 111 
	0x53c8, 0xffffffff, 0x00000000,
- 
 
 112 
	0x53c4, 0xffffffff, 0x00000000,
- 
 
 113 
	0x53c0, 0xffffffff, 0x00000000,
- 
 
 114 
	0x53bc, 0xffffffff, 0x00000000,
- 
 
 115 
	0x53b8, 0xffffffff, 0x00000000,
- 
 
 116 
	0x53b4, 0xffffffff, 0x00000000,
- 
 
 117 
	0x53b0, 0xffffffff, 0x00000000
- 
 
 118 
};
- 
 
 119 
 
- 
 
 120 
static const u32 cypress_mgcg_init[] =
- 
 
 121 
{
- 
 
 122 
	0x802c, 0xffffffff, 0xc0000000,
- 
 
 123 
	0x5448, 0xffffffff, 0x00000100,
- 
 
 124 
	0x55e4, 0xffffffff, 0x00000100,
- 
 
 125 
	0x160c, 0xffffffff, 0x00000100,
- 
 
 126 
	0x5644, 0xffffffff, 0x00000100,
- 
 
 127 
	0xc164, 0xffffffff, 0x00000100,
- 
 
 128 
	0x8a18, 0xffffffff, 0x00000100,
- 
 
 129 
	0x897c, 0xffffffff, 0x06000100,
- 
 
 130 
	0x8b28, 0xffffffff, 0x00000100,
- 
 
 131 
	0x9144, 0xffffffff, 0x00000100,
- 
 
 132 
	0x9a60, 0xffffffff, 0x00000100,
- 
 
 133 
	0x9868, 0xffffffff, 0x00000100,
- 
 
 134 
	0x8d58, 0xffffffff, 0x00000100,
- 
 
 135 
	0x9510, 0xffffffff, 0x00000100,
- 
 
 136 
	0x949c, 0xffffffff, 0x00000100,
- 
 
 137 
	0x9654, 0xffffffff, 0x00000100,
- 
 
 138 
	0x9030, 0xffffffff, 0x00000100,
- 
 
 139 
	0x9034, 0xffffffff, 0x00000100,
- 
 
 140 
	0x9038, 0xffffffff, 0x00000100,
- 
 
 141 
	0x903c, 0xffffffff, 0x00000100,
- 
 
 142 
	0x9040, 0xffffffff, 0x00000100,
- 
 
 143 
	0xa200, 0xffffffff, 0x00000100,
- 
 
 144 
	0xa204, 0xffffffff, 0x00000100,
- 
 
 145 
	0xa208, 0xffffffff, 0x00000100,
- 
 
 146 
	0xa20c, 0xffffffff, 0x00000100,
- 
 
 147 
	0x971c, 0xffffffff, 0x00000100,
- 
 
 148 
	0x977c, 0xffffffff, 0x00000100,
- 
 
 149 
	0x3f80, 0xffffffff, 0x00000100,
- 
 
 150 
	0xa210, 0xffffffff, 0x00000100,
- 
 
 151 
	0xa214, 0xffffffff, 0x00000100,
- 
 
 152 
	0x4d8, 0xffffffff, 0x00000100,
- 
 
 153 
	0x9784, 0xffffffff, 0x00000100,
- 
 
 154 
	0x9698, 0xffffffff, 0x00000100,
- 
 
 155 
	0x4d4, 0xffffffff, 0x00000200,
- 
 
 156 
	0x30cc, 0xffffffff, 0x00000100,
- 
 
 157 
	0xd0c0, 0xffffffff, 0xff000100,
- 
 
 158 
	0x802c, 0xffffffff, 0x40000000,
- 
 
 159 
	0x915c, 0xffffffff, 0x00010000,
- 
 
 160 
	0x9160, 0xffffffff, 0x00030002,
- 
 
 161 
	0x9178, 0xffffffff, 0x00070000,
- 
 
 162 
	0x917c, 0xffffffff, 0x00030002,
- 
 
 163 
	0x9180, 0xffffffff, 0x00050004,
- 
 
 164 
	0x918c, 0xffffffff, 0x00010006,
- 
 
 165 
	0x9190, 0xffffffff, 0x00090008,
- 
 
 166 
	0x9194, 0xffffffff, 0x00070000,
- 
 
 167 
	0x9198, 0xffffffff, 0x00030002,
- 
 
 168 
	0x919c, 0xffffffff, 0x00050004,
- 
 
 169 
	0x91a8, 0xffffffff, 0x00010006,
- 
 
 170 
	0x91ac, 0xffffffff, 0x00090008,
- 
 
 171 
	0x91b0, 0xffffffff, 0x00070000,
- 
 
 172 
	0x91b4, 0xffffffff, 0x00030002,
- 
 
 173 
	0x91b8, 0xffffffff, 0x00050004,
- 
 
 174 
	0x91c4, 0xffffffff, 0x00010006,
- 
 
 175 
	0x91c8, 0xffffffff, 0x00090008,
- 
 
 176 
	0x91cc, 0xffffffff, 0x00070000,
- 
 
 177 
	0x91d0, 0xffffffff, 0x00030002,
- 
 
 178 
	0x91d4, 0xffffffff, 0x00050004,
- 
 
 179 
	0x91e0, 0xffffffff, 0x00010006,
- 
 
 180 
	0x91e4, 0xffffffff, 0x00090008,
- 
 
 181 
	0x91e8, 0xffffffff, 0x00000000,
- 
 
 182 
	0x91ec, 0xffffffff, 0x00070000,
- 
 
 183 
	0x91f0, 0xffffffff, 0x00030002,
- 
 
 184 
	0x91f4, 0xffffffff, 0x00050004,
- 
 
 185 
	0x9200, 0xffffffff, 0x00010006,
- 
 
 186 
	0x9204, 0xffffffff, 0x00090008,
- 
 
 187 
	0x9208, 0xffffffff, 0x00070000,
- 
 
 188 
	0x920c, 0xffffffff, 0x00030002,
- 
 
 189 
	0x9210, 0xffffffff, 0x00050004,
- 
 
 190 
	0x921c, 0xffffffff, 0x00010006,
- 
 
 191 
	0x9220, 0xffffffff, 0x00090008,
- 
 
 192 
	0x9224, 0xffffffff, 0x00070000,
- 
 
 193 
	0x9228, 0xffffffff, 0x00030002,
- 
 
 194 
	0x922c, 0xffffffff, 0x00050004,
- 
 
 195 
	0x9238, 0xffffffff, 0x00010006,
- 
 
 196 
	0x923c, 0xffffffff, 0x00090008,
- 
 
 197 
	0x9240, 0xffffffff, 0x00070000,
- 
 
 198 
	0x9244, 0xffffffff, 0x00030002,
- 
 
 199 
	0x9248, 0xffffffff, 0x00050004,
- 
 
 200 
	0x9254, 0xffffffff, 0x00010006,
- 
 
 201 
	0x9258, 0xffffffff, 0x00090008,
- 
 
 202 
	0x925c, 0xffffffff, 0x00070000,
- 
 
 203 
	0x9260, 0xffffffff, 0x00030002,
- 
 
 204 
	0x9264, 0xffffffff, 0x00050004,
- 
 
 205 
	0x9270, 0xffffffff, 0x00010006,
- 
 
 206 
	0x9274, 0xffffffff, 0x00090008,
- 
 
 207 
	0x9278, 0xffffffff, 0x00070000,
- 
 
 208 
	0x927c, 0xffffffff, 0x00030002,
- 
 
 209 
	0x9280, 0xffffffff, 0x00050004,
- 
 
 210 
	0x928c, 0xffffffff, 0x00010006,
- 
 
 211 
	0x9290, 0xffffffff, 0x00090008,
- 
 
 212 
	0x9294, 0xffffffff, 0x00000000,
- 
 
 213 
	0x929c, 0xffffffff, 0x00000001,
- 
 
 214 
	0x802c, 0xffffffff, 0x40010000,
- 
 
 215 
	0x915c, 0xffffffff, 0x00010000,
- 
 
 216 
	0x9160, 0xffffffff, 0x00030002,
- 
 
 217 
	0x9178, 0xffffffff, 0x00070000,
- 
 
 218 
	0x917c, 0xffffffff, 0x00030002,
- 
 
 219 
	0x9180, 0xffffffff, 0x00050004,
- 
 
 220 
	0x918c, 0xffffffff, 0x00010006,
- 
 
 221 
	0x9190, 0xffffffff, 0x00090008,
- 
 
 222 
	0x9194, 0xffffffff, 0x00070000,
- 
 
 223 
	0x9198, 0xffffffff, 0x00030002,
- 
 
 224 
	0x919c, 0xffffffff, 0x00050004,
- 
 
 225 
	0x91a8, 0xffffffff, 0x00010006,
- 
 
 226 
	0x91ac, 0xffffffff, 0x00090008,
- 
 
 227 
	0x91b0, 0xffffffff, 0x00070000,
- 
 
 228 
	0x91b4, 0xffffffff, 0x00030002,
- 
 
 229 
	0x91b8, 0xffffffff, 0x00050004,
- 
 
 230 
	0x91c4, 0xffffffff, 0x00010006,
- 
 
 231 
	0x91c8, 0xffffffff, 0x00090008,
- 
 
 232 
	0x91cc, 0xffffffff, 0x00070000,
- 
 
 233 
	0x91d0, 0xffffffff, 0x00030002,
- 
 
 234 
	0x91d4, 0xffffffff, 0x00050004,
- 
 
 235 
	0x91e0, 0xffffffff, 0x00010006,
- 
 
 236 
	0x91e4, 0xffffffff, 0x00090008,
- 
 
 237 
	0x91e8, 0xffffffff, 0x00000000,
- 
 
 238 
	0x91ec, 0xffffffff, 0x00070000,
- 
 
 239 
	0x91f0, 0xffffffff, 0x00030002,
- 
 
 240 
	0x91f4, 0xffffffff, 0x00050004,
- 
 
 241 
	0x9200, 0xffffffff, 0x00010006,
- 
 
 242 
	0x9204, 0xffffffff, 0x00090008,
- 
 
 243 
	0x9208, 0xffffffff, 0x00070000,
- 
 
 244 
	0x920c, 0xffffffff, 0x00030002,
- 
 
 245 
	0x9210, 0xffffffff, 0x00050004,
- 
 
 246 
	0x921c, 0xffffffff, 0x00010006,
- 
 
 247 
	0x9220, 0xffffffff, 0x00090008,
- 
 
 248 
	0x9224, 0xffffffff, 0x00070000,
- 
 
 249 
	0x9228, 0xffffffff, 0x00030002,
- 
 
 250 
	0x922c, 0xffffffff, 0x00050004,
- 
 
 251 
	0x9238, 0xffffffff, 0x00010006,
- 
 
 252 
	0x923c, 0xffffffff, 0x00090008,
- 
 
 253 
	0x9240, 0xffffffff, 0x00070000,
- 
 
 254 
	0x9244, 0xffffffff, 0x00030002,
- 
 
 255 
	0x9248, 0xffffffff, 0x00050004,
- 
 
 256 
	0x9254, 0xffffffff, 0x00010006,
- 
 
 257 
	0x9258, 0xffffffff, 0x00090008,
- 
 
 258 
	0x925c, 0xffffffff, 0x00070000,
- 
 
 259 
	0x9260, 0xffffffff, 0x00030002,
- 
 
 260 
	0x9264, 0xffffffff, 0x00050004,
- 
 
 261 
	0x9270, 0xffffffff, 0x00010006,
- 
 
 262 
	0x9274, 0xffffffff, 0x00090008,
- 
 
 263 
	0x9278, 0xffffffff, 0x00070000,
- 
 
 264 
	0x927c, 0xffffffff, 0x00030002,
- 
 
 265 
	0x9280, 0xffffffff, 0x00050004,
- 
 
 266 
	0x928c, 0xffffffff, 0x00010006,
- 
 
 267 
	0x9290, 0xffffffff, 0x00090008,
- 
 
 268 
	0x9294, 0xffffffff, 0x00000000,
- 
 
 269 
	0x929c, 0xffffffff, 0x00000001,
- 
 
 270 
	0x802c, 0xffffffff, 0xc0000000
- 
 
 271 
};
- 
 
 272 
 
- 
 
 273 
static const u32 redwood_mgcg_init[] =
- 
 
 274 
{
- 
 
 275 
	0x802c, 0xffffffff, 0xc0000000,
- 
 
 276 
	0x5448, 0xffffffff, 0x00000100,
- 
 
 277 
	0x55e4, 0xffffffff, 0x00000100,
- 
 
 278 
	0x160c, 0xffffffff, 0x00000100,
- 
 
 279 
	0x5644, 0xffffffff, 0x00000100,
- 
 
 280 
	0xc164, 0xffffffff, 0x00000100,
- 
 
 281 
	0x8a18, 0xffffffff, 0x00000100,
- 
 
 282 
	0x897c, 0xffffffff, 0x06000100,
- 
 
 283 
	0x8b28, 0xffffffff, 0x00000100,
- 
 
 284 
	0x9144, 0xffffffff, 0x00000100,
- 
 
 285 
	0x9a60, 0xffffffff, 0x00000100,
- 
 
 286 
	0x9868, 0xffffffff, 0x00000100,
- 
 
 287 
	0x8d58, 0xffffffff, 0x00000100,
- 
 
 288 
	0x9510, 0xffffffff, 0x00000100,
- 
 
 289 
	0x949c, 0xffffffff, 0x00000100,
- 
 
 290 
	0x9654, 0xffffffff, 0x00000100,
- 
 
 291 
	0x9030, 0xffffffff, 0x00000100,
- 
 
 292 
	0x9034, 0xffffffff, 0x00000100,
- 
 
 293 
	0x9038, 0xffffffff, 0x00000100,
- 
 
 294 
	0x903c, 0xffffffff, 0x00000100,
- 
 
 295 
	0x9040, 0xffffffff, 0x00000100,
- 
 
 296 
	0xa200, 0xffffffff, 0x00000100,
- 
 
 297 
	0xa204, 0xffffffff, 0x00000100,
- 
 
 298 
	0xa208, 0xffffffff, 0x00000100,
- 
 
 299 
	0xa20c, 0xffffffff, 0x00000100,
- 
 
 300 
	0x971c, 0xffffffff, 0x00000100,
- 
 
 301 
	0x977c, 0xffffffff, 0x00000100,
- 
 
 302 
	0x3f80, 0xffffffff, 0x00000100,
- 
 
 303 
	0xa210, 0xffffffff, 0x00000100,
- 
 
 304 
	0xa214, 0xffffffff, 0x00000100,
- 
 
 305 
	0x4d8, 0xffffffff, 0x00000100,
- 
 
 306 
	0x9784, 0xffffffff, 0x00000100,
- 
 
 307 
	0x9698, 0xffffffff, 0x00000100,
- 
 
 308 
	0x4d4, 0xffffffff, 0x00000200,
- 
 
 309 
	0x30cc, 0xffffffff, 0x00000100,
- 
 
 310 
	0xd0c0, 0xffffffff, 0xff000100,
- 
 
 311 
	0x802c, 0xffffffff, 0x40000000,
- 
 
 312 
	0x915c, 0xffffffff, 0x00010000,
- 
 
 313 
	0x9160, 0xffffffff, 0x00030002,
- 
 
 314 
	0x9178, 0xffffffff, 0x00070000,
- 
 
 315 
	0x917c, 0xffffffff, 0x00030002,
- 
 
 316 
	0x9180, 0xffffffff, 0x00050004,
- 
 
 317 
	0x918c, 0xffffffff, 0x00010006,
- 
 
 318 
	0x9190, 0xffffffff, 0x00090008,
- 
 
 319 
	0x9194, 0xffffffff, 0x00070000,
- 
 
 320 
	0x9198, 0xffffffff, 0x00030002,
- 
 
 321 
	0x919c, 0xffffffff, 0x00050004,
- 
 
 322 
	0x91a8, 0xffffffff, 0x00010006,
- 
 
 323 
	0x91ac, 0xffffffff, 0x00090008,
- 
 
 324 
	0x91b0, 0xffffffff, 0x00070000,
- 
 
 325 
	0x91b4, 0xffffffff, 0x00030002,
- 
 
 326 
	0x91b8, 0xffffffff, 0x00050004,
- 
 
 327 
	0x91c4, 0xffffffff, 0x00010006,
- 
 
 328 
	0x91c8, 0xffffffff, 0x00090008,
- 
 
 329 
	0x91cc, 0xffffffff, 0x00070000,
- 
 
 330 
	0x91d0, 0xffffffff, 0x00030002,
- 
 
 331 
	0x91d4, 0xffffffff, 0x00050004,
- 
 
 332 
	0x91e0, 0xffffffff, 0x00010006,
- 
 
 333 
	0x91e4, 0xffffffff, 0x00090008,
- 
 
 334 
	0x91e8, 0xffffffff, 0x00000000,
- 
 
 335 
	0x91ec, 0xffffffff, 0x00070000,
- 
 
 336 
	0x91f0, 0xffffffff, 0x00030002,
- 
 
 337 
	0x91f4, 0xffffffff, 0x00050004,
- 
 
 338 
	0x9200, 0xffffffff, 0x00010006,
- 
 
 339 
	0x9204, 0xffffffff, 0x00090008,
- 
 
 340 
	0x9294, 0xffffffff, 0x00000000,
- 
 
 341 
	0x929c, 0xffffffff, 0x00000001,
- 
 
 342 
	0x802c, 0xffffffff, 0xc0000000
- 
 
 343 
};
- 
 
 344 
 
- 
 
 345 
static const u32 cedar_golden_registers[] =
- 
 
 346 
{
- 
 
 347 
	0x3f90, 0xffff0000, 0xff000000,
- 
 
 348 
	0x9148, 0xffff0000, 0xff000000,
- 
 
 349 
	0x3f94, 0xffff0000, 0xff000000,
- 
 
 350 
	0x914c, 0xffff0000, 0xff000000,
- 
 
 351 
	0x9b7c, 0xffffffff, 0x00000000,
- 
 
 352 
	0x8a14, 0xffffffff, 0x00000007,
- 
 
 353 
	0x8b10, 0xffffffff, 0x00000000,
- 
 
 354 
	0x960c, 0xffffffff, 0x54763210,
- 
 
 355 
	0x88c4, 0xffffffff, 0x000000c2,
- 
 
 356 
	0x88d4, 0xffffffff, 0x00000000,
- 
 
 357 
	0x8974, 0xffffffff, 0x00000000,
- 
 
 358 
	0xc78, 0x00000080, 0x00000080,
- 
 
 359 
	0x5eb4, 0xffffffff, 0x00000002,
- 
 
 360 
	0x5e78, 0xffffffff, 0x001000f0,
- 
 
 361 
	0x6104, 0x01000300, 0x00000000,
- 
 
 362 
	0x5bc0, 0x00300000, 0x00000000,
- 
 
 363 
	0x7030, 0xffffffff, 0x00000011,
- 
 
 364 
	0x7c30, 0xffffffff, 0x00000011,
- 
 
 365 
	0x10830, 0xffffffff, 0x00000011,
- 
 
 366 
	0x11430, 0xffffffff, 0x00000011,
- 
 
 367 
	0xd02c, 0xffffffff, 0x08421000,
- 
 
 368 
	0x240c, 0xffffffff, 0x00000380,
- 
 
 369 
	0x8b24, 0xffffffff, 0x00ff0fff,
- 
 
 370 
	0x28a4c, 0x06000000, 0x06000000,
- 
 
 371 
	0x10c, 0x00000001, 0x00000001,
- 
 
 372 
	0x8d00, 0xffffffff, 0x100e4848,
- 
 
 373 
	0x8d04, 0xffffffff, 0x00164745,
- 
 
 374 
	0x8c00, 0xffffffff, 0xe4000003,
- 
 
 375 
	0x8c04, 0xffffffff, 0x40600060,
- 
 
 376 
	0x8c08, 0xffffffff, 0x001c001c,
- 
 
 377 
	0x8cf0, 0xffffffff, 0x08e00410,
- 
 
 378 
	0x8c20, 0xffffffff, 0x00800080,
- 
 
 379 
	0x8c24, 0xffffffff, 0x00800080,
- 
 
 380 
	0x8c18, 0xffffffff, 0x20202078,
- 
 
 381 
	0x8c1c, 0xffffffff, 0x00001010,
- 
 
 382 
	0x28350, 0xffffffff, 0x00000000,
- 
 
 383 
	0xa008, 0xffffffff, 0x00010000,
- 
 
 384 
	0x5cc, 0xffffffff, 0x00000001,
- 
 
 385 
	0x9508, 0xffffffff, 0x00000002
- 
 
 386 
};
- 
 
 387 
 
- 
 
 388 
static const u32 cedar_mgcg_init[] =
- 
 
 389 
{
- 
 
 390 
	0x802c, 0xffffffff, 0xc0000000,
- 
 
 391 
	0x5448, 0xffffffff, 0x00000100,
- 
 
 392 
	0x55e4, 0xffffffff, 0x00000100,
- 
 
 393 
	0x160c, 0xffffffff, 0x00000100,
- 
 
 394 
	0x5644, 0xffffffff, 0x00000100,
- 
 
 395 
	0xc164, 0xffffffff, 0x00000100,
- 
 
 396 
	0x8a18, 0xffffffff, 0x00000100,
- 
 
 397 
	0x897c, 0xffffffff, 0x06000100,
- 
 
 398 
	0x8b28, 0xffffffff, 0x00000100,
- 
 
 399 
	0x9144, 0xffffffff, 0x00000100,
- 
 
 400 
	0x9a60, 0xffffffff, 0x00000100,
- 
 
 401 
	0x9868, 0xffffffff, 0x00000100,
- 
 
 402 
	0x8d58, 0xffffffff, 0x00000100,
- 
 
 403 
	0x9510, 0xffffffff, 0x00000100,
- 
 
 404 
	0x949c, 0xffffffff, 0x00000100,
- 
 
 405 
	0x9654, 0xffffffff, 0x00000100,
- 
 
 406 
	0x9030, 0xffffffff, 0x00000100,
- 
 
 407 
	0x9034, 0xffffffff, 0x00000100,
- 
 
 408 
	0x9038, 0xffffffff, 0x00000100,
- 
 
 409 
	0x903c, 0xffffffff, 0x00000100,
- 
 
 410 
	0x9040, 0xffffffff, 0x00000100,
- 
 
 411 
	0xa200, 0xffffffff, 0x00000100,
- 
 
 412 
	0xa204, 0xffffffff, 0x00000100,
- 
 
 413 
	0xa208, 0xffffffff, 0x00000100,
- 
 
 414 
	0xa20c, 0xffffffff, 0x00000100,
- 
 
 415 
	0x971c, 0xffffffff, 0x00000100,
- 
 
 416 
	0x977c, 0xffffffff, 0x00000100,
- 
 
 417 
	0x3f80, 0xffffffff, 0x00000100,
- 
 
 418 
	0xa210, 0xffffffff, 0x00000100,
- 
 
 419 
	0xa214, 0xffffffff, 0x00000100,
- 
 
 420 
	0x4d8, 0xffffffff, 0x00000100,
- 
 
 421 
	0x9784, 0xffffffff, 0x00000100,
- 
 
 422 
	0x9698, 0xffffffff, 0x00000100,
- 
 
 423 
	0x4d4, 0xffffffff, 0x00000200,
- 
 
 424 
	0x30cc, 0xffffffff, 0x00000100,
- 
 
 425 
	0xd0c0, 0xffffffff, 0xff000100,
- 
 
 426 
	0x802c, 0xffffffff, 0x40000000,
- 
 
 427 
	0x915c, 0xffffffff, 0x00010000,
- 
 
 428 
	0x9178, 0xffffffff, 0x00050000,
- 
 
 429 
	0x917c, 0xffffffff, 0x00030002,
- 
 
 430 
	0x918c, 0xffffffff, 0x00010004,
- 
 
 431 
	0x9190, 0xffffffff, 0x00070006,
- 
 
 432 
	0x9194, 0xffffffff, 0x00050000,
- 
 
 433 
	0x9198, 0xffffffff, 0x00030002,
- 
 
 434 
	0x91a8, 0xffffffff, 0x00010004,
- 
 
 435 
	0x91ac, 0xffffffff, 0x00070006,
- 
 
 436 
	0x91e8, 0xffffffff, 0x00000000,
- 
 
 437 
	0x9294, 0xffffffff, 0x00000000,
- 
 
 438 
	0x929c, 0xffffffff, 0x00000001,
- 
 
 439 
	0x802c, 0xffffffff, 0xc0000000
- 
 
 440 
};
- 
 
 441 
 
- 
 
 442 
static const u32 juniper_mgcg_init[] =
- 
 
 443 
{
- 
 
 444 
	0x802c, 0xffffffff, 0xc0000000,
- 
 
 445 
	0x5448, 0xffffffff, 0x00000100,
- 
 
 446 
	0x55e4, 0xffffffff, 0x00000100,
- 
 
 447 
	0x160c, 0xffffffff, 0x00000100,
- 
 
 448 
	0x5644, 0xffffffff, 0x00000100,
- 
 
 449 
	0xc164, 0xffffffff, 0x00000100,
- 
 
 450 
	0x8a18, 0xffffffff, 0x00000100,
- 
 
 451 
	0x897c, 0xffffffff, 0x06000100,
- 
 
 452 
	0x8b28, 0xffffffff, 0x00000100,
- 
 
 453 
	0x9144, 0xffffffff, 0x00000100,
- 
 
 454 
	0x9a60, 0xffffffff, 0x00000100,
- 
 
 455 
	0x9868, 0xffffffff, 0x00000100,
- 
 
 456 
	0x8d58, 0xffffffff, 0x00000100,
- 
 
 457 
	0x9510, 0xffffffff, 0x00000100,
- 
 
 458 
	0x949c, 0xffffffff, 0x00000100,
- 
 
 459 
	0x9654, 0xffffffff, 0x00000100,
- 
 
 460 
	0x9030, 0xffffffff, 0x00000100,
- 
 
 461 
	0x9034, 0xffffffff, 0x00000100,
- 
 
 462 
	0x9038, 0xffffffff, 0x00000100,
- 
 
 463 
	0x903c, 0xffffffff, 0x00000100,
- 
 
 464 
	0x9040, 0xffffffff, 0x00000100,
- 
 
 465 
	0xa200, 0xffffffff, 0x00000100,
- 
 
 466 
	0xa204, 0xffffffff, 0x00000100,
- 
 
 467 
	0xa208, 0xffffffff, 0x00000100,
- 
 
 468 
	0xa20c, 0xffffffff, 0x00000100,
- 
 
 469 
	0x971c, 0xffffffff, 0x00000100,
- 
 
 470 
	0xd0c0, 0xffffffff, 0xff000100,
- 
 
 471 
	0x802c, 0xffffffff, 0x40000000,
- 
 
 472 
	0x915c, 0xffffffff, 0x00010000,
- 
 
 473 
	0x9160, 0xffffffff, 0x00030002,
- 
 
 474 
	0x9178, 0xffffffff, 0x00070000,
- 
 
 475 
	0x917c, 0xffffffff, 0x00030002,
- 
 
 476 
	0x9180, 0xffffffff, 0x00050004,
- 
 
 477 
	0x918c, 0xffffffff, 0x00010006,
- 
 
 478 
	0x9190, 0xffffffff, 0x00090008,
- 
 
 479 
	0x9194, 0xffffffff, 0x00070000,
- 
 
 480 
	0x9198, 0xffffffff, 0x00030002,
- 
 
 481 
	0x919c, 0xffffffff, 0x00050004,
- 
 
 482 
	0x91a8, 0xffffffff, 0x00010006,
- 
 
 483 
	0x91ac, 0xffffffff, 0x00090008,
- 
 
 484 
	0x91b0, 0xffffffff, 0x00070000,
- 
 
 485 
	0x91b4, 0xffffffff, 0x00030002,
- 
 
 486 
	0x91b8, 0xffffffff, 0x00050004,
- 
 
 487 
	0x91c4, 0xffffffff, 0x00010006,
- 
 
 488 
	0x91c8, 0xffffffff, 0x00090008,
- 
 
 489 
	0x91cc, 0xffffffff, 0x00070000,
- 
 
 490 
	0x91d0, 0xffffffff, 0x00030002,
- 
 
 491 
	0x91d4, 0xffffffff, 0x00050004,
- 
 
 492 
	0x91e0, 0xffffffff, 0x00010006,
- 
 
 493 
	0x91e4, 0xffffffff, 0x00090008,
- 
 
 494 
	0x91e8, 0xffffffff, 0x00000000,
- 
 
 495 
	0x91ec, 0xffffffff, 0x00070000,
- 
 
 496 
	0x91f0, 0xffffffff, 0x00030002,
- 
 
 497 
	0x91f4, 0xffffffff, 0x00050004,
- 
 
 498 
	0x9200, 0xffffffff, 0x00010006,
- 
 
 499 
	0x9204, 0xffffffff, 0x00090008,
- 
 
 500 
	0x9208, 0xffffffff, 0x00070000,
- 
 
 501 
	0x920c, 0xffffffff, 0x00030002,
- 
 
 502 
	0x9210, 0xffffffff, 0x00050004,
- 
 
 503 
	0x921c, 0xffffffff, 0x00010006,
- 
 
 504 
	0x9220, 0xffffffff, 0x00090008,
- 
 
 505 
	0x9224, 0xffffffff, 0x00070000,
- 
 
 506 
	0x9228, 0xffffffff, 0x00030002,
- 
 
 507 
	0x922c, 0xffffffff, 0x00050004,
- 
 
 508 
	0x9238, 0xffffffff, 0x00010006,
- 
 
 509 
	0x923c, 0xffffffff, 0x00090008,
- 
 
 510 
	0x9240, 0xffffffff, 0x00070000,
- 
 
 511 
	0x9244, 0xffffffff, 0x00030002,
- 
 
 512 
	0x9248, 0xffffffff, 0x00050004,
- 
 
 513 
	0x9254, 0xffffffff, 0x00010006,
- 
 
 514 
	0x9258, 0xffffffff, 0x00090008,
- 
 
 515 
	0x925c, 0xffffffff, 0x00070000,
- 
 
 516 
	0x9260, 0xffffffff, 0x00030002,
- 
 
 517 
	0x9264, 0xffffffff, 0x00050004,
- 
 
 518 
	0x9270, 0xffffffff, 0x00010006,
- 
 
 519 
	0x9274, 0xffffffff, 0x00090008,
- 
 
 520 
	0x9278, 0xffffffff, 0x00070000,
- 
 
 521 
	0x927c, 0xffffffff, 0x00030002,
- 
 
 522 
	0x9280, 0xffffffff, 0x00050004,
- 
 
 523 
	0x928c, 0xffffffff, 0x00010006,
- 
 
 524 
	0x9290, 0xffffffff, 0x00090008,
- 
 
 525 
	0x9294, 0xffffffff, 0x00000000,
- 
 
 526 
	0x929c, 0xffffffff, 0x00000001,
- 
 
 527 
	0x802c, 0xffffffff, 0xc0000000,
- 
 
 528 
	0x977c, 0xffffffff, 0x00000100,
- 
 
 529 
	0x3f80, 0xffffffff, 0x00000100,
- 
 
 530 
	0xa210, 0xffffffff, 0x00000100,
- 
 
 531 
	0xa214, 0xffffffff, 0x00000100,
- 
 
 532 
	0x4d8, 0xffffffff, 0x00000100,
- 
 
 533 
	0x9784, 0xffffffff, 0x00000100,
- 
 
 534 
	0x9698, 0xffffffff, 0x00000100,
- 
 
 535 
	0x4d4, 0xffffffff, 0x00000200,
- 
 
 536 
	0x30cc, 0xffffffff, 0x00000100,
- 
 
 537 
	0x802c, 0xffffffff, 0xc0000000
- 
 
 538 
};
- 
 
 539 
 
- 
 
 540 
static const u32 supersumo_golden_registers[] =
- 
 
 541 
{
- 
 
 542 
	0x5eb4, 0xffffffff, 0x00000002,
- 
 
 543 
	0x5cc, 0xffffffff, 0x00000001,
- 
 
 544 
	0x7030, 0xffffffff, 0x00000011,
- 
 
 545 
	0x7c30, 0xffffffff, 0x00000011,
- 
 
 546 
	0x6104, 0x01000300, 0x00000000,
- 
 
 547 
	0x5bc0, 0x00300000, 0x00000000,
- 
 
 548 
	0x8c04, 0xffffffff, 0x40600060,
- 
 
 549 
	0x8c08, 0xffffffff, 0x001c001c,
- 
 
 550 
	0x8c20, 0xffffffff, 0x00800080,
- 
 
 551 
	0x8c24, 0xffffffff, 0x00800080,
- 
 
 552 
	0x8c18, 0xffffffff, 0x20202078,
- 
 
 553 
	0x8c1c, 0xffffffff, 0x00001010,
- 
 
 554 
	0x918c, 0xffffffff, 0x00010006,
- 
 
 555 
	0x91a8, 0xffffffff, 0x00010006,
- 
 
 556 
	0x91c4, 0xffffffff, 0x00010006,
- 
 
 557 
	0x91e0, 0xffffffff, 0x00010006,
- 
 
 558 
	0x9200, 0xffffffff, 0x00010006,
- 
 
 559 
	0x9150, 0xffffffff, 0x6e944040,
- 
 
 560 
	0x917c, 0xffffffff, 0x00030002,
- 
 
 561 
	0x9180, 0xffffffff, 0x00050004,
- 
 
 562 
	0x9198, 0xffffffff, 0x00030002,
- 
 
 563 
	0x919c, 0xffffffff, 0x00050004,
- 
 
 564 
	0x91b4, 0xffffffff, 0x00030002,
- 
 
 565 
	0x91b8, 0xffffffff, 0x00050004,
- 
 
 566 
	0x91d0, 0xffffffff, 0x00030002,
- 
 
 567 
	0x91d4, 0xffffffff, 0x00050004,
- 
 
 568 
	0x91f0, 0xffffffff, 0x00030002,
- 
 
 569 
	0x91f4, 0xffffffff, 0x00050004,
- 
 
 570 
	0x915c, 0xffffffff, 0x00010000,
- 
 
 571 
	0x9160, 0xffffffff, 0x00030002,
- 
 
 572 
	0x3f90, 0xffff0000, 0xff000000,
- 
 
 573 
	0x9178, 0xffffffff, 0x00070000,
- 
 
 574 
	0x9194, 0xffffffff, 0x00070000,
- 
 
 575 
	0x91b0, 0xffffffff, 0x00070000,
- 
 
 576 
	0x91cc, 0xffffffff, 0x00070000,
- 
 
 577 
	0x91ec, 0xffffffff, 0x00070000,
- 
 
 578 
	0x9148, 0xffff0000, 0xff000000,
- 
 
 579 
	0x9190, 0xffffffff, 0x00090008,
- 
 
 580 
	0x91ac, 0xffffffff, 0x00090008,
- 
 
 581 
	0x91c8, 0xffffffff, 0x00090008,
- 
 
 582 
	0x91e4, 0xffffffff, 0x00090008,
- 
 
 583 
	0x9204, 0xffffffff, 0x00090008,
- 
 
 584 
	0x3f94, 0xffff0000, 0xff000000,
- 
 
 585 
	0x914c, 0xffff0000, 0xff000000,
- 
 
 586 
	0x929c, 0xffffffff, 0x00000001,
- 
 
 587 
	0x8a18, 0xffffffff, 0x00000100,
- 
 
 588 
	0x8b28, 0xffffffff, 0x00000100,
- 
 
 589 
	0x9144, 0xffffffff, 0x00000100,
- 
 
 590 
	0x5644, 0xffffffff, 0x00000100,
- 
 
 591 
	0x9b7c, 0xffffffff, 0x00000000,
- 
 
 592 
	0x8030, 0xffffffff, 0x0000100a,
- 
 
 593 
	0x8a14, 0xffffffff, 0x00000007,
- 
 
 594 
	0x8b24, 0xffffffff, 0x00ff0fff,
- 
 
 595 
	0x8b10, 0xffffffff, 0x00000000,
- 
 
 596 
	0x28a4c, 0x06000000, 0x06000000,
- 
 
 597 
	0x4d8, 0xffffffff, 0x00000100,
- 
 
 598 
	0x913c, 0xffff000f, 0x0100000a,
- 
 
 599 
	0x960c, 0xffffffff, 0x54763210,
- 
 
 600 
	0x88c4, 0xffffffff, 0x000000c2,
- 
 
 601 
	0x88d4, 0xffffffff, 0x00000010,
- 
 
 602 
	0x8974, 0xffffffff, 0x00000000,
- 
 
 603 
	0xc78, 0x00000080, 0x00000080,
- 
 
 604 
	0x5e78, 0xffffffff, 0x001000f0,
- 
 
 605 
	0xd02c, 0xffffffff, 0x08421000,
- 
 
 606 
	0xa008, 0xffffffff, 0x00010000,
- 
 
 607 
	0x8d00, 0xffffffff, 0x100e4848,
- 
 
 608 
	0x8d04, 0xffffffff, 0x00164745,
- 
 
 609 
	0x8c00, 0xffffffff, 0xe4000003,
- 
 
 610 
	0x8cf0, 0x1fffffff, 0x08e00620,
- 
 
 611 
	0x28350, 0xffffffff, 0x00000000,
- 
 
 612 
	0x9508, 0xffffffff, 0x00000002
- 
 
 613 
};
- 
 
 614 
 
- 
 
 615 
static const u32 sumo_golden_registers[] =
- 
 
 616 
{
- 
 
 617 
	0x900c, 0x00ffffff, 0x0017071f,
- 
 
 618 
	0x8c18, 0xffffffff, 0x10101060,
- 
 
 619 
	0x8c1c, 0xffffffff, 0x00001010,
- 
 
 620 
	0x8c30, 0x0000000f, 0x00000005,
- 
 
 621 
	0x9688, 0x0000000f, 0x00000007
- 
 
 622 
};
- 
 
 623 
 
- 
 
 624 
static const u32 wrestler_golden_registers[] =
- 
 
 625 
{
- 
 
 626 
	0x5eb4, 0xffffffff, 0x00000002,
- 
 
 627 
	0x5cc, 0xffffffff, 0x00000001,
- 
 
 628 
	0x7030, 0xffffffff, 0x00000011,
- 
 
 629 
	0x7c30, 0xffffffff, 0x00000011,
- 
 
 630 
	0x6104, 0x01000300, 0x00000000,
- 
 
 631 
	0x5bc0, 0x00300000, 0x00000000,
- 
 
 632 
	0x918c, 0xffffffff, 0x00010006,
- 
 
 633 
	0x91a8, 0xffffffff, 0x00010006,
- 
 
 634 
	0x9150, 0xffffffff, 0x6e944040,
- 
 
 635 
	0x917c, 0xffffffff, 0x00030002,
- 
 
 636 
	0x9198, 0xffffffff, 0x00030002,
- 
 
 637 
	0x915c, 0xffffffff, 0x00010000,
- 
 
 638 
	0x3f90, 0xffff0000, 0xff000000,
- 
 
 639 
	0x9178, 0xffffffff, 0x00070000,
- 
 
 640 
	0x9194, 0xffffffff, 0x00070000,
- 
 
 641 
	0x9148, 0xffff0000, 0xff000000,
- 
 
 642 
	0x9190, 0xffffffff, 0x00090008,
- 
 
 643 
	0x91ac, 0xffffffff, 0x00090008,
- 
 
 644 
	0x3f94, 0xffff0000, 0xff000000,
- 
 
 645 
	0x914c, 0xffff0000, 0xff000000,
- 
 
 646 
	0x929c, 0xffffffff, 0x00000001,
- 
 
 647 
	0x8a18, 0xffffffff, 0x00000100,
- 
 
 648 
	0x8b28, 0xffffffff, 0x00000100,
- 
 
 649 
	0x9144, 0xffffffff, 0x00000100,
- 
 
 650 
	0x9b7c, 0xffffffff, 0x00000000,
- 
 
 651 
	0x8030, 0xffffffff, 0x0000100a,
- 
 
 652 
	0x8a14, 0xffffffff, 0x00000001,
- 
 
 653 
	0x8b24, 0xffffffff, 0x00ff0fff,
- 
 
 654 
	0x8b10, 0xffffffff, 0x00000000,
- 
 
 655 
	0x28a4c, 0x06000000, 0x06000000,
- 
 
 656 
	0x4d8, 0xffffffff, 0x00000100,
- 
 
 657 
	0x913c, 0xffff000f, 0x0100000a,
- 
 
 658 
	0x960c, 0xffffffff, 0x54763210,
- 
 
 659 
	0x88c4, 0xffffffff, 0x000000c2,
- 
 
 660 
	0x88d4, 0xffffffff, 0x00000010,
- 
 
 661 
	0x8974, 0xffffffff, 0x00000000,
- 
 
 662 
	0xc78, 0x00000080, 0x00000080,
- 
 
 663 
	0x5e78, 0xffffffff, 0x001000f0,
- 
 
 664 
	0xd02c, 0xffffffff, 0x08421000,
- 
 
 665 
	0xa008, 0xffffffff, 0x00010000,
- 
 
 666 
	0x8d00, 0xffffffff, 0x100e4848,
- 
 
 667 
	0x8d04, 0xffffffff, 0x00164745,
- 
 
 668 
	0x8c00, 0xffffffff, 0xe4000003,
- 
 
 669 
	0x8cf0, 0x1fffffff, 0x08e00410,
- 
 
 670 
	0x28350, 0xffffffff, 0x00000000,
- 
 
 671 
	0x9508, 0xffffffff, 0x00000002,
- 
 
 672 
	0x900c, 0xffffffff, 0x0017071f,
- 
 
 673 
	0x8c18, 0xffffffff, 0x10101060,
- 
 
 674 
	0x8c1c, 0xffffffff, 0x00001010
- 
 
 675 
};
- 
 
 676 
 
- 
 
 677 
static const u32 barts_golden_registers[] =
- 
 
 678 
{
- 
 
 679 
	0x5eb4, 0xffffffff, 0x00000002,
- 
 
 680 
	0x5e78, 0x8f311ff1, 0x001000f0,
- 
 
 681 
	0x3f90, 0xffff0000, 0xff000000,
- 
 
 682 
	0x9148, 0xffff0000, 0xff000000,
- 
 
 683 
	0x3f94, 0xffff0000, 0xff000000,
- 
 
 684 
	0x914c, 0xffff0000, 0xff000000,
- 
 
 685 
	0xc78, 0x00000080, 0x00000080,
- 
 
 686 
	0xbd4, 0x70073777, 0x00010001,
- 
 
 687 
	0xd02c, 0xbfffff1f, 0x08421000,
- 
 
 688 
	0xd0b8, 0x03773777, 0x02011003,
- 
 
 689 
	0x5bc0, 0x00200000, 0x50100000,
- 
 
 690 
	0x98f8, 0x33773777, 0x02011003,
- 
 
 691 
	0x98fc, 0xffffffff, 0x76543210,
- 
 
 692 
	0x7030, 0x31000311, 0x00000011,
- 
 
 693 
	0x2f48, 0x00000007, 0x02011003,
- 
 
 694 
	0x6b28, 0x00000010, 0x00000012,
- 
 
 695 
	0x7728, 0x00000010, 0x00000012,
- 
 
 696 
	0x10328, 0x00000010, 0x00000012,
- 
 
 697 
	0x10f28, 0x00000010, 0x00000012,
- 
 
 698 
	0x11b28, 0x00000010, 0x00000012,
- 
 
 699 
	0x12728, 0x00000010, 0x00000012,
- 
 
 700 
	0x240c, 0x000007ff, 0x00000380,
- 
 
 701 
	0x8a14, 0xf000001f, 0x00000007,
- 
 
 702 
	0x8b24, 0x3fff3fff, 0x00ff0fff,
- 
 
 703 
	0x8b10, 0x0000ff0f, 0x00000000,
- 
 
 704 
	0x28a4c, 0x07ffffff, 0x06000000,
- 
 
 705 
	0x10c, 0x00000001, 0x00010003,
- 
 
 706 
	0xa02c, 0xffffffff, 0x0000009b,
- 
 
 707 
	0x913c, 0x0000000f, 0x0100000a,
- 
 
 708 
	0x8d00, 0xffff7f7f, 0x100e4848,
- 
 
 709 
	0x8d04, 0x00ffffff, 0x00164745,
- 
 
 710 
	0x8c00, 0xfffc0003, 0xe4000003,
- 
 
 711 
	0x8c04, 0xf8ff00ff, 0x40600060,
- 
 
 712 
	0x8c08, 0x00ff00ff, 0x001c001c,
- 
 
 713 
	0x8cf0, 0x1fff1fff, 0x08e00620,
- 
 
 714 
	0x8c20, 0x0fff0fff, 0x00800080,
- 
 
 715 
	0x8c24, 0x0fff0fff, 0x00800080,
- 
 
 716 
	0x8c18, 0xffffffff, 0x20202078,
- 
 
 717 
	0x8c1c, 0x0000ffff, 0x00001010,
- 
 
 718 
	0x28350, 0x00000f01, 0x00000000,
- 
 
 719 
	0x9508, 0x3700001f, 0x00000002,
- 
 
 720 
	0x960c, 0xffffffff, 0x54763210,
- 
 
 721 
	0x88c4, 0x001f3ae3, 0x000000c2,
- 
 
 722 
	0x88d4, 0x0000001f, 0x00000010,
- 
 
 723 
	0x8974, 0xffffffff, 0x00000000
- 
 
 724 
};
- 
 
 725 
 
- 
 
 726 
static const u32 turks_golden_registers[] =
- 
 
 727 
{
- 
 
 728 
	0x5eb4, 0xffffffff, 0x00000002,
- 
 
 729 
	0x5e78, 0x8f311ff1, 0x001000f0,
- 
 
 730 
	0x8c8, 0x00003000, 0x00001070,
- 
 
 731 
	0x8cc, 0x000fffff, 0x00040035,
- 
 
 732 
	0x3f90, 0xffff0000, 0xfff00000,
- 
 
 733 
	0x9148, 0xffff0000, 0xfff00000,
- 
 
 734 
	0x3f94, 0xffff0000, 0xfff00000,
- 
 
 735 
	0x914c, 0xffff0000, 0xfff00000,
- 
 
 736 
	0xc78, 0x00000080, 0x00000080,
- 
 
 737 
	0xbd4, 0x00073007, 0x00010002,
- 
 
 738 
	0xd02c, 0xbfffff1f, 0x08421000,
- 
 
 739 
	0xd0b8, 0x03773777, 0x02010002,
- 
 
 740 
	0x5bc0, 0x00200000, 0x50100000,
- 
 
 741 
	0x98f8, 0x33773777, 0x00010002,
- 
 
 742 
	0x98fc, 0xffffffff, 0x33221100,
- 
 
 743 
	0x7030, 0x31000311, 0x00000011,
- 
 
 744 
	0x2f48, 0x33773777, 0x00010002,
- 
 
 745 
	0x6b28, 0x00000010, 0x00000012,
- 
 
 746 
	0x7728, 0x00000010, 0x00000012,
- 
 
 747 
	0x10328, 0x00000010, 0x00000012,
- 
 
 748 
	0x10f28, 0x00000010, 0x00000012,
- 
 
 749 
	0x11b28, 0x00000010, 0x00000012,
- 
 
 750 
	0x12728, 0x00000010, 0x00000012,
- 
 
 751 
	0x240c, 0x000007ff, 0x00000380,
- 
 
 752 
	0x8a14, 0xf000001f, 0x00000007,
- 
 
 753 
	0x8b24, 0x3fff3fff, 0x00ff0fff,
- 
 
 754 
	0x8b10, 0x0000ff0f, 0x00000000,
- 
 
 755 
	0x28a4c, 0x07ffffff, 0x06000000,
- 
 
 756 
	0x10c, 0x00000001, 0x00010003,
- 
 
 757 
	0xa02c, 0xffffffff, 0x0000009b,
- 
 
 758 
	0x913c, 0x0000000f, 0x0100000a,
- 
 
 759 
	0x8d00, 0xffff7f7f, 0x100e4848,
- 
 
 760 
	0x8d04, 0x00ffffff, 0x00164745,
- 
 
 761 
	0x8c00, 0xfffc0003, 0xe4000003,
- 
 
 762 
	0x8c04, 0xf8ff00ff, 0x40600060,
- 
 
 763 
	0x8c08, 0x00ff00ff, 0x001c001c,
- 
 
 764 
	0x8cf0, 0x1fff1fff, 0x08e00410,
- 
 
 765 
	0x8c20, 0x0fff0fff, 0x00800080,
- 
 
 766 
	0x8c24, 0x0fff0fff, 0x00800080,
- 
 
 767 
	0x8c18, 0xffffffff, 0x20202078,
- 
 
 768 
	0x8c1c, 0x0000ffff, 0x00001010,
- 
 
 769 
	0x28350, 0x00000f01, 0x00000000,
- 
 
 770 
	0x9508, 0x3700001f, 0x00000002,
- 
 
 771 
	0x960c, 0xffffffff, 0x54763210,
- 
 
 772 
	0x88c4, 0x001f3ae3, 0x000000c2,
- 
 
 773 
	0x88d4, 0x0000001f, 0x00000010,
- 
 
 774 
	0x8974, 0xffffffff, 0x00000000
- 
 
 775 
};
- 
 
 776 
 
- 
 
 777 
static const u32 caicos_golden_registers[] =
- 
 
 778 
{
- 
 
 779 
	0x5eb4, 0xffffffff, 0x00000002,
- 
 
 780 
	0x5e78, 0x8f311ff1, 0x001000f0,
- 
 
 781 
	0x8c8, 0x00003420, 0x00001450,
- 
 
 782 
	0x8cc, 0x000fffff, 0x00040035,
- 
 
 783 
	0x3f90, 0xffff0000, 0xfffc0000,
- 
 
 784 
	0x9148, 0xffff0000, 0xfffc0000,
- 
 
 785 
	0x3f94, 0xffff0000, 0xfffc0000,
- 
 
 786 
	0x914c, 0xffff0000, 0xfffc0000,
- 
 
 787 
	0xc78, 0x00000080, 0x00000080,
- 
 
 788 
	0xbd4, 0x00073007, 0x00010001,
- 
 
 789 
	0xd02c, 0xbfffff1f, 0x08421000,
- 
 
 790 
	0xd0b8, 0x03773777, 0x02010001,
- 
 
 791 
	0x5bc0, 0x00200000, 0x50100000,
- 
 
 792 
	0x98f8, 0x33773777, 0x02010001,
- 
 
 793 
	0x98fc, 0xffffffff, 0x33221100,
- 
 
 794 
	0x7030, 0x31000311, 0x00000011,
- 
 
 795 
	0x2f48, 0x33773777, 0x02010001,
- 
 
 796 
	0x6b28, 0x00000010, 0x00000012,
- 
 
 797 
	0x7728, 0x00000010, 0x00000012,
- 
 
 798 
	0x10328, 0x00000010, 0x00000012,
- 
 
 799 
	0x10f28, 0x00000010, 0x00000012,
- 
 
 800 
	0x11b28, 0x00000010, 0x00000012,
- 
 
 801 
	0x12728, 0x00000010, 0x00000012,
- 
 
 802 
	0x240c, 0x000007ff, 0x00000380,
- 
 
 803 
	0x8a14, 0xf000001f, 0x00000001,
- 
 
 804 
	0x8b24, 0x3fff3fff, 0x00ff0fff,
- 
 
 805 
	0x8b10, 0x0000ff0f, 0x00000000,
- 
 
 806 
	0x28a4c, 0x07ffffff, 0x06000000,
- 
 
 807 
	0x10c, 0x00000001, 0x00010003,
- 
 
 808 
	0xa02c, 0xffffffff, 0x0000009b,
- 
 
 809 
	0x913c, 0x0000000f, 0x0100000a,
- 
 
 810 
	0x8d00, 0xffff7f7f, 0x100e4848,
- 
 
 811 
	0x8d04, 0x00ffffff, 0x00164745,
- 
 
 812 
	0x8c00, 0xfffc0003, 0xe4000003,
- 
 
 813 
	0x8c04, 0xf8ff00ff, 0x40600060,
- 
 
 814 
	0x8c08, 0x00ff00ff, 0x001c001c,
- 
 
 815 
	0x8cf0, 0x1fff1fff, 0x08e00410,
- 
 
 816 
	0x8c20, 0x0fff0fff, 0x00800080,
- 
 
 817 
	0x8c24, 0x0fff0fff, 0x00800080,
- 
 
 818 
	0x8c18, 0xffffffff, 0x20202078,
- 
 
 819 
	0x8c1c, 0x0000ffff, 0x00001010,
- 
 
 820 
	0x28350, 0x00000f01, 0x00000000,
- 
 
 821 
	0x9508, 0x3700001f, 0x00000002,
- 
 
 822 
	0x960c, 0xffffffff, 0x54763210,
- 
 
 823 
	0x88c4, 0x001f3ae3, 0x000000c2,
- 
 
 824 
	0x88d4, 0x0000001f, 0x00000010,
- 
 
 825 
	0x8974, 0xffffffff, 0x00000000
- 
 
 826 
};
- 
 
 827 
 
- 
 
 828 
static void evergreen_init_golden_registers(struct radeon_device *rdev)
- 
 
 829 
{
- 
 
 830 
	switch (rdev->family) {
- 
 
 831 
	case CHIP_CYPRESS:
- 
 
 832 
	case CHIP_HEMLOCK:
- 
 
 833 
		radeon_program_register_sequence(rdev,
- 
 
 834 
						 evergreen_golden_registers,
- 
 
 835 
						 (const u32)ARRAY_SIZE(evergreen_golden_registers));
- 
 
 836 
		radeon_program_register_sequence(rdev,
- 
 
 837 
						 evergreen_golden_registers2,
- 
 
 838 
						 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
- 
 
 839 
		radeon_program_register_sequence(rdev,
- 
 
 840 
						 cypress_mgcg_init,
- 
 
 841 
						 (const u32)ARRAY_SIZE(cypress_mgcg_init));
- 
 
 842 
		break;
- 
 
 843 
	case CHIP_JUNIPER:
- 
 
 844 
		radeon_program_register_sequence(rdev,
- 
 
 845 
						 evergreen_golden_registers,
- 
 
 846 
						 (const u32)ARRAY_SIZE(evergreen_golden_registers));
- 
 
 847 
		radeon_program_register_sequence(rdev,
- 
 
 848 
						 evergreen_golden_registers2,
- 
 
 849 
						 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
- 
 
 850 
		radeon_program_register_sequence(rdev,
- 
 
 851 
						 juniper_mgcg_init,
- 
 
 852 
						 (const u32)ARRAY_SIZE(juniper_mgcg_init));
- 
 
 853 
		break;
- 
 
 854 
	case CHIP_REDWOOD:
- 
 
 855 
		radeon_program_register_sequence(rdev,
- 
 
 856 
						 evergreen_golden_registers,
- 
 
 857 
						 (const u32)ARRAY_SIZE(evergreen_golden_registers));
- 
 
 858 
		radeon_program_register_sequence(rdev,
- 
 
 859 
						 evergreen_golden_registers2,
- 
 
 860 
						 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
- 
 
 861 
		radeon_program_register_sequence(rdev,
- 
 
 862 
						 redwood_mgcg_init,
- 
 
 863 
						 (const u32)ARRAY_SIZE(redwood_mgcg_init));
- 
 
 864 
		break;
- 
 
 865 
	case CHIP_CEDAR:
- 
 
 866 
		radeon_program_register_sequence(rdev,
- 
 
 867 
						 cedar_golden_registers,
- 
 
 868 
						 (const u32)ARRAY_SIZE(cedar_golden_registers));
- 
 
 869 
		radeon_program_register_sequence(rdev,
- 
 
 870 
						 evergreen_golden_registers2,
- 
 
 871 
						 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
- 
 
 872 
		radeon_program_register_sequence(rdev,
- 
 
 873 
						 cedar_mgcg_init,
- 
 
 874 
						 (const u32)ARRAY_SIZE(cedar_mgcg_init));
- 
 
 875 
		break;
- 
 
 876 
	case CHIP_PALM:
- 
 
 877 
		radeon_program_register_sequence(rdev,
- 
 
 878 
						 wrestler_golden_registers,
- 
 
 879 
						 (const u32)ARRAY_SIZE(wrestler_golden_registers));
- 
 
 880 
		break;
- 
 
 881 
	case CHIP_SUMO:
- 
 
 882 
		radeon_program_register_sequence(rdev,
- 
 
 883 
						 supersumo_golden_registers,
- 
 
 884 
						 (const u32)ARRAY_SIZE(supersumo_golden_registers));
- 
 
 885 
		break;
- 
 
 886 
	case CHIP_SUMO2:
- 
 
 887 
		radeon_program_register_sequence(rdev,
- 
 
 888 
						 supersumo_golden_registers,
- 
 
 889 
						 (const u32)ARRAY_SIZE(supersumo_golden_registers));
- 
 
 890 
		radeon_program_register_sequence(rdev,
- 
 
 891 
						 sumo_golden_registers,
- 
 
 892 
						 (const u32)ARRAY_SIZE(sumo_golden_registers));
- 
 
 893 
		break;
- 
 
 894 
	case CHIP_BARTS:
- 
 
 895 
		radeon_program_register_sequence(rdev,
- 
 
 896 
						 barts_golden_registers,
- 
 
 897 
						 (const u32)ARRAY_SIZE(barts_golden_registers));
- 
 
 898 
		break;
- 
 
 899 
	case CHIP_TURKS:
- 
 
 900 
		radeon_program_register_sequence(rdev,
- 
 
 901 
						 turks_golden_registers,
- 
 
 902 
						 (const u32)ARRAY_SIZE(turks_golden_registers));
- 
 
 903 
		break;
- 
 
 904 
	case CHIP_CAICOS:
- 
 
 905 
		radeon_program_register_sequence(rdev,
- 
 
 906 
						 caicos_golden_registers,
- 
 
 907 
						 (const u32)ARRAY_SIZE(caicos_golden_registers));
- 
 
 908 
		break;
- 
 
 909 
	default:
- 
 
 910 
		break;
- 
 
 911 
	}
- 
 
 912 
}
55 
 
 913 
 
56 
void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 914 
void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
57 
			     unsigned *bankh, unsigned *mtaspect,
 915 
			     unsigned *bankh, unsigned *mtaspect,
58 
			     unsigned *tile_split)
 916 
			     unsigned *tile_split)
59 
{
 917 
{
Line 82... Line 940...
82 
	case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
 940 
	case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
83 
	case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
 941 
	case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
84 
	}
 942 
	}
85 
}
 943 
}
Line -... Line 944...
- 
 
 944 
 
- 
 
 945 
static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,
- 
 
 946 
			      u32 cntl_reg, u32 status_reg)
- 
 
 947 
{
- 
 
 948 
	int r, i;
- 
 
 949 
	struct atom_clock_dividers dividers;
- 
 
 950 
 
- 
 
 951 
        r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
- 
 
 952 
					   clock, false, ÷rs);
- 
 
 953 
	if (r)
- 
 
 954 
		return r;
- 
 
 955 
 
- 
 
 956 
	WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));
- 
 
 957 
 
- 
 
 958 
	for (i = 0; i < 100; i++) {
- 
 
 959 
		if (RREG32(status_reg) & DCLK_STATUS)
- 
 
 960 
			break;
- 
 
 961 
		mdelay(10);
- 
 
 962 
	}
- 
 
 963 
	if (i == 100)
- 
 
 964 
		return -ETIMEDOUT;
- 
 
 965 
 
- 
 
 966 
	return 0;
- 
 
 967 
}
- 
 
 968 
 
- 
 
 969 
int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
- 
 
 970 
{
- 
 
 971 
	int r = 0;
- 
 
 972 
	u32 cg_scratch = RREG32(CG_SCRATCH1);
- 
 
 973 
 
- 
 
 974 
	r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
- 
 
 975 
	if (r)
- 
 
 976 
		goto done;
- 
 
 977 
	cg_scratch &= 0xffff0000;
- 
 
 978 
	cg_scratch |= vclk / 100; /* Mhz */
- 
 
 979 
 
- 
 
 980 
	r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
- 
 
 981 
	if (r)
- 
 
 982 
		goto done;
- 
 
 983 
	cg_scratch &= 0x0000ffff;
- 
 
 984 
	cg_scratch |= (dclk / 100) << 16; /* Mhz */
- 
 
 985 
 
- 
 
 986 
done:
- 
 
 987 
	WREG32(CG_SCRATCH1, cg_scratch);
- 
 
 988 
 
- 
 
 989 
	return r;
- 
 
 990 
}
- 
 
 991 
 
- 
 
 992 
int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
- 
 
 993 
{
- 
 
 994 
	/* start off with something large */
- 
 
 995 
	unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
- 
 
 996 
	int r;
- 
 
 997 
 
- 
 
 998 
	/* bypass vclk and dclk with bclk */
- 
 
 999 
	WREG32_P(CG_UPLL_FUNC_CNTL_2,
- 
 
 1000 
		VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
- 
 
 1001 
		~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
- 
 
 1002 
 
- 
 
 1003 
	/* put PLL in bypass mode */
- 
 
 1004 
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
- 
 
 1005 
 
- 
 
 1006 
	if (!vclk || !dclk) {
- 
 
 1007 
		/* keep the Bypass mode, put PLL to sleep */
- 
 
 1008 
		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
- 
 
 1009 
		return 0;
- 
 
 1010 
	}
- 
 
 1011 
 
- 
 
 1012 
//   r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
- 
 
 1013 
//                     16384, 0x03FFFFFF, 0, 128, 5,
- 
 
 1014 
//                     &fb_div, &vclk_div, &dclk_div);
- 
 
 1015 
	if (r)
- 
 
 1016 
		return r;
- 
 
 1017 
 
- 
 
 1018 
	/* set VCO_MODE to 1 */
- 
 
 1019 
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
- 
 
 1020 
 
- 
 
 1021 
	/* toggle UPLL_SLEEP to 1 then back to 0 */
- 
 
 1022 
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
- 
 
 1023 
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
- 
 
 1024 
 
- 
 
 1025 
	/* deassert UPLL_RESET */
- 
 
 1026 
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
- 
 
 1027 
 
- 
 
 1028 
	mdelay(1);
- 
 
 1029 
 
- 
 
 1030 
//   r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
- 
 
 1031 
//   if (r)
- 
 
 1032 
//       return r;
- 
 
 1033 
 
- 
 
 1034 
	/* assert UPLL_RESET again */
- 
 
 1035 
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
- 
 
 1036 
 
- 
 
 1037 
	/* disable spread spectrum. */
- 
 
 1038 
	WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
- 
 
 1039 
 
- 
 
 1040 
	/* set feedback divider */
- 
 
 1041 
	WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
- 
 
 1042 
 
- 
 
 1043 
	/* set ref divider to 0 */
- 
 
 1044 
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
- 
 
 1045 
 
- 
 
 1046 
	if (fb_div < 307200)
- 
 
 1047 
		WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
- 
 
 1048 
	else
- 
 
 1049 
		WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
- 
 
 1050 
 
- 
 
 1051 
	/* set PDIV_A and PDIV_B */
- 
 
 1052 
	WREG32_P(CG_UPLL_FUNC_CNTL_2,
- 
 
 1053 
		UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
- 
 
 1054 
		~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
- 
 
 1055 
 
- 
 
 1056 
	/* give the PLL some time to settle */
- 
 
 1057 
	mdelay(15);
- 
 
 1058 
 
- 
 
 1059 
	/* deassert PLL_RESET */
- 
 
 1060 
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
- 
 
 1061 
 
- 
 
 1062 
	mdelay(15);
- 
 
 1063 
 
- 
 
 1064 
	/* switch from bypass mode to normal mode */
- 
 
 1065 
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
- 
 
 1066 
 
- 
 
 1067 
//   r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
- 
 
 1068 
//   if (r)
- 
 
 1069 
//       return r;
- 
 
 1070 
 
- 
 
 1071 
	/* switch VCLK and DCLK selection */
- 
 
 1072 
	WREG32_P(CG_UPLL_FUNC_CNTL_2,
- 
 
 1073 
		VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
- 
 
 1074 
		~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
- 
 
 1075 
 
- 
 
 1076 
	mdelay(100);
- 
 
 1077 
 
- 
 
 1078 
	return 0;
- 
 
 1079 
}
86 
 
 1080 
 
87 
void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
 1081 
void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
88 
{
 1082 
{
89 
	u16 ctl, v;
 1083 
	u16 ctl, v;
Line 103... Line 1097...
103 
		ctl |= (2 << 12);
 1097 
		ctl |= (2 << 12);
104 
		pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
 1098 
		pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
105 
	}
 1099 
	}
106 
}
 1100 
}
Line -... Line 1101...
- 
 
 1101 
 
- 
 
 1102 
static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
- 
 
 1103 
{
- 
 
 1104 
	if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
- 
 
 1105 
		return true;
- 
 
 1106 
	else
- 
 
 1107 
		return false;
- 
 
 1108 
}
- 
 
 1109 
 
- 
 
 1110 
static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
- 
 
 1111 
{
- 
 
 1112 
	u32 pos1, pos2;
- 
 
 1113 
 
- 
 
 1114 
	pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
- 
 
 1115 
	pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
- 
 
 1116 
 
- 
 
 1117 
	if (pos1 != pos2)
- 
 
 1118 
		return true;
- 
 
 1119 
	else
- 
 
 1120 
		return false;
- 
 
 1121 
}
107 
 
 1122 
 
108 
/**
 1123 
/**
109 
 * dce4_wait_for_vblank - vblank wait asic callback.
 1124 
 * dce4_wait_for_vblank - vblank wait asic callback.
110 
 *
 1125 
 *
111 
 * @rdev: radeon_device pointer
 1126 
 * @rdev: radeon_device pointer
112 
 * @crtc: crtc to wait for vblank on
 1127 
 * @crtc: crtc to wait for vblank on
113 
 *
 1128 
 *
114 
 * Wait for vblank on the requested crtc (evergreen+).
 1129 
 * Wait for vblank on the requested crtc (evergreen+).
115 
 */
 1130 
 */
116 
void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
 1131 
void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
117 
{
 1132 
{
Line 118... Line 1133...
118 
	int i;
 1133 
	unsigned i = 0;
119 
 
 1134 
 
Line 120... Line 1135...
120 
	if (crtc >= rdev->num_crtc)
 1135 
	if (crtc >= rdev->num_crtc)
- 
 
 1136 
		return;
- 
 
 1137 
 
- 
 
 1138 
	if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
- 
 
 1139 
		return;
- 
 
 1140 
 
121 
		return;
 1141 
	/* depending on when we hit vblank, we may be close to active; if so,
- 
 
 1142 
	 * wait for another frame.
122 
 
 1143 
	 */
123 
	if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
 1144 
	while (dce4_is_in_vblank(rdev, crtc)) {
124 
		for (i = 0; i < rdev->usec_timeout; i++) {
 - 
 
125 
			if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
 1145 
		if (i++ % 100 == 0) {
- 
 
 1146 
			if (!dce4_is_counter_moving(rdev, crtc))
- 
 
 1147 
				break;
126 
				break;
 1148 
		}
- 
 
 1149 
	}
127 
			udelay(1);
 1150 
 
128 
		}
 1151 
	while (!dce4_is_in_vblank(rdev, crtc)) {
129 
		for (i = 0; i < rdev->usec_timeout; i++) {
 - 
 
130 
			if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
 1152 
		if (i++ % 100 == 0) {
131 
				break;
 1153 
			if (!dce4_is_counter_moving(rdev, crtc))
132 
			udelay(1);
 1154 
				break;
Line 291... Line 1313...
291 
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
 1313 
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
292 
		rdev->pm.power_state[idx].num_clock_modes - 1;
 1314 
		rdev->pm.power_state[idx].num_clock_modes - 1;
293 
}
 1315 
}
Line 294... Line 1316...
294 
 
 1316 
 
- 
 
 1317 
/**
- 
 
 1318 
 * btc_pm_init_profile - Initialize power profiles callback.
- 
 
 1319 
 *
- 
 
 1320 
 * @rdev: radeon_device pointer
- 
 
 1321 
 *
- 
 
 1322 
 * Initialize the power states used in profile mode
- 
 
 1323 
 * (BTC, cayman).
- 
 
 1324 
 * Used for profile mode only.
- 
 
 1325 
 */
- 
 
 1326 
void btc_pm_init_profile(struct radeon_device *rdev)
- 
 
 1327 
{
- 
 
 1328 
	int idx;
- 
 
 1329 
 
- 
 
 1330 
	/* default */
- 
 
 1331 
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
- 
 
 1332 
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
- 
 
 1333 
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
- 
 
 1334 
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
- 
 
 1335 
	/* starting with BTC, there is one state that is used for both
- 
 
 1336 
	 * MH and SH.  Difference is that we always use the high clock index for
- 
 
 1337 
	 * mclk.
- 
 
 1338 
	 */
- 
 
 1339 
	if (rdev->flags & RADEON_IS_MOBILITY)
- 
 
 1340 
		idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
- 
 
 1341 
	else
- 
 
 1342 
		idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
- 
 
 1343 
	/* low sh */
- 
 
 1344 
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
- 
 
 1345 
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
- 
 
 1346 
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
- 
 
 1347 
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
- 
 
 1348 
	/* mid sh */
- 
 
 1349 
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
- 
 
 1350 
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
- 
 
 1351 
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
- 
 
 1352 
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
- 
 
 1353 
	/* high sh */
- 
 
 1354 
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
- 
 
 1355 
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
- 
 
 1356 
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
- 
 
 1357 
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
- 
 
 1358 
	/* low mh */
- 
 
 1359 
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
- 
 
 1360 
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
- 
 
 1361 
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
- 
 
 1362 
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
- 
 
 1363 
	/* mid mh */
- 
 
 1364 
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
- 
 
 1365 
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
- 
 
 1366 
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
- 
 
 1367 
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
- 
 
 1368 
	/* high mh */
- 
 
 1369 
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
- 
 
 1370 
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
- 
 
 1371 
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
- 
 
 1372 
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
- 
 
 1373 
}
- 
 
 1374 
 
295 
/**
 1375 
/**
296 
 * evergreen_pm_misc - set additional pm hw parameters callback.
 1376 
 * evergreen_pm_misc - set additional pm hw parameters callback.
297 
 *
 1377 
 *
298 
 * @rdev: radeon_device pointer
 1378 
 * @rdev: radeon_device pointer
299 
 *
 1379 
 *
Line 314... Line 1394...
314 
		if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 1394 
		if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
315 
			radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 1395 
			radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
316 
			rdev->pm.current_vddc = voltage->voltage;
 1396 
			rdev->pm.current_vddc = voltage->voltage;
317 
			DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 1397 
			DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
318 
		}
 1398 
		}
- 
 
 1399 
 
- 
 
 1400 
		/* starting with BTC, there is one state that is used for both
- 
 
 1401 
		 * MH and SH.  Difference is that we always use the high clock index for
- 
 
 1402 
		 * mclk and vddci.
- 
 
 1403 
		 */
- 
 
 1404 
		if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
- 
 
 1405 
		    (rdev->family >= CHIP_BARTS) &&
- 
 
 1406 
		    rdev->pm.active_crtc_count &&
- 
 
 1407 
		    ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
- 
 
 1408 
		     (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
- 
 
 1409 
			voltage = &rdev->pm.power_state[req_ps_idx].
- 
 
 1410 
				clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;
- 
 
 1411 
 
319 
		/* 0xff01 is a flag rather then an actual voltage */
 1412 
		/* 0xff01 is a flag rather then an actual voltage */
320 
		if (voltage->vddci == 0xff01)
 1413 
		if (voltage->vddci == 0xff01)
321 
			return;
 1414 
			return;
322 
		if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 1415 
		if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
323 
			radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 1416 
			radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
Line 506... Line 1599...
506 
	u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 1599 
	u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
507 
		DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 1600 
		DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
Line 508... Line 1601...
508 
 
 1601 
 
509 
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 1602 
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
- 
 
 1603 
		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
- 
 
 1604 
 
- 
 
 1605 
		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
- 
 
 1606 
		    connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
- 
 
 1607 
			/* don't try to enable hpd on eDP or LVDS avoid breaking the
- 
 
 1608 
			 * aux dp channel on imac and help (but not completely fix)
- 
 
 1609 
			 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
- 
 
 1610 
			 * also avoid interrupt storms during dpms.
- 
 
 1611 
			 */
- 
 
 1612 
			continue;
510 
		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 1613 
		}
511 
		switch (radeon_connector->hpd.hpd) {
 1614 
		switch (radeon_connector->hpd.hpd) {
512 
		case RADEON_HPD_1:
 1615 
		case RADEON_HPD_1:
513 
			WREG32(DC_HPD1_CONTROL, tmp);
 1616 
			WREG32(DC_HPD1_CONTROL, tmp);
514 
			break;
 1617 
			break;
Line 1209... Line 2312...
1209 
void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
 2312 
void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1210 
{
 2313 
{
1211 
	u32 crtc_enabled, tmp, frame_count, blackout;
 2314 
	u32 crtc_enabled, tmp, frame_count, blackout;
1212 
	int i, j;
 2315 
	int i, j;
Line -... Line 2316...
- 
 
 2316 
 
1213 
 
 2317 
	if (!ASIC_IS_NODCE(rdev)) {
1214 
	save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
 2318 
	save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
Line 1215... Line 2319...
1215 
	save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 2319 
	save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1216 
 
 2320 
 
- 
 
 2321 
	/* disable VGA render */
1217 
	/* disable VGA render */
 2322 
	WREG32(VGA_RENDER_CONTROL, 0);
1218 
	WREG32(VGA_RENDER_CONTROL, 0);
 2323 
	}
1219 
	/* blank the display controllers */
 2324 
	/* blank the display controllers */
1220 
	for (i = 0; i < rdev->num_crtc; i++) {
 2325 
	for (i = 0; i < rdev->num_crtc; i++) {
1221 
		crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
 2326 
		crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1222 
		if (crtc_enabled) {
 2327 
		if (crtc_enabled) {
1223 
			save->crtc_enabled[i] = true;
 2328 
			save->crtc_enabled[i] = true;
1224 
			if (ASIC_IS_DCE6(rdev)) {
 2329 
			if (ASIC_IS_DCE6(rdev)) {
1225 
				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
 2330 
				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
- 
 
 2331 
				if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1226 
				if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
 2332 
					radeon_wait_for_vblank(rdev, i);
1227 
					radeon_wait_for_vblank(rdev, i);
 2333 
					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1228 
					tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
 2334 
					tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1229 
					WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 2335 
					WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1230 
				}
 2336 
				}
1231 
			} else {
 2337 
			} else {
1232 
				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
 2338 
				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
- 
 
 2339 
				if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1233 
				if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
 2340 
					radeon_wait_for_vblank(rdev, i);
1234 
					radeon_wait_for_vblank(rdev, i);
 2341 
					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
- 
 
 2342 
					tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1235 
					tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 2343 
					WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1236 
					WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
 2344 
					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1237 
				}
 2345 
				}
1238 
			}
 2346 
			}
1239 
			/* wait for the next frame */
 2347 
			/* wait for the next frame */
1240 
			frame_count = radeon_get_vblank_counter(rdev, i);
 2348 
			frame_count = radeon_get_vblank_counter(rdev, i);
1241 
			for (j = 0; j < rdev->usec_timeout; j++) {
 2349 
			for (j = 0; j < rdev->usec_timeout; j++) {
1242 
				if (radeon_get_vblank_counter(rdev, i) != frame_count)
 2350 
				if (radeon_get_vblank_counter(rdev, i) != frame_count)
1243 
					break;
 2351 
					break;
- 
 
 2352 
				udelay(1);
- 
 
 2353 
			}
- 
 
 2354 
 
- 
 
 2355 
			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
- 
 
 2356 
			WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
- 
 
 2357 
			tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
- 
 
 2358 
			tmp &= ~EVERGREEN_CRTC_MASTER_EN;
- 
 
 2359 
			WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
- 
 
 2360 
			WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1244 
				udelay(1);
 2361 
			save->crtc_enabled[i] = false;
1245 
			}
 2362 
			/* ***** */
1246 
		} else {
 2363 
		} else {
1247 
			save->crtc_enabled[i] = false;
 2364 
			save->crtc_enabled[i] = false;
Line 1256... Line 2373...
1256 
		WREG32(BIF_FB_EN, 0);
 2373 
		WREG32(BIF_FB_EN, 0);
1257 
		/* blackout the MC */
 2374 
		/* blackout the MC */
1258 
		blackout &= ~BLACKOUT_MODE_MASK;
 2375 
		blackout &= ~BLACKOUT_MODE_MASK;
1259 
		WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
 2376 
		WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1260 
	}
 2377 
	}
- 
 
 2378 
	/* wait for the MC to settle */
- 
 
 2379 
	udelay(100);
- 
 
 2380 
 
- 
 
 2381 
	/* lock double buffered regs */
- 
 
 2382 
	for (i = 0; i < rdev->num_crtc; i++) {
- 
 
 2383 
		if (save->crtc_enabled[i]) {
- 
 
 2384 
			tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
- 
 
 2385 
			if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
- 
 
 2386 
				tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
- 
 
 2387 
				WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
- 
 
 2388 
			}
- 
 
 2389 
			tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
- 
 
 2390 
			if (!(tmp & 1)) {
- 
 
 2391 
				tmp |= 1;
- 
 
 2392 
				WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
- 
 
 2393 
			}
- 
 
 2394 
		}
- 
 
 2395 
	}
1261 
}
 2396 
}
Line 1262... Line 2397...
1262 
 
 2397 
 
1263 
void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
 2398 
void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1264 
{
 2399 
{
Line 1274... Line 2409...
1274 
		WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 2409 
		WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
1275 
		       (u32)rdev->mc.vram_start);
 2410 
		       (u32)rdev->mc.vram_start);
1276 
		WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 2411 
		WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
1277 
		       (u32)rdev->mc.vram_start);
 2412 
		       (u32)rdev->mc.vram_start);
1278 
	}
 2413 
	}
- 
 
 2414 
 
- 
 
 2415 
	if (!ASIC_IS_NODCE(rdev)) {
1279 
	WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
 2416 
	WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1280 
	WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
 2417 
	WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
- 
 
 2418 
	}
- 
 
 2419 
 
- 
 
 2420 
	/* unlock regs and wait for update */
- 
 
 2421 
	for (i = 0; i < rdev->num_crtc; i++) {
- 
 
 2422 
		if (save->crtc_enabled[i]) {
- 
 
 2423 
			tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
- 
 
 2424 
			if ((tmp & 0x3) != 0) {
- 
 
 2425 
				tmp &= ~0x3;
- 
 
 2426 
				WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
- 
 
 2427 
			}
- 
 
 2428 
			tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
- 
 
 2429 
			if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
- 
 
 2430 
				tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
- 
 
 2431 
				WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
- 
 
 2432 
			}
- 
 
 2433 
			tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
- 
 
 2434 
			if (tmp & 1) {
- 
 
 2435 
				tmp &= ~1;
- 
 
 2436 
				WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
- 
 
 2437 
			}
- 
 
 2438 
			for (j = 0; j < rdev->usec_timeout; j++) {
- 
 
 2439 
				tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
- 
 
 2440 
				if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
- 
 
 2441 
					break;
- 
 
 2442 
				udelay(1);
- 
 
 2443 
			}
- 
 
 2444 
		}
- 
 
 2445 
	}
Line 1281... Line 2446...
1281 
 
 2446 
 
1282 
	/* unblackout the MC */
 2447 
	/* unblackout the MC */
1283 
	tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
 2448 
	tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1284 
	tmp &= ~BLACKOUT_MODE_MASK;
 2449 
	tmp &= ~BLACKOUT_MODE_MASK;
Line 1289... Line 2454...
1289 
	for (i = 0; i < rdev->num_crtc; i++) {
 2454 
	for (i = 0; i < rdev->num_crtc; i++) {
1290 
		if (save->crtc_enabled[i]) {
 2455 
		if (save->crtc_enabled[i]) {
1291 
			if (ASIC_IS_DCE6(rdev)) {
 2456 
			if (ASIC_IS_DCE6(rdev)) {
1292 
				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
 2457 
				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1293 
				tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
 2458 
				tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
- 
 
 2459 
				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1294 
				WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 2460 
				WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
- 
 
 2461 
				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1295 
			} else {
 2462 
			} else {
1296 
				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
 2463 
				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1297 
				tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 2464 
				tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
- 
 
 2465 
				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1298 
				WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
 2466 
				WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
- 
 
 2467 
				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1299 
			}
 2468 
			}
1300 
			/* wait for the next frame */
 2469 
			/* wait for the next frame */
1301 
			frame_count = radeon_get_vblank_counter(rdev, i);
 2470 
			frame_count = radeon_get_vblank_counter(rdev, i);
1302 
			for (j = 0; j < rdev->usec_timeout; j++) {
 2471 
			for (j = 0; j < rdev->usec_timeout; j++) {
1303 
				if (radeon_get_vblank_counter(rdev, i) != frame_count)
 2472 
				if (radeon_get_vblank_counter(rdev, i) != frame_count)
1304 
					break;
 2473 
					break;
1305 
				udelay(1);
 2474 
				udelay(1);
1306 
			}
 2475 
			}
1307 
		}
 2476 
		}
1308 
	}
 2477 
	}
- 
 
 2478 
	if (!ASIC_IS_NODCE(rdev)) {
1309 
	/* Unlock vga access */
 2479 
	/* Unlock vga access */
1310 
	WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
 2480 
	WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1311 
	mdelay(1);
 2481 
	mdelay(1);
1312 
	WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
 2482 
	WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1313 
}
 2483 
	}
- 
 
 2484 
}
Line 1314... Line 2485...
1314 
 
 2485 
 
1315 
void evergreen_mc_program(struct radeon_device *rdev)
 2486 
void evergreen_mc_program(struct radeon_device *rdev)
1316 
{
 2487 
{
1317 
	struct evergreen_mc_save save;
 2488 
	struct evergreen_mc_save save;
Line 1938... Line 3109...
1938 
			tmp |= rb_disable_bitmap;
 3109 
			tmp |= rb_disable_bitmap;
1939 
		}
 3110 
		}
1940 
	}
 3111 
	}
1941 
	/* enabled rb are just the one not disabled :) */
 3112 
	/* enabled rb are just the one not disabled :) */
1942 
	disabled_rb_mask = tmp;
 3113 
	disabled_rb_mask = tmp;
- 
 
 3114 
	tmp = 0;
- 
 
 3115 
	for (i = 0; i < rdev->config.evergreen.max_backends; i++)
- 
 
 3116 
		tmp |= (1 << i);
- 
 
 3117 
	/* if all the backends are disabled, fix it up here */
- 
 
 3118 
	if ((disabled_rb_mask & tmp) == tmp) {
- 
 
 3119 
		for (i = 0; i < rdev->config.evergreen.max_backends; i++)
- 
 
 3120 
			disabled_rb_mask &= ~(1 << i);
- 
 
 3121 
	}
Line 1943... Line 3122...
1943 
 
 3122 
 
1944 
	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
 3123 
	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
Line 1945... Line 3124...
1945 
	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
 3124 
	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1946 
 
 3125 
 
1947 
	WREG32(GB_ADDR_CONFIG, gb_addr_config);
 3126 
	WREG32(GB_ADDR_CONFIG, gb_addr_config);
1948 
	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
 3127 
	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
- 
 
 3128 
	WREG32(HDP_ADDR_CONFIG, gb_addr_config);
- 
 
 3129 
	WREG32(DMA_TILING_CONFIG, gb_addr_config);
- 
 
 3130 
	WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1949 
	WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 3131 
	WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
- 
 
 3132 
	WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
- 
 
 3133 
 
- 
 
 3134 
	if ((rdev->config.evergreen.max_backends == 1) &&
- 
 
 3135 
	    (rdev->flags & RADEON_IS_IGP)) {
- 
 
 3136 
		if ((disabled_rb_mask & 3) == 1) {
- 
 
 3137 
			/* RB0 disabled, RB1 enabled */
- 
 
 3138 
			tmp = 0x11111111;
- 
 
 3139 
		} else {
- 
 
 3140 
			/* RB1 disabled, RB0 enabled */
- 
 
 3141 
			tmp = 0x00000000;
1950 
	WREG32(DMA_TILING_CONFIG, gb_addr_config);
 3142 
		}
1951 
 
 3143 
	} else {
1952 
	tmp = gb_addr_config & NUM_PIPES_MASK;
 3144 
	tmp = gb_addr_config & NUM_PIPES_MASK;
- 
 
 3145 
	tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
1953 
	tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
 3146 
					EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
Line 1954... Line 3147...
1954 
					EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
 3147 
	}
1955 
	WREG32(GB_BACKEND_MAP, tmp);
 3148 
	WREG32(GB_BACKEND_MAP, tmp);
1956 
 
 3149 
 
Line 2188... Line 3381...
2188 
		/* size in bytes on fusion */
 3381 
		/* size in bytes on fusion */
2189 
		rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 3382 
		rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2190 
		rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 3383 
		rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2191 
	} else {
 3384 
	} else {
2192 
		/* size in MB on evergreen/cayman/tn */
 3385 
		/* size in MB on evergreen/cayman/tn */
2193 
		rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
 3386 
		rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
2194 
		rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
 3387 
		rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
2195 
	}
 3388 
	}
2196 
	rdev->mc.visible_vram_size = rdev->mc.aper_size;
 3389 
	rdev->mc.visible_vram_size = rdev->mc.aper_size;
2197 
	r700_vram_gtt_location(rdev, &rdev->mc);
 3390 
	r700_vram_gtt_location(rdev, &rdev->mc);
2198 
	radeon_update_bandwidth_info(rdev);
 3391 
	radeon_update_bandwidth_info(rdev);
Line 2199... Line 3392...
2199 
 
 3392 
 
2200 
	return 0;
 3393 
	return 0;
Line 2201... Line 3394...
2201 
}
 3394 
}
2202 
 
 3395 
 
2203 
bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
 - 
 
2204 
{
 - 
 
2205 
	u32 srbm_status;
 - 
 
2206 
	u32 grbm_status;
 - 
 
2207 
	u32 grbm_status_se0, grbm_status_se1;
 - 
 
2208 
 
 - 
 
2209 
	srbm_status = RREG32(SRBM_STATUS);
 - 
 
2210 
	grbm_status = RREG32(GRBM_STATUS);
 - 
 
2211 
	grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
 - 
 
2212 
	grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
 - 
 
2213 
	if (!(grbm_status & GUI_ACTIVE)) {
 - 
 
2214 
		radeon_ring_lockup_update(ring);
 - 
 
2215 
		return false;
 - 
 
2216 
	}
 - 
 
2217 
	/* force CP activities */
 - 
 
2218 
	radeon_ring_force_activity(rdev, ring);
 - 
 
2219 
	return radeon_ring_test_lockup(rdev, ring);
 - 
 
2220 
}
 - 
 
2221 
 
 - 
 
2222 
static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
 - 
 
2223 
{
 - 
 
2224 
	struct evergreen_mc_save save;
 - 
 
2225 
	u32 grbm_reset = 0;
 - 
 
2226 
 
 - 
 
2227 
	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
 - 
 
2228 
		return 0;
 - 
 
2229 
 
 3396 
void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
2230 
	dev_info(rdev->dev, "GPU softreset \n");
 3397 
{
2231 
	dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
 3398 
	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
2232 
		RREG32(GRBM_STATUS));
 3399 
		RREG32(GRBM_STATUS));
2233 
	dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
 3400 
	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
2234 
		RREG32(GRBM_STATUS_SE0));
 3401 
		RREG32(GRBM_STATUS_SE0));
2235 
	dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
 3402 
	dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
2236 
		RREG32(GRBM_STATUS_SE1));
 3403 
		RREG32(GRBM_STATUS_SE1));
- 
 
 3404 
	dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
- 
 
 3405 
		RREG32(SRBM_STATUS));
2237 
	dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
 3406 
	dev_info(rdev->dev, "  SRBM_STATUS2              = 0x%08X\n",
2238 
		RREG32(SRBM_STATUS));
 3407 
		RREG32(SRBM_STATUS2));
2239 
	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
 3408 
	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2240 
		RREG32(CP_STALLED_STAT1));
 3409 
		RREG32(CP_STALLED_STAT1));
2241 
	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
 3410 
	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2242 
		RREG32(CP_STALLED_STAT2));
 3411 
		RREG32(CP_STALLED_STAT2));
2243 
	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
 3412 
	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
2244 
		RREG32(CP_BUSY_STAT));
 3413 
		RREG32(CP_BUSY_STAT));
- 
 
 3414 
	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
- 
 
 3415 
		RREG32(CP_STAT));
- 
 
 3416 
	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
- 
 
 3417 
		RREG32(DMA_STATUS_REG));
- 
 
 3418 
	if (rdev->family >= CHIP_CAYMAN) {
- 
 
 3419 
		dev_info(rdev->dev, "  R_00D834_DMA_STATUS_REG   = 0x%08X\n",
- 
 
 3420 
			 RREG32(DMA_STATUS_REG + 0x800));
- 
 
 3421 
	}
- 
 
 3422 
}
- 
 
 3423 
 
- 
 
 3424 
bool evergreen_is_display_hung(struct radeon_device *rdev)
- 
 
 3425 
{
- 
 
 3426 
	u32 crtc_hung = 0;
- 
 
 3427 
	u32 crtc_status[6];
- 
 
 3428 
	u32 i, j, tmp;
- 
 
 3429 
 
- 
 
 3430 
	for (i = 0; i < rdev->num_crtc; i++) {
- 
 
 3431 
		if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
- 
 
 3432 
			crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
- 
 
 3433 
			crtc_hung |= (1 << i);
- 
 
 3434 
		}
- 
 
 3435 
	}
- 
 
 3436 
 
- 
 
 3437 
	for (j = 0; j < 10; j++) {
- 
 
 3438 
		for (i = 0; i < rdev->num_crtc; i++) {
- 
 
 3439 
			if (crtc_hung & (1 << i)) {
- 
 
 3440 
				tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
- 
 
 3441 
				if (tmp != crtc_status[i])
- 
 
 3442 
					crtc_hung &= ~(1 << i);
- 
 
 3443 
			}
- 
 
 3444 
		}
- 
 
 3445 
		if (crtc_hung == 0)
- 
 
 3446 
			return false;
- 
 
 3447 
		udelay(100);
- 
 
 3448 
	}
- 
 
 3449 
 
- 
 
 3450 
	return true;
- 
 
 3451 
}
- 
 
 3452 
 
- 
 
 3453 
static u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)
- 
 
 3454 
{
- 
 
 3455 
	u32 reset_mask = 0;
- 
 
 3456 
	u32 tmp;
- 
 
 3457 
 
- 
 
 3458 
	/* GRBM_STATUS */
- 
 
 3459 
	tmp = RREG32(GRBM_STATUS);
- 
 
 3460 
	if (tmp & (PA_BUSY | SC_BUSY |
- 
 
 3461 
		   SH_BUSY | SX_BUSY |
- 
 
 3462 
		   TA_BUSY | VGT_BUSY |
- 
 
 3463 
		   DB_BUSY | CB_BUSY |
- 
 
 3464 
		   SPI_BUSY | VGT_BUSY_NO_DMA))
- 
 
 3465 
		reset_mask |= RADEON_RESET_GFX;
- 
 
 3466 
 
- 
 
 3467 
	if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
- 
 
 3468 
		   CP_BUSY | CP_COHERENCY_BUSY))
- 
 
 3469 
		reset_mask |= RADEON_RESET_CP;
- 
 
 3470 
 
- 
 
 3471 
	if (tmp & GRBM_EE_BUSY)
- 
 
 3472 
		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
- 
 
 3473 
 
- 
 
 3474 
	/* DMA_STATUS_REG */
- 
 
 3475 
	tmp = RREG32(DMA_STATUS_REG);
- 
 
 3476 
	if (!(tmp & DMA_IDLE))
- 
 
 3477 
		reset_mask |= RADEON_RESET_DMA;
- 
 
 3478 
 
- 
 
 3479 
	/* SRBM_STATUS2 */
- 
 
 3480 
	tmp = RREG32(SRBM_STATUS2);
- 
 
 3481 
	if (tmp & DMA_BUSY)
- 
 
 3482 
		reset_mask |= RADEON_RESET_DMA;
- 
 
 3483 
 
- 
 
 3484 
	/* SRBM_STATUS */
- 
 
 3485 
	tmp = RREG32(SRBM_STATUS);
- 
 
 3486 
	if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
- 
 
 3487 
		reset_mask |= RADEON_RESET_RLC;
- 
 
 3488 
 
- 
 
 3489 
	if (tmp & IH_BUSY)
- 
 
 3490 
		reset_mask |= RADEON_RESET_IH;
- 
 
 3491 
 
- 
 
 3492 
	if (tmp & SEM_BUSY)
- 
 
 3493 
		reset_mask |= RADEON_RESET_SEM;
- 
 
 3494 
 
- 
 
 3495 
	if (tmp & GRBM_RQ_PENDING)
- 
 
 3496 
		reset_mask |= RADEON_RESET_GRBM;
- 
 
 3497 
 
- 
 
 3498 
	if (tmp & VMC_BUSY)
- 
 
 3499 
		reset_mask |= RADEON_RESET_VMC;
- 
 
 3500 
 
- 
 
 3501 
	if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
- 
 
 3502 
		   MCC_BUSY | MCD_BUSY))
- 
 
 3503 
		reset_mask |= RADEON_RESET_MC;
- 
 
 3504 
 
- 
 
 3505 
	if (evergreen_is_display_hung(rdev))
- 
 
 3506 
		reset_mask |= RADEON_RESET_DISPLAY;
- 
 
 3507 
 
- 
 
 3508 
	/* VM_L2_STATUS */
- 
 
 3509 
	tmp = RREG32(VM_L2_STATUS);
- 
 
 3510 
	if (tmp & L2_BUSY)
- 
 
 3511 
		reset_mask |= RADEON_RESET_VMC;
- 
 
 3512 
 
- 
 
 3513 
	/* Skip MC reset as it's mostly likely not hung, just busy */
- 
 
 3514 
	if (reset_mask & RADEON_RESET_MC) {
- 
 
 3515 
		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
- 
 
 3516 
		reset_mask &= ~RADEON_RESET_MC;
- 
 
 3517 
	}
- 
 
 3518 
 
- 
 
 3519 
	return reset_mask;
- 
 
 3520 
}
- 
 
 3521 
 
- 
 
 3522 
static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
- 
 
 3523 
{
- 
 
 3524 
	struct evergreen_mc_save save;
- 
 
 3525 
	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
- 
 
 3526 
	u32 tmp;
- 
 
 3527 
 
- 
 
 3528 
	if (reset_mask == 0)
- 
 
 3529 
		return;
- 
 
 3530 
 
- 
 
 3531 
	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
- 
 
 3532 
 
- 
 
 3533 
	evergreen_print_gpu_status_regs(rdev);
- 
 
 3534 
 
- 
 
 3535 
	/* Disable CP parsing/prefetching */
- 
 
 3536 
	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
- 
 
 3537 
 
- 
 
 3538 
	if (reset_mask & RADEON_RESET_DMA) {
- 
 
 3539 
	/* Disable DMA */
- 
 
 3540 
	tmp = RREG32(DMA_RB_CNTL);
- 
 
 3541 
	tmp &= ~DMA_RB_ENABLE;
- 
 
 3542 
	WREG32(DMA_RB_CNTL, tmp);
- 
 
 3543 
	}
- 
 
 3544 
 
2245 
	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
 3545 
	udelay(50);
2246 
		RREG32(CP_STAT));
 3546 
 
2247 
	evergreen_mc_stop(rdev, &save);
 3547 
	evergreen_mc_stop(rdev, &save);
2248 
	if (evergreen_mc_wait_for_idle(rdev)) {
 3548 
	if (evergreen_mc_wait_for_idle(rdev)) {
2249 
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 - 
 
2250 
	}
 - 
 
Line 2251... Line 3549...
2251 
	/* Disable CP parsing/prefetching */
 3549 
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2252 
	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
 3550 
	}
2253 
 
 3551 
 
2254 
	/* reset all the gfx blocks */
 - 
 
2255 
	grbm_reset = (SOFT_RESET_CP |
 3552 
	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
2256 
		      SOFT_RESET_CB |
 3553 
		grbm_soft_reset |= SOFT_RESET_DB |
2257 
		      SOFT_RESET_DB |
 3554 
			SOFT_RESET_CB |
2258 
		      SOFT_RESET_PA |
 - 
 
2259 
		      SOFT_RESET_SC |
 3555 
			SOFT_RESET_PA |
- 
 
 3556 
			SOFT_RESET_SC |
2260 
		      SOFT_RESET_SPI |
 3557 
			SOFT_RESET_SPI |
2261 
		      SOFT_RESET_SH |
 3558 
			SOFT_RESET_SX |
2262 
		      SOFT_RESET_SX |
 3559 
			SOFT_RESET_SH |
2263 
		      SOFT_RESET_TC |
 3560 
			SOFT_RESET_TC |
- 
 
 3561 
			SOFT_RESET_TA |
- 
 
 3562 
			SOFT_RESET_VC |
- 
 
 3563 
			SOFT_RESET_VGT;
- 
 
 3564 
	}
- 
 
 3565 
 
- 
 
 3566 
	if (reset_mask & RADEON_RESET_CP) {
- 
 
 3567 
		grbm_soft_reset |= SOFT_RESET_CP |
- 
 
 3568 
			SOFT_RESET_VGT;
- 
 
 3569 
 
- 
 
 3570 
		srbm_soft_reset |= SOFT_RESET_GRBM;
- 
 
 3571 
	}
- 
 
 3572 
 
- 
 
 3573 
	if (reset_mask & RADEON_RESET_DMA)
- 
 
 3574 
		srbm_soft_reset |= SOFT_RESET_DMA;
- 
 
 3575 
 
- 
 
 3576 
	if (reset_mask & RADEON_RESET_DISPLAY)
- 
 
 3577 
		srbm_soft_reset |= SOFT_RESET_DC;
- 
 
 3578 
 
- 
 
 3579 
	if (reset_mask & RADEON_RESET_RLC)
- 
 
 3580 
		srbm_soft_reset |= SOFT_RESET_RLC;
- 
 
 3581 
 
- 
 
 3582 
	if (reset_mask & RADEON_RESET_SEM)
- 
 
 3583 
		srbm_soft_reset |= SOFT_RESET_SEM;
- 
 
 3584 
 
- 
 
 3585 
	if (reset_mask & RADEON_RESET_IH)
- 
 
 3586 
		srbm_soft_reset |= SOFT_RESET_IH;
- 
 
 3587 
 
- 
 
 3588 
	if (reset_mask & RADEON_RESET_GRBM)
- 
 
 3589 
		srbm_soft_reset |= SOFT_RESET_GRBM;
- 
 
 3590 
 
- 
 
 3591 
	if (reset_mask & RADEON_RESET_VMC)
- 
 
 3592 
		srbm_soft_reset |= SOFT_RESET_VMC;
- 
 
 3593 
 
- 
 
 3594 
	if (!(rdev->flags & RADEON_IS_IGP)) {
- 
 
 3595 
		if (reset_mask & RADEON_RESET_MC)
- 
 
 3596 
			srbm_soft_reset |= SOFT_RESET_MC;
- 
 
 3597 
	}
- 
 
 3598 
 
- 
 
 3599 
	if (grbm_soft_reset) {
- 
 
 3600 
		tmp = RREG32(GRBM_SOFT_RESET);
- 
 
 3601 
		tmp |= grbm_soft_reset;
Line 2264... Line -...
2264 
		      SOFT_RESET_TA |
 - 
 
2265 
		      SOFT_RESET_VC |
 - 
 
2266 
		      SOFT_RESET_VGT);
 - 
 
2267 
 
 3602 
		dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
- 
 
 3603 
		WREG32(GRBM_SOFT_RESET, tmp);
- 
 
 3604 
		tmp = RREG32(GRBM_SOFT_RESET);
2268 
	dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
 3605 
 
2269 
	WREG32(GRBM_SOFT_RESET, grbm_reset);
 3606 
		udelay(50);
- 
 
 3607 
 
- 
 
 3608 
		tmp &= ~grbm_soft_reset;
- 
 
 3609 
		WREG32(GRBM_SOFT_RESET, tmp);
- 
 
 3610 
		tmp = RREG32(GRBM_SOFT_RESET);
- 
 
 3611 
	}
- 
 
 3612 
 
- 
 
 3613 
	if (srbm_soft_reset) {
- 
 
 3614 
		tmp = RREG32(SRBM_SOFT_RESET);
- 
 
 3615 
		tmp |= srbm_soft_reset;
- 
 
 3616 
		dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
- 
 
 3617 
		WREG32(SRBM_SOFT_RESET, tmp);
- 
 
 3618 
		tmp = RREG32(SRBM_SOFT_RESET);
- 
 
 3619 
 
- 
 
 3620 
		udelay(50);
- 
 
 3621 
 
- 
 
 3622 
		tmp &= ~srbm_soft_reset;
2270 
	(void)RREG32(GRBM_SOFT_RESET);
 3623 
		WREG32(SRBM_SOFT_RESET, tmp);
2271 
	udelay(50);
 3624 
		tmp = RREG32(SRBM_SOFT_RESET);
2272 
	WREG32(GRBM_SOFT_RESET, 0);
 - 
 
2273 
	(void)RREG32(GRBM_SOFT_RESET);
 - 
 
2274 
	/* Wait a little for things to settle down */
 - 
 
2275 
	udelay(50);
 - 
 
2276 
	dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
 - 
 
2277 
		RREG32(GRBM_STATUS));
 - 
 
2278 
	dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
 - 
 
2279 
		RREG32(GRBM_STATUS_SE0));
 - 
 
2280 
	dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
 - 
 
2281 
		RREG32(GRBM_STATUS_SE1));
 - 
 
2282 
	dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
 - 
 
2283 
		RREG32(SRBM_STATUS));
 - 
 
- 
 
 3625 
	}
2284 
	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
 - 
 
2285 
		RREG32(CP_STALLED_STAT1));
 - 
 
2286 
	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
 - 
 
2287 
		RREG32(CP_STALLED_STAT2));
 - 
 
2288 
	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
 3626 
 
2289 
		RREG32(CP_BUSY_STAT));
 3627 
	/* Wait a little for things to settle down */
- 
 
 3628 
	udelay(50);
- 
 
 3629 
 
2290 
	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
 3630 
	evergreen_mc_resume(rdev, &save);
Line 2291... Line 3631...
2291 
		RREG32(CP_STAT));
 3631 
	udelay(50);
2292 
	evergreen_mc_resume(rdev, &save);
 3632 
 
- 
 
 3633 
	evergreen_print_gpu_status_regs(rdev);
- 
 
 3634 
}
2293 
	return 0;
 3635 
 
- 
 
 3636 
int evergreen_asic_reset(struct radeon_device *rdev)
- 
 
 3637 
{
- 
 
 3638 
	u32 reset_mask;
- 
 
 3639 
 
- 
 
 3640 
	reset_mask = evergreen_gpu_check_soft_reset(rdev);
- 
 
 3641 
 
- 
 
 3642 
	if (reset_mask)
- 
 
 3643 
		r600_set_bios_scratch_engine_hung(rdev, true);
- 
 
 3644 
 
- 
 
 3645 
	evergreen_gpu_soft_reset(rdev, reset_mask);
- 
 
 3646 
 
- 
 
 3647 
	reset_mask = evergreen_gpu_check_soft_reset(rdev);
- 
 
 3648 
 
- 
 
 3649 
	if (!reset_mask)
- 
 
 3650 
		r600_set_bios_scratch_engine_hung(rdev, false);
- 
 
 3651 
 
- 
 
 3652 
	return 0;
- 
 
 3653 
}
- 
 
 3654 
 
- 
 
 3655 
/**
- 
 
 3656 
 * evergreen_gfx_is_lockup - Check if the GFX engine is locked up
- 
 
 3657 
 *
- 
 
 3658 
 * @rdev: radeon_device pointer
- 
 
 3659 
 * @ring: radeon_ring structure holding ring information
- 
 
 3660 
 *
- 
 
 3661 
 * Check if the GFX engine is locked up.
- 
 
 3662 
 * Returns true if the engine appears to be locked up, false if not.
- 
 
 3663 
 */
- 
 
 3664 
bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
- 
 
 3665 
{
- 
 
 3666 
	u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
- 
 
 3667 
 
- 
 
 3668 
	if (!(reset_mask & (RADEON_RESET_GFX |
- 
 
 3669 
					       RADEON_RESET_COMPUTE |
- 
 
 3670 
			    RADEON_RESET_CP))) {
- 
 
 3671 
		radeon_ring_lockup_update(ring);
- 
 
 3672 
		return false;
- 
 
 3673 
	}
- 
 
 3674 
	/* force CP activities */
- 
 
 3675 
	radeon_ring_force_activity(rdev, ring);
- 
 
 3676 
	return radeon_ring_test_lockup(rdev, ring);
- 
 
 3677 
}
- 
 
 3678 
 
- 
 
 3679 
/**
- 
 
 3680 
 * evergreen_dma_is_lockup - Check if the DMA engine is locked up
- 
 
 3681 
 *
- 
 
 3682 
 * @rdev: radeon_device pointer
- 
 
 3683 
 * @ring: radeon_ring structure holding ring information
- 
 
 3684 
 *
- 
 
 3685 
 * Check if the async DMA engine is locked up.
- 
 
 3686 
 * Returns true if the engine appears to be locked up, false if not.
- 
 
 3687 
 */
- 
 
 3688 
bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
- 
 
 3689 
{
- 
 
 3690 
	u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
- 
 
 3691 
 
- 
 
 3692 
	if (!(reset_mask & RADEON_RESET_DMA)) {
- 
 
 3693 
		radeon_ring_lockup_update(ring);
2294 
}
 3694 
		return false;
Line 2295... Line 3695...
2295 
 
 3695 
	}
Line 2296... Line 3696...
2296 
int evergreen_asic_reset(struct radeon_device *rdev)
 3696 
	/* force ring activities */
Line 3030... Line 4430...
3030 
				break;
 4430 
				break;
3031 
			default:
 4431 
			default:
3032 
				DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
 4432 
				DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3033 
				break;
 4433 
				break;
3034 
			}
 4434 
			}
- 
 
 4435 
		case 124: /* UVD */
- 
 
 4436 
			DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
- 
 
 4437 
			radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
3035 
			break;
 4438 
			break;
3036 
		case 146:
 4439 
		case 146:
3037 
		case 147:
 4440 
		case 147:
3038 
			dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
 4441 
			dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3039 
			dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
 4442 
			dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
Line 3114... Line 4517...
3114 
				   struct radeon_fence *fence)
 4517 
				   struct radeon_fence *fence)
3115 
{
 4518 
{
3116 
	struct radeon_ring *ring = &rdev->ring[fence->ring];
 4519 
	struct radeon_ring *ring = &rdev->ring[fence->ring];
3117 
	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
 4520 
	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3118 
	/* write the fence */
 4521 
	/* write the fence */
3119 
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
 4522 
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
3120 
	radeon_ring_write(ring, addr & 0xfffffffc);
 4523 
	radeon_ring_write(ring, addr & 0xfffffffc);
3121 
	radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
 4524 
	radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3122 
	radeon_ring_write(ring, fence->seq);
 4525 
	radeon_ring_write(ring, fence->seq);
3123 
	/* generate an interrupt */
 4526 
	/* generate an interrupt */
3124 
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
 4527 
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
3125 
	/* flush HDP */
 4528 
	/* flush HDP */
3126 
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
 4529 
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
3127 
	radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);
 4530 
	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3128 
	radeon_ring_write(ring, 1);
 4531 
	radeon_ring_write(ring, 1);
3129 
}
 4532 
}
Line 3130... Line 4533...
3130 
 
 4533 
 
3131 
/**
 4534 
/**
Line 3144... Line 4547...
3144 
	if (rdev->wb.enabled) {
 4547 
	if (rdev->wb.enabled) {
3145 
		u32 next_rptr = ring->wptr + 4;
 4548 
		u32 next_rptr = ring->wptr + 4;
3146 
		while ((next_rptr & 7) != 5)
 4549 
		while ((next_rptr & 7) != 5)
3147 
			next_rptr++;
 4550 
			next_rptr++;
3148 
		next_rptr += 3;
 4551 
		next_rptr += 3;
3149 
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
 4552 
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
3150 
		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
 4553 
		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3151 
		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
 4554 
		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3152 
		radeon_ring_write(ring, next_rptr);
 4555 
		radeon_ring_write(ring, next_rptr);
3153 
	}
 4556 
	}
Line 3154... Line 4557...
3154 
 
 4557 
 
3155 
	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
 4558 
	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3156 
	 * Pad as necessary with NOPs.
 4559 
	 * Pad as necessary with NOPs.
3157 
	 */
 4560 
	 */
3158 
	while ((ring->wptr & 7) != 5)
 4561 
	while ((ring->wptr & 7) != 5)
3159 
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
 4562 
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
3160 
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
 4563 
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
3161 
	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
 4564 
	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
Line 3162... Line 4565...
3162 
	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
 4565 
	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
Line 3214... Line 4617...
3214 
	for (i = 0; i < num_loops; i++) {
 4617 
	for (i = 0; i < num_loops; i++) {
3215 
		cur_size_in_dw = size_in_dw;
 4618 
		cur_size_in_dw = size_in_dw;
3216 
		if (cur_size_in_dw > 0xFFFFF)
 4619 
		if (cur_size_in_dw > 0xFFFFF)
3217 
			cur_size_in_dw = 0xFFFFF;
 4620 
			cur_size_in_dw = 0xFFFFF;
3218 
		size_in_dw -= cur_size_in_dw;
 4621 
		size_in_dw -= cur_size_in_dw;
3219 
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
 4622 
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
3220 
		radeon_ring_write(ring, dst_offset & 0xfffffffc);
 4623 
		radeon_ring_write(ring, dst_offset & 0xfffffffc);
3221 
		radeon_ring_write(ring, src_offset & 0xfffffffc);
 4624 
		radeon_ring_write(ring, src_offset & 0xfffffffc);
3222 
		radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
 4625 
		radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3223 
		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
 4626 
		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
3224 
		src_offset += cur_size_in_dw * 4;
 4627 
		src_offset += cur_size_in_dw * 4;
Line 3237... Line 4640...
3237 
	return r;
 4640 
	return r;
3238 
}
 4641 
}
Line 3239... Line 4642...
3239 
 
 4642 
 
3240 
static int evergreen_startup(struct radeon_device *rdev)
 4643 
static int evergreen_startup(struct radeon_device *rdev)
3241 
{
 4644 
{
3242 
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 4645 
	struct radeon_ring *ring;
Line 3243... Line 4646...
3243 
	int r;
 4646 
	int r;
3244 
 
 4647 
 
Line 3304... Line 4707...
3304 
	if (r) {
 4707 
	if (r) {
3305 
		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
 4708 
		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3306 
		return r;
 4709 
		return r;
3307 
	}
 4710 
	}
Line -... Line 4711...
- 
 
 4711 
 
- 
 
 4712 
//   r = rv770_uvd_resume(rdev);
- 
 
 4713 
//   if (!r) {
- 
 
 4714 
//       r = radeon_fence_driver_start_ring(rdev,
- 
 
 4715 
//                          R600_RING_TYPE_UVD_INDEX);
- 
 
 4716 
//       if (r)
- 
 
 4717 
//           dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
- 
 
 4718 
//   }
- 
 
 4719 
 
- 
 
 4720 
//   if (r)
- 
 
 4721 
//       rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3308 
 
 4722 
 
- 
 
 4723 
	/* Enable IRQ */
- 
 
 4724 
	if (!rdev->irq.installed) {
- 
 
 4725 
		r = radeon_irq_kms_init(rdev);
- 
 
 4726 
		if (r)
- 
 
 4727 
			return r;
- 
 
 4728 
	}
3309 
	/* Enable IRQ */
 4729 
 
3310 
	r = r600_irq_init(rdev);
 4730 
	r = r600_irq_init(rdev);
3311 
	if (r) {
 4731 
	if (r) {
3312 
		DRM_ERROR("radeon: IH init failed (%d).\n", r);
 4732 
		DRM_ERROR("radeon: IH init failed (%d).\n", r);
3313 
//		radeon_irq_kms_fini(rdev);
 4733 
//		radeon_irq_kms_fini(rdev);
3314 
		return r;
 4734 
		return r;
3315 
	}
 4735 
	}
Line -... Line 4736...
- 
 
 4736 
	evergreen_irq_set(rdev);
3316 
	evergreen_irq_set(rdev);
 4737 
 
3317 
 
 4738 
	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3318 
	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
 4739 
	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3319 
			     R600_CP_RB_RPTR, R600_CP_RB_WPTR,
 4740 
			     R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3320 
			     0, 0xfffff, RADEON_CP_PACKET2);
 4741 
			     0, 0xfffff, RADEON_CP_PACKET2);
Line 3321... Line 4742...
3321 
	if (r)
 4742 
	if (r)
3322 
		return r;
 4743 
		return r;
3323 
 
 4744 
 
3324 
	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
 4745 
	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3325 
	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
 4746 
	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3326 
			     DMA_RB_RPTR, DMA_RB_WPTR,
 4747 
			     DMA_RB_RPTR, DMA_RB_WPTR,
Line 3327... Line 4748...
3327 
			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
 4748 
			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
3328 
	if (r)
 4749 
	if (r)
Line 3336... Line 4757...
3336 
		return r;
 4757 
		return r;
3337 
	r = r600_dma_resume(rdev);
 4758 
	r = r600_dma_resume(rdev);
3338 
	if (r)
 4759 
	if (r)
3339 
		return r;
 4760 
		return r;
Line -... Line 4761...
- 
 
 4761 
 
- 
 
 4762 
	ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
- 
 
 4763 
	if (ring->ring_size) {
- 
 
 4764 
		r = radeon_ring_init(rdev, ring, ring->ring_size,
- 
 
 4765 
				     R600_WB_UVD_RPTR_OFFSET,
- 
 
 4766 
				     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
- 
 
 4767 
				     0, 0xfffff, RADEON_CP_PACKET2);
- 
 
 4768 
		if (!r)
- 
 
 4769 
			r = r600_uvd_init(rdev);
- 
 
 4770 
 
- 
 
 4771 
		if (r)
- 
 
 4772 
			DRM_ERROR("radeon: error initializing UVD (%d).\n", r);
- 
 
 4773 
	}
3340 
 
 4774 
 
3341 
	r = radeon_ib_pool_init(rdev);
 4775 
	r = radeon_ib_pool_init(rdev);
3342 
	if (r) {
 4776 
	if (r) {
3343 
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 4777 
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3344 
		return r;
 4778 
		return r;
Line 3408... Line 4842...
3408 
			return -EINVAL;
 4842 
			return -EINVAL;
3409 
		}
 4843 
		}
3410 
		DRM_INFO("GPU not posted. posting now...\n");
 4844 
		DRM_INFO("GPU not posted. posting now...\n");
3411 
		atom_asic_init(rdev->mode_info.atom_context);
 4845 
		atom_asic_init(rdev->mode_info.atom_context);
3412 
	}
 4846 
	}
- 
 
 4847 
	/* init golden registers */
- 
 
 4848 
	evergreen_init_golden_registers(rdev);
3413 
	/* Initialize scratch registers */
 4849 
	/* Initialize scratch registers */
3414 
	r600_scratch_init(rdev);
 4850 
	r600_scratch_init(rdev);
3415 
	/* Initialize surface registers */
 4851 
	/* Initialize surface registers */
3416 
	radeon_surface_init(rdev);
 4852 
	radeon_surface_init(rdev);
3417 
	/* Initialize clocks */
 4853 
	/* Initialize clocks */
Line 3433... Line 4869...
3433 
	/* Memory manager */
 4869 
	/* Memory manager */
3434 
	r = radeon_bo_init(rdev);
 4870 
	r = radeon_bo_init(rdev);
3435 
	if (r)
 4871 
	if (r)
3436 
		return r;
 4872 
		return r;
Line 3437... Line -...
3437 
 
 - 
 
3438 
	r = radeon_irq_kms_init(rdev);
 - 
 
3439 
	if (r)
 - 
 
3440 
		return r;
 - 
 
3441 
 
 4873 
 
3442 
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
 4874 
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
Line 3443... Line 4875...
3443 
	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 4875 
	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3444 
 
 4876 
 
Line -... Line 4877...
- 
 
 4877 
	rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
- 
 
 4878 
	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
- 
 
 4879 
 
- 
 
 4880 
//   r = radeon_uvd_init(rdev);
- 
 
 4881 
//   if (!r) {
- 
 
 4882 
//       rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
- 
 
 4883 
//       r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
3445 
	rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
 4884 
//                  4096);
3446 
	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
 4885 
//   }
Line 3447... Line 4886...
3447 
 
 4886 
 
3448 
	rdev->ih.ring_obj = NULL;
 4887 
	rdev->ih.ring_obj = NULL;
Line 3474... Line 4913...
3474 
}
 4913 
}
Line 3475... Line 4914...
3475 
 
 4914 
 
3476 
 
 4915 
 
3477 
void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
 4916 
void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3478 
{
 - 
 
Line 3479... Line 4917...
3479 
	u32 link_width_cntl, speed_cntl, mask;
 4917 
{
3480 
	int ret;
 4918 
	u32 link_width_cntl, speed_cntl;
Line 3481... Line 4919...
3481 
 
 4919 
 
Line 3490... Line 4928...
3490 
 
 4928 
 
3491 
	/* x2 cards have a special sequence */
 4929 
	/* x2 cards have a special sequence */
3492 
	if (ASIC_IS_X2(rdev))
 4930 
	if (ASIC_IS_X2(rdev))
Line 3493... Line 4931...
3493 
		return;
 4931 
		return;
3494 
 
 - 
 
3495 
	ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
 - 
 
3496 
	if (ret != 0)
 - 
 
3497 
		return;
 4932 
 
3498 
 
 4933 
	if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
Line 3499... Line 4934...
3499 
	if (!(mask & DRM_PCIE_SPEED_50))
 4934 
		(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
3500 
		return;
 4935 
		return;
3501 
 
 4936 
 
3502 
	speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
 4937 
	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3503 
	if (speed_cntl & LC_CURRENT_DATA_RATE) {
 4938 
	if (speed_cntl & LC_CURRENT_DATA_RATE) {
Line 3504... Line 4939...
3504 
		DRM_INFO("PCIE gen 2 link speeds already enabled\n");
 4939 
		DRM_INFO("PCIE gen 2 link speeds already enabled\n");
Line 3505... Line 4940...
3505 
		return;
 4940 
		return;
3506 
	}
 4941 
	}
Line 3507... Line 4942...
3507 
 
 4942 
 
3508 
	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
 4943 
	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3509 
 
 4944 
 
Line 3510... Line 4945...
3510 
	if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
 4945 
	if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3511 
	    (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
 4946 
	    (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3512 
 
 4947 
 
Line 3513... Line 4948...
3513 
		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
 4948 
		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
3514 
		link_width_cntl &= ~LC_UPCONFIGURE_DIS;
 4949 
		link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3515 
		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 4950 
		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
Line 3516... Line 4951...
3516 
 
 4951 
 
3517 
		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
 4952 
		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3518 
		speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
 4953 
		speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
Line 3519... Line 4954...
3519 
		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
 4954 
		WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3520 
 
 4955 
 
3521 
		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
 4956 
		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
Line 3522... Line 4957...
3522 
		speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
 4957 
		speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3523 
		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
 4958 
		WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3524 
 
 4959 
 
3525 
		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
 4960 
		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3526 
		speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
 4961 
		speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3527 
		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
 4962 
		WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3528 
 
 4963 
 
3529 
		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
 4964 
		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3530 
		speed_cntl |= LC_GEN2_EN_STRAP;
 4965 
		speed_cntl |= LC_GEN2_EN_STRAP;
3531 
		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
 4966 
		WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);