Rev 3120 | Rev 3764 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 3120 | Rev 3192 | ||
---|---|---|---|
Line 1732... | Line 1732... | ||
1732 | gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; |
1732 | gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; |
1733 | break; |
1733 | break; |
1734 | case CHIP_SUMO: |
1734 | case CHIP_SUMO: |
1735 | rdev->config.evergreen.num_ses = 1; |
1735 | rdev->config.evergreen.num_ses = 1; |
1736 | rdev->config.evergreen.max_pipes = 4; |
1736 | rdev->config.evergreen.max_pipes = 4; |
1737 | rdev->config.evergreen.max_tile_pipes = 2; |
1737 | rdev->config.evergreen.max_tile_pipes = 4; |
1738 | if (rdev->pdev->device == 0x9648) |
1738 | if (rdev->pdev->device == 0x9648) |
1739 | rdev->config.evergreen.max_simds = 3; |
1739 | rdev->config.evergreen.max_simds = 3; |
1740 | else if ((rdev->pdev->device == 0x9647) || |
1740 | else if ((rdev->pdev->device == 0x9647) || |
1741 | (rdev->pdev->device == 0x964a)) |
1741 | (rdev->pdev->device == 0x964a)) |
1742 | rdev->config.evergreen.max_simds = 4; |
1742 | rdev->config.evergreen.max_simds = 4; |
Line 1755... | Line 1755... | ||
1755 | rdev->config.evergreen.sq_num_cf_insts = 2; |
1755 | rdev->config.evergreen.sq_num_cf_insts = 2; |
Line 1756... | Line 1756... | ||
1756 | 1756 | ||
1757 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1757 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1758 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
1758 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
1759 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
1759 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
1760 | gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; |
1760 | gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN; |
1761 | break; |
1761 | break; |
1762 | case CHIP_SUMO2: |
1762 | case CHIP_SUMO2: |
1763 | rdev->config.evergreen.num_ses = 1; |
1763 | rdev->config.evergreen.num_ses = 1; |
1764 | rdev->config.evergreen.max_pipes = 4; |
1764 | rdev->config.evergreen.max_pipes = 4; |
Line 1777... | Line 1777... | ||
1777 | rdev->config.evergreen.sq_num_cf_insts = 2; |
1777 | rdev->config.evergreen.sq_num_cf_insts = 2; |
Line 1778... | Line 1778... | ||
1778 | 1778 | ||
1779 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1779 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1780 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
1780 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
1781 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
1781 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
1782 | gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; |
1782 | gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN; |
1783 | break; |
1783 | break; |
1784 | case CHIP_BARTS: |
1784 | case CHIP_BARTS: |
1785 | rdev->config.evergreen.num_ses = 2; |
1785 | rdev->config.evergreen.num_ses = 2; |
1786 | rdev->config.evergreen.max_pipes = 4; |
1786 | rdev->config.evergreen.max_pipes = 4; |
Line 1825... | Line 1825... | ||
1825 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
1825 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
1826 | gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN; |
1826 | gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN; |
1827 | break; |
1827 | break; |
1828 | case CHIP_CAICOS: |
1828 | case CHIP_CAICOS: |
1829 | rdev->config.evergreen.num_ses = 1; |
1829 | rdev->config.evergreen.num_ses = 1; |
1830 | rdev->config.evergreen.max_pipes = 4; |
1830 | rdev->config.evergreen.max_pipes = 2; |
1831 | rdev->config.evergreen.max_tile_pipes = 2; |
1831 | rdev->config.evergreen.max_tile_pipes = 2; |
1832 | rdev->config.evergreen.max_simds = 2; |
1832 | rdev->config.evergreen.max_simds = 2; |
1833 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; |
1833 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; |
1834 | rdev->config.evergreen.max_gprs = 256; |
1834 | rdev->config.evergreen.max_gprs = 256; |
1835 | rdev->config.evergreen.max_threads = 192; |
1835 | rdev->config.evergreen.max_threads = 192; |
Line 1945... | Line 1945... | ||
1945 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
1945 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
Line 1946... | Line 1946... | ||
1946 | 1946 | ||
1947 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
1947 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
1948 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
1948 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
- | 1949 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
|
Line 1949... | Line 1950... | ||
1949 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
1950 | WREG32(DMA_TILING_CONFIG, gb_addr_config); |
1950 | 1951 | ||
1951 | tmp = gb_addr_config & NUM_PIPES_MASK; |
1952 | tmp = gb_addr_config & NUM_PIPES_MASK; |
1952 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, |
1953 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, |
Line 2314... | Line 2315... | ||
2314 | if (rdev->family >= CHIP_CAYMAN) { |
2315 | if (rdev->family >= CHIP_CAYMAN) { |
2315 | cayman_cp_int_cntl_setup(rdev, 0, |
2316 | cayman_cp_int_cntl_setup(rdev, 0, |
2316 | CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
2317 | CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
2317 | cayman_cp_int_cntl_setup(rdev, 1, 0); |
2318 | cayman_cp_int_cntl_setup(rdev, 1, 0); |
2318 | cayman_cp_int_cntl_setup(rdev, 2, 0); |
2319 | cayman_cp_int_cntl_setup(rdev, 2, 0); |
- | 2320 | tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; |
|
- | 2321 | WREG32(CAYMAN_DMA1_CNTL, tmp); |
|
2319 | } else |
2322 | } else |
2320 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
2323 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
- | 2324 | tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
|
- | 2325 | WREG32(DMA_CNTL, tmp); |
|
2321 | WREG32(GRBM_INT_CNTL, 0); |
2326 | WREG32(GRBM_INT_CNTL, 0); |
2322 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
2327 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
2323 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
2328 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
2324 | if (rdev->num_crtc >= 4) { |
2329 | if (rdev->num_crtc >= 4) { |
2325 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
2330 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
Line 2368... | Line 2373... | ||
2368 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
2373 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
2369 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
2374 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
2370 | u32 grbm_int_cntl = 0; |
2375 | u32 grbm_int_cntl = 0; |
2371 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; |
2376 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; |
2372 | u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; |
2377 | u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; |
- | 2378 | u32 dma_cntl, dma_cntl1 = 0; |
|
Line 2373... | Line 2379... | ||
2373 | 2379 | ||
2374 | if (!rdev->irq.installed) { |
2380 | if (!rdev->irq.installed) { |
2375 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
2381 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
2376 | return -EINVAL; |
2382 | return -EINVAL; |
Line 2395... | Line 2401... | ||
2395 | afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
2401 | afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
2396 | afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
2402 | afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
2397 | afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
2403 | afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
2398 | afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
2404 | afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
Line -... | Line 2405... | ||
- | 2405 | ||
- | 2406 | dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
|
2399 | 2407 | ||
2400 | if (rdev->family >= CHIP_CAYMAN) { |
2408 | if (rdev->family >= CHIP_CAYMAN) { |
2401 | /* enable CP interrupts on all rings */ |
2409 | /* enable CP interrupts on all rings */ |
2402 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
2410 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
2403 | DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); |
2411 | DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); |
Line 2417... | Line 2425... | ||
2417 | cp_int_cntl |= RB_INT_ENABLE; |
2425 | cp_int_cntl |= RB_INT_ENABLE; |
2418 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
2426 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
2419 | } |
2427 | } |
2420 | } |
2428 | } |
Line -... | Line 2429... | ||
- | 2429 | ||
- | 2430 | if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { |
|
- | 2431 | DRM_DEBUG("r600_irq_set: sw int dma\n"); |
|
- | 2432 | dma_cntl |= TRAP_ENABLE; |
|
- | 2433 | } |
|
- | 2434 | ||
- | 2435 | if (rdev->family >= CHIP_CAYMAN) { |
|
- | 2436 | dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; |
|
- | 2437 | if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { |
|
- | 2438 | DRM_DEBUG("r600_irq_set: sw int dma1\n"); |
|
- | 2439 | dma_cntl1 |= TRAP_ENABLE; |
|
- | 2440 | } |
|
- | 2441 | } |
|
2421 | 2442 | ||
2422 | if (rdev->irq.crtc_vblank_int[0] || |
2443 | if (rdev->irq.crtc_vblank_int[0] || |
2423 | atomic_read(&rdev->irq.pflip[0])) { |
2444 | atomic_read(&rdev->irq.pflip[0])) { |
2424 | DRM_DEBUG("evergreen_irq_set: vblank 0\n"); |
2445 | DRM_DEBUG("evergreen_irq_set: vblank 0\n"); |
2425 | crtc1 |= VBLANK_INT_MASK; |
2446 | crtc1 |= VBLANK_INT_MASK; |
Line 2502... | Line 2523... | ||
2502 | cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); |
2523 | cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); |
2503 | cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1); |
2524 | cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1); |
2504 | cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2); |
2525 | cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2); |
2505 | } else |
2526 | } else |
2506 | WREG32(CP_INT_CNTL, cp_int_cntl); |
2527 | WREG32(CP_INT_CNTL, cp_int_cntl); |
- | 2528 | ||
- | 2529 | WREG32(DMA_CNTL, dma_cntl); |
|
- | 2530 | ||
- | 2531 | if (rdev->family >= CHIP_CAYMAN) |
|
- | 2532 | WREG32(CAYMAN_DMA1_CNTL, dma_cntl1); |
|
- | 2533 | ||
2507 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
2534 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
Line 2508... | Line 2535... | ||
2508 | 2535 | ||
2509 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); |
2536 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); |
2510 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); |
2537 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); |
Line 3004... | Line 3031... | ||
3004 | default: |
3031 | default: |
3005 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); |
3032 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); |
3006 | break; |
3033 | break; |
3007 | } |
3034 | } |
3008 | break; |
3035 | break; |
- | 3036 | case 146: |
|
- | 3037 | case 147: |
|
- | 3038 | dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); |
|
- | 3039 | dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", |
|
- | 3040 | RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); |
|
- | 3041 | dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", |
|
- | 3042 | RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); |
|
- | 3043 | /* reset addr and status */ |
|
- | 3044 | WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); |
|
- | 3045 | break; |
|
3009 | case 176: /* CP_INT in ring buffer */ |
3046 | case 176: /* CP_INT in ring buffer */ |
3010 | case 177: /* CP_INT in IB1 */ |
3047 | case 177: /* CP_INT in IB1 */ |
3011 | case 178: /* CP_INT in IB2 */ |
3048 | case 178: /* CP_INT in IB2 */ |
3012 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
3049 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
3013 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
3050 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
Line 3027... | Line 3064... | ||
3027 | break; |
3064 | break; |
3028 | } |
3065 | } |
3029 | } else |
3066 | } else |
3030 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
3067 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
3031 | break; |
3068 | break; |
- | 3069 | case 224: /* DMA trap event */ |
|
- | 3070 | DRM_DEBUG("IH: DMA trap\n"); |
|
- | 3071 | radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); |
|
- | 3072 | break; |
|
3032 | case 233: /* GUI IDLE */ |
3073 | case 233: /* GUI IDLE */ |
3033 | DRM_DEBUG("IH: GUI idle\n"); |
3074 | DRM_DEBUG("IH: GUI idle\n"); |
3034 | break; |
3075 | break; |
- | 3076 | case 244: /* DMA trap event */ |
|
- | 3077 | if (rdev->family >= CHIP_CAYMAN) { |
|
- | 3078 | DRM_DEBUG("IH: DMA1 trap\n"); |
|
- | 3079 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); |
|
- | 3080 | } |
|
- | 3081 | break; |
|
3035 | default: |
3082 | default: |
3036 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
3083 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
3037 | break; |
3084 | break; |
3038 | } |
3085 | } |
Line 3051... | Line 3098... | ||
3051 | goto restart_ih; |
3098 | goto restart_ih; |
Line 3052... | Line 3099... | ||
3052 | 3099 | ||
3053 | return IRQ_HANDLED; |
3100 | return IRQ_HANDLED; |
Line -... | Line 3101... | ||
- | 3101 | } |
|
- | 3102 | ||
- | 3103 | /** |
|
- | 3104 | * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring |
|
- | 3105 | * |
|
- | 3106 | * @rdev: radeon_device pointer |
|
- | 3107 | * @fence: radeon fence object |
|
- | 3108 | * |
|
- | 3109 | * Add a DMA fence packet to the ring to write |
|
- | 3110 | * the fence seq number and DMA trap packet to generate |
|
- | 3111 | * an interrupt if needed (evergreen-SI). |
|
- | 3112 | */ |
|
- | 3113 | void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, |
|
- | 3114 | struct radeon_fence *fence) |
|
- | 3115 | { |
|
- | 3116 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
|
- | 3117 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
|
- | 3118 | /* write the fence */ |
|
- | 3119 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); |
|
- | 3120 | radeon_ring_write(ring, addr & 0xfffffffc); |
|
- | 3121 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); |
|
- | 3122 | radeon_ring_write(ring, fence->seq); |
|
- | 3123 | /* generate an interrupt */ |
|
- | 3124 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); |
|
- | 3125 | /* flush HDP */ |
|
- | 3126 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); |
|
- | 3127 | radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL); |
|
- | 3128 | radeon_ring_write(ring, 1); |
|
- | 3129 | } |
|
- | 3130 | ||
- | 3131 | /** |
|
- | 3132 | * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine |
|
- | 3133 | * |
|
- | 3134 | * @rdev: radeon_device pointer |
|
- | 3135 | * @ib: IB object to schedule |
|
- | 3136 | * |
|
- | 3137 | * Schedule an IB in the DMA ring (evergreen). |
|
- | 3138 | */ |
|
- | 3139 | void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, |
|
- | 3140 | struct radeon_ib *ib) |
|
- | 3141 | { |
|
- | 3142 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
|
- | 3143 | ||
- | 3144 | if (rdev->wb.enabled) { |
|
- | 3145 | u32 next_rptr = ring->wptr + 4; |
|
- | 3146 | while ((next_rptr & 7) != 5) |
|
- | 3147 | next_rptr++; |
|
- | 3148 | next_rptr += 3; |
|
- | 3149 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); |
|
- | 3150 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
|
- | 3151 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); |
|
- | 3152 | radeon_ring_write(ring, next_rptr); |
|
- | 3153 | } |
|
- | 3154 | ||
- | 3155 | /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. |
|
- | 3156 | * Pad as necessary with NOPs. |
|
- | 3157 | */ |
|
- | 3158 | while ((ring->wptr & 7) != 5) |
|
- | 3159 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
|
- | 3160 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); |
|
- | 3161 | radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); |
|
- | 3162 | radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); |
|
- | 3163 | ||
- | 3164 | } |
|
- | 3165 | ||
- | 3166 | /** |
|
- | 3167 | * evergreen_copy_dma - copy pages using the DMA engine |
|
- | 3168 | * |
|
- | 3169 | * @rdev: radeon_device pointer |
|
- | 3170 | * @src_offset: src GPU address |
|
- | 3171 | * @dst_offset: dst GPU address |
|
- | 3172 | * @num_gpu_pages: number of GPU pages to xfer |
|
- | 3173 | * @fence: radeon fence object |
|
- | 3174 | * |
|
- | 3175 | * Copy GPU paging using the DMA engine (evergreen-cayman). |
|
- | 3176 | * Used by the radeon ttm implementation to move pages if |
|
- | 3177 | * registered as the asic copy callback. |
|
- | 3178 | */ |
|
- | 3179 | int evergreen_copy_dma(struct radeon_device *rdev, |
|
- | 3180 | uint64_t src_offset, uint64_t dst_offset, |
|
- | 3181 | unsigned num_gpu_pages, |
|
- | 3182 | struct radeon_fence **fence) |
|
- | 3183 | { |
|
- | 3184 | struct radeon_semaphore *sem = NULL; |
|
- | 3185 | int ring_index = rdev->asic->copy.dma_ring_index; |
|
- | 3186 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
|
- | 3187 | u32 size_in_dw, cur_size_in_dw; |
|
- | 3188 | int i, num_loops; |
|
- | 3189 | int r = 0; |
|
- | 3190 | ||
- | 3191 | r = radeon_semaphore_create(rdev, &sem); |
|
- | 3192 | if (r) { |
|
- | 3193 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
|
- | 3194 | return r; |
|
- | 3195 | } |
|
- | 3196 | ||
- | 3197 | size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; |
|
- | 3198 | num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff); |
|
- | 3199 | r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); |
|
- | 3200 | if (r) { |
|
- | 3201 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
|
- | 3202 | radeon_semaphore_free(rdev, &sem, NULL); |
|
- | 3203 | return r; |
|
- | 3204 | } |
|
- | 3205 | ||
- | 3206 | if (radeon_fence_need_sync(*fence, ring->idx)) { |
|
- | 3207 | radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, |
|
- | 3208 | ring->idx); |
|
- | 3209 | radeon_fence_note_sync(*fence, ring->idx); |
|
- | 3210 | } else { |
|
- | 3211 | radeon_semaphore_free(rdev, &sem, NULL); |
|
- | 3212 | } |
|
- | 3213 | ||
- | 3214 | for (i = 0; i < num_loops; i++) { |
|
- | 3215 | cur_size_in_dw = size_in_dw; |
|
- | 3216 | if (cur_size_in_dw > 0xFFFFF) |
|
- | 3217 | cur_size_in_dw = 0xFFFFF; |
|
- | 3218 | size_in_dw -= cur_size_in_dw; |
|
- | 3219 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); |
|
- | 3220 | radeon_ring_write(ring, dst_offset & 0xfffffffc); |
|
- | 3221 | radeon_ring_write(ring, src_offset & 0xfffffffc); |
|
- | 3222 | radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); |
|
- | 3223 | radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); |
|
- | 3224 | src_offset += cur_size_in_dw * 4; |
|
- | 3225 | dst_offset += cur_size_in_dw * 4; |
|
- | 3226 | } |
|
- | 3227 | ||
- | 3228 | r = radeon_fence_emit(rdev, fence, ring->idx); |
|
- | 3229 | if (r) { |
|
- | 3230 | radeon_ring_unlock_undo(rdev, ring); |
|
- | 3231 | return r; |
|
- | 3232 | } |
|
- | 3233 | ||
- | 3234 | radeon_ring_unlock_commit(rdev, ring); |
|
- | 3235 | radeon_semaphore_free(rdev, &sem, *fence); |
|
- | 3236 | ||
- | 3237 | return r; |
|
3054 | } |
3238 | } |
3055 | 3239 | ||
3056 | static int evergreen_startup(struct radeon_device *rdev) |
3240 | static int evergreen_startup(struct radeon_device *rdev) |
3057 | { |
3241 | { |
Line 3108... | Line 3292... | ||
3108 | /* allocate wb buffer */ |
3292 | /* allocate wb buffer */ |
3109 | r = radeon_wb_init(rdev); |
3293 | r = radeon_wb_init(rdev); |
3110 | if (r) |
3294 | if (r) |
3111 | return r; |
3295 | return r; |
Line -... | Line 3296... | ||
- | 3296 | ||
- | 3297 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
|
- | 3298 | if (r) { |
|
- | 3299 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
|
- | 3300 | return r; |
|
- | 3301 | } |
|
- | 3302 | ||
- | 3303 | r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); |
|
- | 3304 | if (r) { |
|
- | 3305 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
|
- | 3306 | return r; |
|
- | 3307 | } |
|
3112 | 3308 | ||
3113 | /* Enable IRQ */ |
3309 | /* Enable IRQ */ |
3114 | r = r600_irq_init(rdev); |
3310 | r = r600_irq_init(rdev); |
3115 | if (r) { |
3311 | if (r) { |
3116 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
3312 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
Line 3122... | Line 3318... | ||
3122 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
3318 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
3123 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
3319 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
3124 | 0, 0xfffff, RADEON_CP_PACKET2); |
3320 | 0, 0xfffff, RADEON_CP_PACKET2); |
3125 | if (r) |
3321 | if (r) |
3126 | return r; |
3322 | return r; |
- | 3323 | ||
- | 3324 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
|
- | 3325 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
|
- | 3326 | DMA_RB_RPTR, DMA_RB_WPTR, |
|
- | 3327 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
|
- | 3328 | if (r) |
|
- | 3329 | return r; |
|
- | 3330 | ||
3127 | r = evergreen_cp_load_microcode(rdev); |
3331 | r = evergreen_cp_load_microcode(rdev); |
3128 | if (r) |
3332 | if (r) |
3129 | return r; |
3333 | return r; |
3130 | r = evergreen_cp_resume(rdev); |
3334 | r = evergreen_cp_resume(rdev); |
3131 | if (r) |
3335 | if (r) |
3132 | return r; |
3336 | return r; |
- | 3337 | r = r600_dma_resume(rdev); |
|
- | 3338 | if (r) |
|
- | 3339 | return r; |
|
- | 3340 | ||
- | 3341 | r = radeon_ib_pool_init(rdev); |
|
- | 3342 | if (r) { |
|
- | 3343 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
|
- | 3344 | return r; |
|
- | 3345 | } |
|
Line 3133... | Line 3346... | ||
3133 | 3346 | ||
3134 | return 0; |
3347 | return 0; |
Line 3227... | Line 3440... | ||
3227 | return r; |
3440 | return r; |
Line 3228... | Line 3441... | ||
3228 | 3441 | ||
3229 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
3442 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
Line -... | Line 3443... | ||
- | 3443 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
|
- | 3444 | ||
- | 3445 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
|
3230 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
3446 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
3231 | 3447 | ||
Line 3232... | Line 3448... | ||
3232 | rdev->ih.ring_obj = NULL; |
3448 | rdev->ih.ring_obj = NULL; |
3233 | r600_ih_ring_init(rdev, 64 * 1024); |
3449 | r600_ih_ring_init(rdev, 64 * 1024); |