Rev 3031 | Rev 3192 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 3031 | Rev 3120 | ||
|---|---|---|---|
| Line 1241... | Line 1241... | ||
| 1241 | for (j = 0; j < rdev->usec_timeout; j++) { |
1241 | for (j = 0; j < rdev->usec_timeout; j++) { |
| 1242 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
1242 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
| 1243 | break; |
1243 | break; |
| 1244 | udelay(1); |
1244 | udelay(1); |
| 1245 | } |
1245 | } |
| - | 1246 | } else { |
|
| - | 1247 | save->crtc_enabled[i] = false; |
|
| 1246 | } |
1248 | } |
| 1247 | } |
1249 | } |
| Line 1248... | Line 1250... | ||
| 1248 | 1250 | ||
| Line 1559... | Line 1561... | ||
| 1559 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
1561 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
| 1560 | WREG32(CP_RB_RPTR_WR, 0); |
1562 | WREG32(CP_RB_RPTR_WR, 0); |
| 1561 | ring->wptr = 0; |
1563 | ring->wptr = 0; |
| 1562 | WREG32(CP_RB_WPTR, ring->wptr); |
1564 | WREG32(CP_RB_WPTR, ring->wptr); |
| Line 1563... | Line 1565... | ||
| 1563 | 1565 | ||
| 1564 | /* set the wb address wether it's enabled or not */ |
1566 | /* set the wb address whether it's enabled or not */ |
| 1565 | WREG32(CP_RB_RPTR_ADDR, |
1567 | WREG32(CP_RB_RPTR_ADDR, |
| 1566 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
1568 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
| 1567 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
1569 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |