Rev 2005 | Rev 2175 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 2005 | Rev 2160 | ||
---|---|---|---|
Line 731... | Line 731... | ||
731 | /* should really do this at mode validation time... */ |
731 | /* should really do this at mode validation time... */ |
732 | if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || |
732 | if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || |
733 | !evergreen_average_bandwidth_vs_available_bandwidth(&wm) || |
733 | !evergreen_average_bandwidth_vs_available_bandwidth(&wm) || |
734 | !evergreen_check_latency_hiding(&wm) || |
734 | !evergreen_check_latency_hiding(&wm) || |
735 | (rdev->disp_priority == 2)) { |
735 | (rdev->disp_priority == 2)) { |
736 | DRM_INFO("force priority to high\n"); |
736 | DRM_DEBUG_KMS("force priority to high\n"); |
737 | priority_a_cnt |= PRIORITY_ALWAYS_ON; |
737 | priority_a_cnt |= PRIORITY_ALWAYS_ON; |
738 | priority_b_cnt |= PRIORITY_ALWAYS_ON; |
738 | priority_b_cnt |= PRIORITY_ALWAYS_ON; |
739 | } |
739 | } |
Line 740... | Line 740... | ||
740 | 740 | ||
Line 1345... | Line 1345... | ||
1345 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ |
1345 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ |
1346 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | |
1346 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | |
1347 | SOFT_RESET_PA | |
1347 | SOFT_RESET_PA | |
1348 | SOFT_RESET_SH | |
1348 | SOFT_RESET_SH | |
1349 | SOFT_RESET_VGT | |
1349 | SOFT_RESET_VGT | |
- | 1350 | SOFT_RESET_SPI | |
|
1350 | SOFT_RESET_SX)); |
1351 | SOFT_RESET_SX)); |
1351 | RREG32(GRBM_SOFT_RESET); |
1352 | RREG32(GRBM_SOFT_RESET); |
1352 | mdelay(15); |
1353 | mdelay(15); |
1353 | WREG32(GRBM_SOFT_RESET, 0); |
1354 | WREG32(GRBM_SOFT_RESET, 0); |
1354 | RREG32(GRBM_SOFT_RESET); |
1355 | RREG32(GRBM_SOFT_RESET); |
Line 1370... | Line 1371... | ||
1370 | WREG32(CP_RB_RPTR_WR, 0); |
1371 | WREG32(CP_RB_RPTR_WR, 0); |
1371 | WREG32(CP_RB_WPTR, 0); |
1372 | WREG32(CP_RB_WPTR, 0); |
Line 1372... | Line 1373... | ||
1372 | 1373 | ||
1373 | /* set the wb address wether it's enabled or not */ |
1374 | /* set the wb address wether it's enabled or not */ |
1374 | WREG32(CP_RB_RPTR_ADDR, |
- | |
1375 | #ifdef __BIG_ENDIAN |
- | |
1376 | RB_RPTR_SWAP(2) | |
- | |
1377 | #endif |
1375 | WREG32(CP_RB_RPTR_ADDR, |
1378 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
1376 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
1379 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
1377 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
Line 1380... | Line 1378... | ||
1380 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
1378 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
Line 2035... | Line 2033... | ||
2035 | rdev->config.evergreen.tile_config |= |
2033 | rdev->config.evergreen.tile_config |= |
2036 | ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8; |
2034 | ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8; |
2037 | rdev->config.evergreen.tile_config |= |
2035 | rdev->config.evergreen.tile_config |= |
2038 | ((gb_addr_config & 0x30000000) >> 28) << 12; |
2036 | ((gb_addr_config & 0x30000000) >> 28) << 12; |
Line -... | Line 2037... | ||
- | 2037 | ||
2039 | 2038 | rdev->config.evergreen.backend_map = gb_backend_map; |
|
2040 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
2039 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
2041 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
2040 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
2042 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
2041 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |