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| Rev 5271 | Rev 6104 | ||
|---|---|---|---|
| Line 25... | Line 25... | ||
| 25 | #include |
25 | #include |
| 26 | #include |
26 | #include |
| 27 | #include "drmP.h" |
27 | #include "drmP.h" |
| 28 | #include "radeon.h" |
28 | #include "radeon.h" |
| 29 | #include "radeon_asic.h" |
29 | #include "radeon_asic.h" |
| - | 30 | #include "radeon_audio.h" |
|
| 30 | #include "cikd.h" |
31 | #include "cikd.h" |
| 31 | #include "atom.h" |
32 | #include "atom.h" |
| 32 | #include "cik_blit_shaders.h" |
33 | #include "cik_blit_shaders.h" |
| 33 | #include "radeon_ucode.h" |
34 | #include "radeon_ucode.h" |
| 34 | #include "clearstate_ci.h" |
35 | #include "clearstate_ci.h" |
| Line 138... | Line 139... | ||
| 138 | static void cik_fini_pg(struct radeon_device *rdev); |
139 | static void cik_fini_pg(struct radeon_device *rdev); |
| 139 | static void cik_fini_cg(struct radeon_device *rdev); |
140 | static void cik_fini_cg(struct radeon_device *rdev); |
| 140 | static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev, |
141 | static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev, |
| 141 | bool enable); |
142 | bool enable); |
| Line -... | Line 143... | ||
| - | 143 | ||
| - | 144 | /** |
|
| - | 145 | * cik_get_allowed_info_register - fetch the register for the info ioctl |
|
| - | 146 | * |
|
| - | 147 | * @rdev: radeon_device pointer |
|
| - | 148 | * @reg: register offset in bytes |
|
| - | 149 | * @val: register value |
|
| - | 150 | * |
|
| - | 151 | * Returns 0 for success or -EINVAL for an invalid register |
|
| - | 152 | * |
|
| - | 153 | */ |
|
| - | 154 | int cik_get_allowed_info_register(struct radeon_device *rdev, |
|
| - | 155 | u32 reg, u32 *val) |
|
| - | 156 | { |
|
| - | 157 | switch (reg) { |
|
| - | 158 | case GRBM_STATUS: |
|
| - | 159 | case GRBM_STATUS2: |
|
| - | 160 | case GRBM_STATUS_SE0: |
|
| - | 161 | case GRBM_STATUS_SE1: |
|
| - | 162 | case GRBM_STATUS_SE2: |
|
| - | 163 | case GRBM_STATUS_SE3: |
|
| - | 164 | case SRBM_STATUS: |
|
| - | 165 | case SRBM_STATUS2: |
|
| - | 166 | case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET): |
|
| - | 167 | case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET): |
|
| - | 168 | case UVD_STATUS: |
|
| - | 169 | /* TODO VCE */ |
|
| - | 170 | *val = RREG32(reg); |
|
| - | 171 | return 0; |
|
| - | 172 | default: |
|
| - | 173 | return -EINVAL; |
|
| - | 174 | } |
|
| - | 175 | } |
|
| - | 176 | ||
| - | 177 | /* |
|
| - | 178 | * Indirect registers accessor |
|
| - | 179 | */ |
|
| - | 180 | u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) |
|
| - | 181 | { |
|
| - | 182 | unsigned long flags; |
|
| - | 183 | u32 r; |
|
| - | 184 | ||
| - | 185 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
|
| - | 186 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
|
| - | 187 | r = RREG32(CIK_DIDT_IND_DATA); |
|
| - | 188 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
|
| - | 189 | return r; |
|
| - | 190 | } |
|
| - | 191 | ||
| - | 192 | void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
|
| - | 193 | { |
|
| - | 194 | unsigned long flags; |
|
| - | 195 | ||
| - | 196 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
|
| - | 197 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
|
| - | 198 | WREG32(CIK_DIDT_IND_DATA, (v)); |
|
| - | 199 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
|
| - | 200 | } |
|
| 142 | 201 | ||
| 143 | /* get temperature in millidegrees */ |
202 | /* get temperature in millidegrees */ |
| 144 | int ci_get_temp(struct radeon_device *rdev) |
203 | int ci_get_temp(struct radeon_device *rdev) |
| 145 | { |
204 | { |
| 146 | u32 temp; |
205 | u32 temp; |
| Line 3610... | Line 3669... | ||
| 3610 | WREG32((0x2c20 + j), 0x00000000); |
3669 | WREG32((0x2c20 + j), 0x00000000); |
| 3611 | WREG32((0x2c24 + j), 0x00000000); |
3670 | WREG32((0x2c24 + j), 0x00000000); |
| 3612 | } |
3671 | } |
| Line 3613... | Line 3672... | ||
| 3613 | 3672 | ||
| - | 3673 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
|
| - | 3674 | WREG32(SRBM_INT_CNTL, 0x1); |
|
| Line 3614... | Line 3675... | ||
| 3614 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
3675 | WREG32(SRBM_INT_ACK, 0x1); |
| Line 3615... | Line 3676... | ||
| 3615 | 3676 | ||
| 3616 | WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); |
3677 | WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); |
| Line 3902... | Line 3963... | ||
| 3902 | struct radeon_fence *fence) |
3963 | struct radeon_fence *fence) |
| 3903 | { |
3964 | { |
| 3904 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
3965 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
| 3905 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
3966 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
| Line 3906... | Line 3967... | ||
| 3906 | 3967 | ||
| - | 3968 | /* Workaround for cache flush problems. First send a dummy EOP |
|
| - | 3969 | * event down the pipe with seq one below. |
|
| - | 3970 | */ |
|
| - | 3971 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
|
| - | 3972 | radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | |
|
| - | 3973 | EOP_TC_ACTION_EN | |
|
| - | 3974 | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | |
|
| - | 3975 | EVENT_INDEX(5))); |
|
| - | 3976 | radeon_ring_write(ring, addr & 0xfffffffc); |
|
| - | 3977 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | |
|
| - | 3978 | DATA_SEL(1) | INT_SEL(0)); |
|
| - | 3979 | radeon_ring_write(ring, fence->seq - 1); |
|
| - | 3980 | radeon_ring_write(ring, 0); |
|
| - | 3981 | ||
| 3907 | /* EVENT_WRITE_EOP - flush caches, send int */ |
3982 | /* Then send the real EOP event down the pipe. */ |
| 3908 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
3983 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
| 3909 | radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | |
3984 | radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | |
| 3910 | EOP_TC_ACTION_EN | |
3985 | EOP_TC_ACTION_EN | |
| 3911 | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | |
3986 | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | |
| Line 4096... | Line 4171... | ||
| 4096 | } |
4171 | } |
| Line 4097... | Line 4172... | ||
| 4097 | 4172 | ||
| Line 4098... | Line 4173... | ||
| 4098 | control |= ib->length_dw | (vm_id << 24); |
4173 | control |= ib->length_dw | (vm_id << 24); |
| 4099 | - | ||
| 4100 | radeon_ring_write(ring, header); |
- | |
| 4101 | radeon_ring_write(ring, |
- | |
| 4102 | #ifdef __BIG_ENDIAN |
- | |
| 4103 | (2 << 0) | |
4174 | |
| 4104 | #endif |
4175 | radeon_ring_write(ring, header); |
| 4105 | (ib->gpu_addr & 0xFFFFFFFC)); |
4176 | radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC)); |
| 4106 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); |
4177 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); |
| Line 4107... | Line 4178... | ||
| 4107 | radeon_ring_write(ring, control); |
4178 | radeon_ring_write(ring, control); |
| Line 4527... | Line 4598... | ||
| 4527 | /* XXX check if swapping is necessary on BE */ |
4598 | /* XXX check if swapping is necessary on BE */ |
| 4528 | rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; |
4599 | rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; |
| 4529 | WDOORBELL32(ring->doorbell_index, ring->wptr); |
4600 | WDOORBELL32(ring->doorbell_index, ring->wptr); |
| 4530 | } |
4601 | } |
| Line -... | Line 4602... | ||
| - | 4602 | ||
| - | 4603 | static void cik_compute_stop(struct radeon_device *rdev, |
|
| - | 4604 | struct radeon_ring *ring) |
|
| - | 4605 | { |
|
| - | 4606 | u32 j, tmp; |
|
| - | 4607 | ||
| - | 4608 | cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); |
|
| - | 4609 | /* Disable wptr polling. */ |
|
| - | 4610 | tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); |
|
| - | 4611 | tmp &= ~WPTR_POLL_EN; |
|
| - | 4612 | WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); |
|
| - | 4613 | /* Disable HQD. */ |
|
| - | 4614 | if (RREG32(CP_HQD_ACTIVE) & 1) { |
|
| - | 4615 | WREG32(CP_HQD_DEQUEUE_REQUEST, 1); |
|
| - | 4616 | for (j = 0; j < rdev->usec_timeout; j++) { |
|
| - | 4617 | if (!(RREG32(CP_HQD_ACTIVE) & 1)) |
|
| - | 4618 | break; |
|
| - | 4619 | udelay(1); |
|
| - | 4620 | } |
|
| - | 4621 | WREG32(CP_HQD_DEQUEUE_REQUEST, 0); |
|
| - | 4622 | WREG32(CP_HQD_PQ_RPTR, 0); |
|
| - | 4623 | WREG32(CP_HQD_PQ_WPTR, 0); |
|
| - | 4624 | } |
|
| - | 4625 | cik_srbm_select(rdev, 0, 0, 0, 0); |
|
| - | 4626 | } |
|
| 4531 | 4627 | ||
| 4532 | /** |
4628 | /** |
| 4533 | * cik_cp_compute_enable - enable/disable the compute CP MEs |
4629 | * cik_cp_compute_enable - enable/disable the compute CP MEs |
| 4534 | * |
4630 | * |
| 4535 | * @rdev: radeon_device pointer |
4631 | * @rdev: radeon_device pointer |
| Line 4540... | Line 4636... | ||
| 4540 | static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable) |
4636 | static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable) |
| 4541 | { |
4637 | { |
| 4542 | if (enable) |
4638 | if (enable) |
| 4543 | WREG32(CP_MEC_CNTL, 0); |
4639 | WREG32(CP_MEC_CNTL, 0); |
| 4544 | else { |
4640 | else { |
| - | 4641 | /* |
|
| - | 4642 | * To make hibernation reliable we need to clear compute ring |
|
| - | 4643 | * configuration before halting the compute ring. |
|
| - | 4644 | */ |
|
| - | 4645 | mutex_lock(&rdev->srbm_mutex); |
|
| - | 4646 | cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); |
|
| - | 4647 | cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); |
|
| - | 4648 | mutex_unlock(&rdev->srbm_mutex); |
|
| - | 4649 | ||
| 4545 | WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); |
4650 | WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); |
| 4546 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; |
4651 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; |
| 4547 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; |
4652 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; |
| 4548 | } |
4653 | } |
| 4549 | udelay(50); |
4654 | udelay(50); |
| Line 5705... | Line 5810... | ||
| 5705 | 5810 | ||
| 5706 | /* bits 0-15 are the VM contexts0-15 */ |
5811 | /* bits 0-15 are the VM contexts0-15 */ |
| 5707 | WREG32(VM_INVALIDATE_REQUEST, 0x1); |
5812 | WREG32(VM_INVALIDATE_REQUEST, 0x1); |
| Line -... | Line 5813... | ||
| - | 5813 | } |
|
| - | 5814 | ||
| - | 5815 | static void cik_pcie_init_compute_vmid(struct radeon_device *rdev) |
|
| - | 5816 | { |
|
| - | 5817 | int i; |
|
| - | 5818 | uint32_t sh_mem_bases, sh_mem_config; |
|
| - | 5819 | ||
| - | 5820 | sh_mem_bases = 0x6000 | 0x6000 << 16; |
|
| - | 5821 | sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED); |
|
| - | 5822 | sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED); |
|
| - | 5823 | ||
| - | 5824 | mutex_lock(&rdev->srbm_mutex); |
|
| - | 5825 | for (i = 8; i < 16; i++) { |
|
| - | 5826 | cik_srbm_select(rdev, 0, 0, 0, i); |
|
| - | 5827 | /* CP and shaders */ |
|
| - | 5828 | WREG32(SH_MEM_CONFIG, sh_mem_config); |
|
| - | 5829 | WREG32(SH_MEM_APE1_BASE, 1); |
|
| - | 5830 | WREG32(SH_MEM_APE1_LIMIT, 0); |
|
| - | 5831 | WREG32(SH_MEM_BASES, sh_mem_bases); |
|
| - | 5832 | } |
|
| - | 5833 | cik_srbm_select(rdev, 0, 0, 0, 0); |
|
| - | 5834 | mutex_unlock(&rdev->srbm_mutex); |
|
| 5708 | } |
5835 | } |
| 5709 | 5836 | ||
| 5710 | /** |
5837 | /** |
| 5711 | * cik_pcie_gart_enable - gart enable |
5838 | * cik_pcie_gart_enable - gart enable |
| 5712 | * |
5839 | * |
| Line 5763... | Line 5890... | ||
| 5763 | WREG32(0x15DC, 0); |
5890 | WREG32(0x15DC, 0); |
| Line 5764... | Line 5891... | ||
| 5764 | 5891 | ||
| 5765 | /* restore context1-15 */ |
5892 | /* restore context1-15 */ |
| 5766 | /* set vm size, must be a multiple of 4 */ |
5893 | /* set vm size, must be a multiple of 4 */ |
| 5767 | WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); |
5894 | WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); |
| 5768 | WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); |
5895 | WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); |
| 5769 | for (i = 1; i < 16; i++) { |
5896 | for (i = 1; i < 16; i++) { |
| 5770 | if (i < 8) |
5897 | if (i < 8) |
| 5771 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), |
5898 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), |
| 5772 | rdev->vm_manager.saved_table_addr[i]); |
5899 | rdev->vm_manager.saved_table_addr[i]); |
| Line 5818... | Line 5945... | ||
| 5818 | /* XXX SDMA RLC - todo */ |
5945 | /* XXX SDMA RLC - todo */ |
| 5819 | } |
5946 | } |
| 5820 | cik_srbm_select(rdev, 0, 0, 0, 0); |
5947 | cik_srbm_select(rdev, 0, 0, 0, 0); |
| 5821 | mutex_unlock(&rdev->srbm_mutex); |
5948 | mutex_unlock(&rdev->srbm_mutex); |
| Line -... | Line 5949... | ||
| - | 5949 | ||
| - | 5950 | cik_pcie_init_compute_vmid(rdev); |
|
| 5822 | 5951 | ||
| 5823 | cik_pcie_gart_tlb_flush(rdev); |
5952 | cik_pcie_gart_tlb_flush(rdev); |
| 5824 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
5953 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| 5825 | (unsigned)(rdev->mc.gtt_size >> 20), |
5954 | (unsigned)(rdev->mc.gtt_size >> 20), |
| 5826 | (unsigned long long)rdev->gart.table_addr); |
5955 | (unsigned long long)rdev->gart.table_addr); |
| Line 6031... | Line 6160... | ||
| 6031 | WRITE_DATA_DST_SEL(0))); |
6160 | WRITE_DATA_DST_SEL(0))); |
| 6032 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
6161 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
| 6033 | radeon_ring_write(ring, 0); |
6162 | radeon_ring_write(ring, 0); |
| 6034 | radeon_ring_write(ring, 1 << vm_id); |
6163 | radeon_ring_write(ring, 1 << vm_id); |
| Line -... | Line 6164... | ||
| - | 6164 | ||
| - | 6165 | /* wait for the invalidate to complete */ |
|
| - | 6166 | radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); |
|
| - | 6167 | radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ |
|
| - | 6168 | WAIT_REG_MEM_FUNCTION(0) | /* always */ |
|
| - | 6169 | WAIT_REG_MEM_ENGINE(0))); /* me */ |
|
| - | 6170 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
|
| - | 6171 | radeon_ring_write(ring, 0); |
|
| - | 6172 | radeon_ring_write(ring, 0); /* ref */ |
|
| - | 6173 | radeon_ring_write(ring, 0); /* mask */ |
|
| - | 6174 | radeon_ring_write(ring, 0x20); /* poll interval */ |
|
| 6035 | 6175 | ||
| 6036 | /* compute doesn't have PFP */ |
6176 | /* compute doesn't have PFP */ |
| 6037 | if (usepfp) { |
6177 | if (usepfp) { |
| 6038 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
6178 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
| 6039 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
6179 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
| Line 7178... | Line 7318... | ||
| 7178 | WREG32(CP_ME2_PIPE1_INT_CNTL, 0); |
7318 | WREG32(CP_ME2_PIPE1_INT_CNTL, 0); |
| 7179 | WREG32(CP_ME2_PIPE2_INT_CNTL, 0); |
7319 | WREG32(CP_ME2_PIPE2_INT_CNTL, 0); |
| 7180 | WREG32(CP_ME2_PIPE3_INT_CNTL, 0); |
7320 | WREG32(CP_ME2_PIPE3_INT_CNTL, 0); |
| 7181 | /* grbm */ |
7321 | /* grbm */ |
| 7182 | WREG32(GRBM_INT_CNTL, 0); |
7322 | WREG32(GRBM_INT_CNTL, 0); |
| - | 7323 | /* SRBM */ |
|
| - | 7324 | WREG32(SRBM_INT_CNTL, 0); |
|
| 7183 | /* vline/vblank, etc. */ |
7325 | /* vline/vblank, etc. */ |
| 7184 | WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
7326 | WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
| 7185 | WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
7327 | WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
| 7186 | if (rdev->num_crtc >= 4) { |
7328 | if (rdev->num_crtc >= 4) { |
| 7187 | WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
7329 | WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
| Line 7321... | Line 7463... | ||
| 7321 | u32 cp_m1p0; |
7463 | u32 cp_m1p0; |
| 7322 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
7464 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
| 7323 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
7465 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
| 7324 | u32 grbm_int_cntl = 0; |
7466 | u32 grbm_int_cntl = 0; |
| 7325 | u32 dma_cntl, dma_cntl1; |
7467 | u32 dma_cntl, dma_cntl1; |
| 7326 | u32 thermal_int; |
- | |
| Line 7327... | Line 7468... | ||
| 7327 | 7468 | ||
| 7328 | if (!rdev->irq.installed) { |
7469 | if (!rdev->irq.installed) { |
| 7329 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
7470 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
| 7330 | return -EINVAL; |
7471 | return -EINVAL; |
| Line 7339... | Line 7480... | ||
| 7339 | 7480 | ||
| 7340 | cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & |
7481 | cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & |
| 7341 | (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
7482 | (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
| Line 7342... | Line 7483... | ||
| 7342 | cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; |
7483 | cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; |
| 7343 | 7484 | ||
| 7344 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
7485 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 7345 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
7486 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 7346 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
7487 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 7347 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
7488 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| Line 7348... | Line 7489... | ||
| 7348 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
7489 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 7349 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
7490 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| Line 7350... | Line 7491... | ||
| 7350 | 7491 | ||
| Line 7351... | Line -... | ||
| 7351 | dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; |
- | |
| 7352 | dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; |
- | |
| 7353 | - | ||
| 7354 | cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; |
- | |
| 7355 | - | ||
| 7356 | if (rdev->flags & RADEON_IS_IGP) |
- | |
| 7357 | thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) & |
- | |
| 7358 | ~(THERM_INTH_MASK | THERM_INTL_MASK); |
7492 | dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; |
| 7359 | else |
7493 | dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; |
| 7360 | thermal_int = RREG32_SMC(CG_THERMAL_INT) & |
7494 | |
| 7361 | ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); |
7495 | cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; |
| 7362 | 7496 | ||
| Line 7438... | Line 7572... | ||
| 7438 | DRM_DEBUG("cik_irq_set: vblank 5\n"); |
7572 | DRM_DEBUG("cik_irq_set: vblank 5\n"); |
| 7439 | crtc6 |= VBLANK_INTERRUPT_MASK; |
7573 | crtc6 |= VBLANK_INTERRUPT_MASK; |
| 7440 | } |
7574 | } |
| 7441 | if (rdev->irq.hpd[0]) { |
7575 | if (rdev->irq.hpd[0]) { |
| 7442 | DRM_DEBUG("cik_irq_set: hpd 1\n"); |
7576 | DRM_DEBUG("cik_irq_set: hpd 1\n"); |
| 7443 | hpd1 |= DC_HPDx_INT_EN; |
7577 | hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 7444 | } |
7578 | } |
| 7445 | if (rdev->irq.hpd[1]) { |
7579 | if (rdev->irq.hpd[1]) { |
| 7446 | DRM_DEBUG("cik_irq_set: hpd 2\n"); |
7580 | DRM_DEBUG("cik_irq_set: hpd 2\n"); |
| 7447 | hpd2 |= DC_HPDx_INT_EN; |
7581 | hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 7448 | } |
7582 | } |
| 7449 | if (rdev->irq.hpd[2]) { |
7583 | if (rdev->irq.hpd[2]) { |
| 7450 | DRM_DEBUG("cik_irq_set: hpd 3\n"); |
7584 | DRM_DEBUG("cik_irq_set: hpd 3\n"); |
| 7451 | hpd3 |= DC_HPDx_INT_EN; |
7585 | hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 7452 | } |
7586 | } |
| 7453 | if (rdev->irq.hpd[3]) { |
7587 | if (rdev->irq.hpd[3]) { |
| 7454 | DRM_DEBUG("cik_irq_set: hpd 4\n"); |
7588 | DRM_DEBUG("cik_irq_set: hpd 4\n"); |
| 7455 | hpd4 |= DC_HPDx_INT_EN; |
7589 | hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 7456 | } |
7590 | } |
| 7457 | if (rdev->irq.hpd[4]) { |
7591 | if (rdev->irq.hpd[4]) { |
| 7458 | DRM_DEBUG("cik_irq_set: hpd 5\n"); |
7592 | DRM_DEBUG("cik_irq_set: hpd 5\n"); |
| 7459 | hpd5 |= DC_HPDx_INT_EN; |
7593 | hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 7460 | } |
7594 | } |
| 7461 | if (rdev->irq.hpd[5]) { |
7595 | if (rdev->irq.hpd[5]) { |
| 7462 | DRM_DEBUG("cik_irq_set: hpd 6\n"); |
7596 | DRM_DEBUG("cik_irq_set: hpd 6\n"); |
| 7463 | hpd6 |= DC_HPDx_INT_EN; |
7597 | hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 7464 | } |
- | |
| 7465 | - | ||
| 7466 | if (rdev->irq.dpm_thermal) { |
- | |
| 7467 | DRM_DEBUG("dpm thermal\n"); |
- | |
| 7468 | if (rdev->flags & RADEON_IS_IGP) |
- | |
| 7469 | thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK; |
- | |
| 7470 | else |
- | |
| 7471 | thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; |
- | |
| 7472 | } |
7598 | } |
| Line 7473... | Line 7599... | ||
| 7473 | 7599 | ||
| Line 7474... | Line 7600... | ||
| 7474 | WREG32(CP_INT_CNTL_RING0, cp_int_cntl); |
7600 | WREG32(CP_INT_CNTL_RING0, cp_int_cntl); |
| Line 7515... | Line 7641... | ||
| 7515 | WREG32(DC_HPD3_INT_CONTROL, hpd3); |
7641 | WREG32(DC_HPD3_INT_CONTROL, hpd3); |
| 7516 | WREG32(DC_HPD4_INT_CONTROL, hpd4); |
7642 | WREG32(DC_HPD4_INT_CONTROL, hpd4); |
| 7517 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
7643 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
| 7518 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
7644 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
| Line 7519... | Line 7645... | ||
| 7519 | 7645 | ||
| 7520 | if (rdev->flags & RADEON_IS_IGP) |
- | |
| 7521 | WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); |
- | |
| 7522 | else |
7646 | /* posting read */ |
| Line 7523... | Line 7647... | ||
| 7523 | WREG32_SMC(CG_THERMAL_INT, thermal_int); |
7647 | RREG32(SRBM_STATUS); |
| 7524 | 7648 | ||
| Line 7525... | Line 7649... | ||
| 7525 | return 0; |
7649 | return 0; |
| Line 7640... | Line 7764... | ||
| 7640 | if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
7764 | if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
| 7641 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
7765 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
| 7642 | tmp |= DC_HPDx_INT_ACK; |
7766 | tmp |= DC_HPDx_INT_ACK; |
| 7643 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
7767 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
| 7644 | } |
7768 | } |
| - | 7769 | if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) { |
|
| - | 7770 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
|
| - | 7771 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 7772 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
|
| - | 7773 | } |
|
| - | 7774 | if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) { |
|
| - | 7775 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
|
| - | 7776 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 7777 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
|
| - | 7778 | } |
|
| - | 7779 | if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { |
|
| - | 7780 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
|
| - | 7781 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 7782 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
|
| - | 7783 | } |
|
| - | 7784 | if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { |
|
| - | 7785 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
|
| - | 7786 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 7787 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
|
| - | 7788 | } |
|
| - | 7789 | if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { |
|
| - | 7790 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
|
| - | 7791 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 7792 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
|
| - | 7793 | } |
|
| - | 7794 | if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { |
|
| - | 7795 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
|
| - | 7796 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 7797 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
|
| - | 7798 | } |
|
| 7645 | } |
7799 | } |
| Line 7646... | Line 7800... | ||
| 7646 | 7800 | ||
| 7647 | /** |
7801 | /** |
| 7648 | * cik_irq_disable - disable interrupts |
7802 | * cik_irq_disable - disable interrupts |
| Line 7765... | Line 7919... | ||
| 7765 | u32 rptr; |
7919 | u32 rptr; |
| 7766 | u32 src_id, src_data, ring_id; |
7920 | u32 src_id, src_data, ring_id; |
| 7767 | u8 me_id, pipe_id, queue_id; |
7921 | u8 me_id, pipe_id, queue_id; |
| 7768 | u32 ring_index; |
7922 | u32 ring_index; |
| 7769 | bool queue_hotplug = false; |
7923 | bool queue_hotplug = false; |
| - | 7924 | bool queue_dp = false; |
|
| 7770 | bool queue_reset = false; |
7925 | bool queue_reset = false; |
| 7771 | u32 addr, status, mc_client; |
7926 | u32 addr, status, mc_client; |
| 7772 | bool queue_thermal = false; |
7927 | bool queue_thermal = false; |
| Line 7773... | Line 7928... | ||
| 7773 | 7928 | ||
| Line 7803... | Line 7958... | ||
| 7803 | 7958 | ||
| 7804 | switch (src_id) { |
7959 | switch (src_id) { |
| 7805 | case 1: /* D1 vblank/vline */ |
7960 | case 1: /* D1 vblank/vline */ |
| 7806 | switch (src_data) { |
7961 | switch (src_data) { |
| 7807 | case 0: /* D1 vblank */ |
7962 | case 0: /* D1 vblank */ |
| - | 7963 | if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)) |
|
| - | 7964 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7808 | if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) { |
7965 | |
| - | 7966 | if (rdev->irq.crtc_vblank_int[0]) { |
|
| 7809 | if (rdev->irq.crtc_vblank_int[0]) { |
7967 | drm_handle_vblank(rdev->ddev, 0); |
| - | 7968 | rdev->pm.vblank_sync = true; |
|
| 7810 | rdev->pm.vblank_sync = true; |
7969 | wake_up(&rdev->irq.vblank_queue); |
| - | 7970 | } |
|
| - | 7971 | if (atomic_read(&rdev->irq.pflip[0])) |
|
| 7811 | } |
7972 | radeon_crtc_handle_vblank(rdev, 0); |
| 7812 | rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
7973 | rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
| 7813 | DRM_DEBUG("IH: D1 vblank\n"); |
7974 | DRM_DEBUG("IH: D1 vblank\n"); |
| 7814 | } |
7975 | |
| 7815 | break; |
7976 | break; |
| 7816 | case 1: /* D1 vline */ |
7977 | case 1: /* D1 vline */ |
| - | 7978 | if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)) |
|
| - | 7979 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7817 | if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) { |
7980 | |
| 7818 | rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT; |
7981 | rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT; |
| 7819 | DRM_DEBUG("IH: D1 vline\n"); |
7982 | DRM_DEBUG("IH: D1 vline\n"); |
| 7820 | } |
7983 | |
| 7821 | break; |
7984 | break; |
| 7822 | default: |
7985 | default: |
| 7823 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
7986 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 7824 | break; |
7987 | break; |
| 7825 | } |
7988 | } |
| 7826 | break; |
7989 | break; |
| 7827 | case 2: /* D2 vblank/vline */ |
7990 | case 2: /* D2 vblank/vline */ |
| 7828 | switch (src_data) { |
7991 | switch (src_data) { |
| 7829 | case 0: /* D2 vblank */ |
7992 | case 0: /* D2 vblank */ |
| - | 7993 | if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) |
|
| - | 7994 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7830 | if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { |
7995 | |
| - | 7996 | if (rdev->irq.crtc_vblank_int[1]) { |
|
| 7831 | if (rdev->irq.crtc_vblank_int[1]) { |
7997 | drm_handle_vblank(rdev->ddev, 1); |
| - | 7998 | rdev->pm.vblank_sync = true; |
|
| 7832 | rdev->pm.vblank_sync = true; |
7999 | wake_up(&rdev->irq.vblank_queue); |
| - | 8000 | } |
|
| - | 8001 | if (atomic_read(&rdev->irq.pflip[1])) |
|
| 7833 | } |
8002 | radeon_crtc_handle_vblank(rdev, 1); |
| 7834 | rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; |
8003 | rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; |
| 7835 | DRM_DEBUG("IH: D2 vblank\n"); |
8004 | DRM_DEBUG("IH: D2 vblank\n"); |
| 7836 | } |
8005 | |
| 7837 | break; |
8006 | break; |
| 7838 | case 1: /* D2 vline */ |
8007 | case 1: /* D2 vline */ |
| - | 8008 | if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)) |
|
| - | 8009 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7839 | if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT) { |
8010 | |
| 7840 | rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; |
8011 | rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; |
| 7841 | DRM_DEBUG("IH: D2 vline\n"); |
8012 | DRM_DEBUG("IH: D2 vline\n"); |
| 7842 | } |
8013 | |
| 7843 | break; |
8014 | break; |
| 7844 | default: |
8015 | default: |
| 7845 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
8016 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 7846 | break; |
8017 | break; |
| 7847 | } |
8018 | } |
| 7848 | break; |
8019 | break; |
| 7849 | case 3: /* D3 vblank/vline */ |
8020 | case 3: /* D3 vblank/vline */ |
| 7850 | switch (src_data) { |
8021 | switch (src_data) { |
| 7851 | case 0: /* D3 vblank */ |
8022 | case 0: /* D3 vblank */ |
| - | 8023 | if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) |
|
| - | 8024 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7852 | if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { |
8025 | |
| - | 8026 | if (rdev->irq.crtc_vblank_int[2]) { |
|
| 7853 | if (rdev->irq.crtc_vblank_int[2]) { |
8027 | drm_handle_vblank(rdev->ddev, 2); |
| - | 8028 | rdev->pm.vblank_sync = true; |
|
| 7854 | rdev->pm.vblank_sync = true; |
8029 | wake_up(&rdev->irq.vblank_queue); |
| - | 8030 | } |
|
| - | 8031 | if (atomic_read(&rdev->irq.pflip[2])) |
|
| 7855 | } |
8032 | radeon_crtc_handle_vblank(rdev, 2); |
| 7856 | rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; |
8033 | rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; |
| 7857 | DRM_DEBUG("IH: D3 vblank\n"); |
8034 | DRM_DEBUG("IH: D3 vblank\n"); |
| 7858 | } |
8035 | |
| 7859 | break; |
8036 | break; |
| 7860 | case 1: /* D3 vline */ |
8037 | case 1: /* D3 vline */ |
| - | 8038 | if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) |
|
| - | 8039 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7861 | if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { |
8040 | |
| 7862 | rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; |
8041 | rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; |
| 7863 | DRM_DEBUG("IH: D3 vline\n"); |
8042 | DRM_DEBUG("IH: D3 vline\n"); |
| 7864 | } |
8043 | |
| 7865 | break; |
8044 | break; |
| 7866 | default: |
8045 | default: |
| 7867 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
8046 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 7868 | break; |
8047 | break; |
| 7869 | } |
8048 | } |
| 7870 | break; |
8049 | break; |
| 7871 | case 4: /* D4 vblank/vline */ |
8050 | case 4: /* D4 vblank/vline */ |
| 7872 | switch (src_data) { |
8051 | switch (src_data) { |
| 7873 | case 0: /* D4 vblank */ |
8052 | case 0: /* D4 vblank */ |
| - | 8053 | if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) |
|
| - | 8054 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7874 | if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { |
8055 | |
| - | 8056 | if (rdev->irq.crtc_vblank_int[3]) { |
|
| 7875 | if (rdev->irq.crtc_vblank_int[3]) { |
8057 | drm_handle_vblank(rdev->ddev, 3); |
| - | 8058 | rdev->pm.vblank_sync = true; |
|
| 7876 | rdev->pm.vblank_sync = true; |
8059 | wake_up(&rdev->irq.vblank_queue); |
| - | 8060 | } |
|
| - | 8061 | if (atomic_read(&rdev->irq.pflip[3])) |
|
| 7877 | } |
8062 | radeon_crtc_handle_vblank(rdev, 3); |
| 7878 | rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; |
8063 | rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; |
| 7879 | DRM_DEBUG("IH: D4 vblank\n"); |
8064 | DRM_DEBUG("IH: D4 vblank\n"); |
| 7880 | } |
8065 | |
| 7881 | break; |
8066 | break; |
| 7882 | case 1: /* D4 vline */ |
8067 | case 1: /* D4 vline */ |
| - | 8068 | if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) |
|
| - | 8069 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7883 | if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { |
8070 | |
| 7884 | rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; |
8071 | rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; |
| 7885 | DRM_DEBUG("IH: D4 vline\n"); |
8072 | DRM_DEBUG("IH: D4 vline\n"); |
| 7886 | } |
8073 | |
| 7887 | break; |
8074 | break; |
| 7888 | default: |
8075 | default: |
| 7889 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
8076 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 7890 | break; |
8077 | break; |
| 7891 | } |
8078 | } |
| 7892 | break; |
8079 | break; |
| 7893 | case 5: /* D5 vblank/vline */ |
8080 | case 5: /* D5 vblank/vline */ |
| 7894 | switch (src_data) { |
8081 | switch (src_data) { |
| 7895 | case 0: /* D5 vblank */ |
8082 | case 0: /* D5 vblank */ |
| - | 8083 | if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) |
|
| - | 8084 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7896 | if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { |
8085 | |
| - | 8086 | if (rdev->irq.crtc_vblank_int[4]) { |
|
| 7897 | if (rdev->irq.crtc_vblank_int[4]) { |
8087 | drm_handle_vblank(rdev->ddev, 4); |
| - | 8088 | rdev->pm.vblank_sync = true; |
|
| 7898 | rdev->pm.vblank_sync = true; |
8089 | wake_up(&rdev->irq.vblank_queue); |
| - | 8090 | } |
|
| - | 8091 | if (atomic_read(&rdev->irq.pflip[4])) |
|
| 7899 | } |
8092 | radeon_crtc_handle_vblank(rdev, 4); |
| 7900 | rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; |
8093 | rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; |
| 7901 | DRM_DEBUG("IH: D5 vblank\n"); |
8094 | DRM_DEBUG("IH: D5 vblank\n"); |
| 7902 | } |
8095 | |
| 7903 | break; |
8096 | break; |
| 7904 | case 1: /* D5 vline */ |
8097 | case 1: /* D5 vline */ |
| - | 8098 | if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) |
|
| - | 8099 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7905 | if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { |
8100 | |
| 7906 | rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; |
8101 | rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; |
| 7907 | DRM_DEBUG("IH: D5 vline\n"); |
8102 | DRM_DEBUG("IH: D5 vline\n"); |
| 7908 | } |
8103 | |
| 7909 | break; |
8104 | break; |
| 7910 | default: |
8105 | default: |
| 7911 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
8106 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 7912 | break; |
8107 | break; |
| 7913 | } |
8108 | } |
| 7914 | break; |
8109 | break; |
| 7915 | case 6: /* D6 vblank/vline */ |
8110 | case 6: /* D6 vblank/vline */ |
| 7916 | switch (src_data) { |
8111 | switch (src_data) { |
| 7917 | case 0: /* D6 vblank */ |
8112 | case 0: /* D6 vblank */ |
| - | 8113 | if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) |
|
| - | 8114 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7918 | if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { |
8115 | |
| - | 8116 | if (rdev->irq.crtc_vblank_int[5]) { |
|
| 7919 | if (rdev->irq.crtc_vblank_int[5]) { |
8117 | drm_handle_vblank(rdev->ddev, 5); |
| - | 8118 | rdev->pm.vblank_sync = true; |
|
| 7920 | rdev->pm.vblank_sync = true; |
8119 | wake_up(&rdev->irq.vblank_queue); |
| - | 8120 | } |
|
| - | 8121 | if (atomic_read(&rdev->irq.pflip[5])) |
|
| 7921 | } |
8122 | radeon_crtc_handle_vblank(rdev, 5); |
| 7922 | rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; |
8123 | rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; |
| 7923 | DRM_DEBUG("IH: D6 vblank\n"); |
8124 | DRM_DEBUG("IH: D6 vblank\n"); |
| 7924 | } |
8125 | |
| 7925 | break; |
8126 | break; |
| 7926 | case 1: /* D6 vline */ |
8127 | case 1: /* D6 vline */ |
| - | 8128 | if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) |
|
| - | 8129 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 7927 | if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { |
8130 | |
| 7928 | rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; |
8131 | rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; |
| 7929 | DRM_DEBUG("IH: D6 vline\n"); |
8132 | DRM_DEBUG("IH: D6 vline\n"); |
| 7930 | } |
8133 | |
| 7931 | break; |
8134 | break; |
| 7932 | default: |
8135 | default: |
| 7933 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
8136 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 7934 | break; |
8137 | break; |
| Line 7943... | Line 8146... | ||
| 7943 | DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); |
8146 | DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); |
| 7944 | break; |
8147 | break; |
| 7945 | case 42: /* HPD hotplug */ |
8148 | case 42: /* HPD hotplug */ |
| 7946 | switch (src_data) { |
8149 | switch (src_data) { |
| 7947 | case 0: |
8150 | case 0: |
| 7948 | if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) { |
8151 | if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT)) |
| - | 8152 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8153 | ||
| 7949 | rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT; |
8154 | rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT; |
| 7950 | queue_hotplug = true; |
8155 | queue_hotplug = true; |
| 7951 | DRM_DEBUG("IH: HPD1\n"); |
8156 | DRM_DEBUG("IH: HPD1\n"); |
| 7952 | } |
8157 | |
| 7953 | break; |
8158 | break; |
| 7954 | case 1: |
8159 | case 1: |
| 7955 | if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) { |
8160 | if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT)) |
| - | 8161 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8162 | ||
| 7956 | rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT; |
8163 | rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT; |
| 7957 | queue_hotplug = true; |
8164 | queue_hotplug = true; |
| 7958 | DRM_DEBUG("IH: HPD2\n"); |
8165 | DRM_DEBUG("IH: HPD2\n"); |
| 7959 | } |
8166 | |
| 7960 | break; |
8167 | break; |
| 7961 | case 2: |
8168 | case 2: |
| 7962 | if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) { |
8169 | if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT)) |
| - | 8170 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8171 | ||
| 7963 | rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; |
8172 | rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; |
| 7964 | queue_hotplug = true; |
8173 | queue_hotplug = true; |
| 7965 | DRM_DEBUG("IH: HPD3\n"); |
8174 | DRM_DEBUG("IH: HPD3\n"); |
| 7966 | } |
8175 | |
| 7967 | break; |
8176 | break; |
| 7968 | case 3: |
8177 | case 3: |
| 7969 | if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) { |
8178 | if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT)) |
| - | 8179 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8180 | ||
| 7970 | rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; |
8181 | rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; |
| 7971 | queue_hotplug = true; |
8182 | queue_hotplug = true; |
| 7972 | DRM_DEBUG("IH: HPD4\n"); |
8183 | DRM_DEBUG("IH: HPD4\n"); |
| 7973 | } |
8184 | |
| 7974 | break; |
8185 | break; |
| 7975 | case 4: |
8186 | case 4: |
| 7976 | if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) { |
8187 | if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT)) |
| - | 8188 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8189 | ||
| 7977 | rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; |
8190 | rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; |
| 7978 | queue_hotplug = true; |
8191 | queue_hotplug = true; |
| 7979 | DRM_DEBUG("IH: HPD5\n"); |
8192 | DRM_DEBUG("IH: HPD5\n"); |
| 7980 | } |
8193 | |
| 7981 | break; |
8194 | break; |
| 7982 | case 5: |
8195 | case 5: |
| 7983 | if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
8196 | if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT)) |
| - | 8197 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8198 | ||
| 7984 | rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; |
8199 | rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; |
| 7985 | queue_hotplug = true; |
8200 | queue_hotplug = true; |
| 7986 | DRM_DEBUG("IH: HPD6\n"); |
8201 | DRM_DEBUG("IH: HPD6\n"); |
| - | 8202 | ||
| - | 8203 | break; |
|
| - | 8204 | case 6: |
|
| - | 8205 | if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT)) |
|
| - | 8206 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8207 | ||
| - | 8208 | rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT; |
|
| - | 8209 | queue_dp = true; |
|
| - | 8210 | DRM_DEBUG("IH: HPD_RX 1\n"); |
|
| - | 8211 | ||
| - | 8212 | break; |
|
| - | 8213 | case 7: |
|
| - | 8214 | if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT)) |
|
| - | 8215 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8216 | ||
| - | 8217 | rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; |
|
| - | 8218 | queue_dp = true; |
|
| - | 8219 | DRM_DEBUG("IH: HPD_RX 2\n"); |
|
| - | 8220 | ||
| - | 8221 | break; |
|
| - | 8222 | case 8: |
|
| - | 8223 | if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) |
|
| - | 8224 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8225 | ||
| - | 8226 | rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; |
|
| - | 8227 | queue_dp = true; |
|
| - | 8228 | DRM_DEBUG("IH: HPD_RX 3\n"); |
|
| - | 8229 | ||
| - | 8230 | break; |
|
| - | 8231 | case 9: |
|
| - | 8232 | if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) |
|
| - | 8233 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8234 | ||
| - | 8235 | rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; |
|
| - | 8236 | queue_dp = true; |
|
| - | 8237 | DRM_DEBUG("IH: HPD_RX 4\n"); |
|
| - | 8238 | ||
| - | 8239 | break; |
|
| - | 8240 | case 10: |
|
| - | 8241 | if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) |
|
| - | 8242 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8243 | ||
| - | 8244 | rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; |
|
| - | 8245 | queue_dp = true; |
|
| - | 8246 | DRM_DEBUG("IH: HPD_RX 5\n"); |
|
| - | 8247 | ||
| 7987 | } |
8248 | break; |
| - | 8249 | case 11: |
|
| - | 8250 | if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) |
|
| - | 8251 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 8252 | ||
| - | 8253 | rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; |
|
| - | 8254 | queue_dp = true; |
|
| - | 8255 | DRM_DEBUG("IH: HPD_RX 6\n"); |
|
| - | 8256 | ||
| 7988 | break; |
8257 | break; |
| 7989 | default: |
8258 | default: |
| 7990 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
8259 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 7991 | break; |
8260 | break; |
| 7992 | } |
8261 | } |
| 7993 | break; |
8262 | break; |
| - | 8263 | case 96: |
|
| - | 8264 | DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); |
|
| - | 8265 | WREG32(SRBM_INT_ACK, 0x1); |
|
| - | 8266 | break; |
|
| 7994 | case 124: /* UVD */ |
8267 | case 124: /* UVD */ |
| 7995 | DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); |
8268 | DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); |
| 7996 | radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); |
8269 | radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); |
| 7997 | break; |
8270 | break; |
| 7998 | case 146: |
8271 | case 146: |
| Line 8317... | Line 8590... | ||
| 8317 | } |
8590 | } |
| 8318 | } |
8591 | } |
| 8319 | if (r) |
8592 | if (r) |
| 8320 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
8593 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
| Line -... | Line 8594... | ||
| - | 8594 | ||
| - | 8595 | r = radeon_vce_resume(rdev); |
|
| - | 8596 | if (!r) { |
|
| - | 8597 | r = vce_v2_0_resume(rdev); |
|
| - | 8598 | if (!r) |
|
| - | 8599 | r = radeon_fence_driver_start_ring(rdev, |
|
| - | 8600 | TN_RING_TYPE_VCE1_INDEX); |
|
| - | 8601 | if (!r) |
|
| - | 8602 | r = radeon_fence_driver_start_ring(rdev, |
|
| - | 8603 | TN_RING_TYPE_VCE2_INDEX); |
|
| 8321 | 8604 | } |
|
| 8322 | if (r) { |
8605 | if (r) { |
| 8323 | dev_err(rdev->dev, "VCE init error (%d).\n", r); |
8606 | dev_err(rdev->dev, "VCE init error (%d).\n", r); |
| 8324 | rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; |
8607 | rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; |
| 8325 | rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; |
8608 | rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; |
| Line 8406... | Line 8689... | ||
| 8406 | if (!r) |
8689 | if (!r) |
| 8407 | r = uvd_v1_0_init(rdev); |
8690 | r = uvd_v1_0_init(rdev); |
| 8408 | if (r) |
8691 | if (r) |
| 8409 | DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
8692 | DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
| 8410 | } |
8693 | } |
| - | 8694 | ||
| - | 8695 | r = -ENOENT; |
|
| - | 8696 | ||
| - | 8697 | ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; |
|
| - | 8698 | if (ring->ring_size) |
|
| - | 8699 | r = radeon_ring_init(rdev, ring, ring->ring_size, 0, |
|
| - | 8700 | VCE_CMD_NO_OP); |
|
| - | 8701 | ||
| - | 8702 | ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; |
|
| - | 8703 | if (ring->ring_size) |
|
| - | 8704 | r = radeon_ring_init(rdev, ring, ring->ring_size, 0, |
|
| - | 8705 | VCE_CMD_NO_OP); |
|
| - | 8706 | ||
| - | 8707 | if (!r) |
|
| - | 8708 | r = vce_v1_0_init(rdev); |
|
| - | 8709 | else if (r != -ENOENT) |
|
| - | 8710 | DRM_ERROR("radeon: failed initializing VCE (%d).\n", r); |
|
| - | 8711 | ||
| 8411 | r = radeon_ib_pool_init(rdev); |
8712 | r = radeon_ib_pool_init(rdev); |
| 8412 | if (r) { |
8713 | if (r) { |
| 8413 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
8714 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 8414 | return r; |
8715 | return r; |
| 8415 | } |
8716 | } |
| Line 8549... | Line 8850... | ||
| 8549 | if (!r) { |
8850 | if (!r) { |
| 8550 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
8851 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
| 8551 | ring->ring_obj = NULL; |
8852 | ring->ring_obj = NULL; |
| 8552 | r600_ring_init(rdev, ring, 4096); |
8853 | r600_ring_init(rdev, ring, 4096); |
| 8553 | } |
8854 | } |
| - | 8855 | ||
| - | 8856 | r = radeon_vce_init(rdev); |
|
| - | 8857 | if (!r) { |
|
| - | 8858 | ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; |
|
| - | 8859 | ring->ring_obj = NULL; |
|
| - | 8860 | r600_ring_init(rdev, ring, 4096); |
|
| - | 8861 | ||
| - | 8862 | ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; |
|
| - | 8863 | ring->ring_obj = NULL; |
|
| - | 8864 | r600_ring_init(rdev, ring, 4096); |
|
| - | 8865 | } |
|
| - | 8866 | ||
| 8554 | rdev->ih.ring_obj = NULL; |
8867 | rdev->ih.ring_obj = NULL; |
| 8555 | r600_ih_ring_init(rdev, 64 * 1024); |
8868 | r600_ih_ring_init(rdev, 64 * 1024); |
| Line 8556... | Line 8869... | ||
| 8556 | 8869 | ||
| 8557 | r = r600_pcie_gart_init(rdev); |
8870 | r = r600_pcie_gart_init(rdev); |
| Line 8560... | Line 8873... | ||
| 8560 | 8873 | ||
| 8561 | rdev->accel_working = true; |
8874 | rdev->accel_working = true; |
| 8562 | r = cik_startup(rdev); |
8875 | r = cik_startup(rdev); |
| 8563 | if (r) { |
8876 | if (r) { |
| - | 8877 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
|
| - | 8878 | cik_cp_fini(rdev); |
|
| - | 8879 | cik_sdma_fini(rdev); |
|
| - | 8880 | cik_irq_fini(rdev); |
|
| - | 8881 | sumo_rlc_fini(rdev); |
|
| - | 8882 | cik_mec_fini(rdev); |
|
| - | 8883 | radeon_wb_fini(rdev); |
|
| - | 8884 | radeon_ib_pool_fini(rdev); |
|
| - | 8885 | radeon_vm_manager_fini(rdev); |
|
| - | 8886 | radeon_irq_kms_fini(rdev); |
|
| 8564 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
8887 | cik_pcie_gart_fini(rdev); |
| 8565 | rdev->accel_working = false; |
8888 | rdev->accel_working = false; |
| Line 8566... | Line 8889... | ||
| 8566 | } |
8889 | } |
| 8567 | 8890 | ||
| Line 8586... | Line 8909... | ||
| 8586 | * to an idle state (CIK). |
8909 | * to an idle state (CIK). |
| 8587 | * Called at driver unload. |
8910 | * Called at driver unload. |
| 8588 | */ |
8911 | */ |
| 8589 | void cik_fini(struct radeon_device *rdev) |
8912 | void cik_fini(struct radeon_device *rdev) |
| 8590 | { |
8913 | { |
| - | 8914 | radeon_pm_fini(rdev); |
|
| - | 8915 | cik_cp_fini(rdev); |
|
| - | 8916 | cik_sdma_fini(rdev); |
|
| - | 8917 | cik_fini_pg(rdev); |
|
| - | 8918 | cik_fini_cg(rdev); |
|
| - | 8919 | cik_irq_fini(rdev); |
|
| - | 8920 | sumo_rlc_fini(rdev); |
|
| - | 8921 | cik_mec_fini(rdev); |
|
| - | 8922 | radeon_wb_fini(rdev); |
|
| - | 8923 | radeon_vm_manager_fini(rdev); |
|
| - | 8924 | radeon_ib_pool_fini(rdev); |
|
| - | 8925 | radeon_irq_kms_fini(rdev); |
|
| - | 8926 | uvd_v1_0_fini(rdev); |
|
| - | 8927 | radeon_uvd_fini(rdev); |
|
| - | 8928 | radeon_vce_fini(rdev); |
|
| - | 8929 | cik_pcie_gart_fini(rdev); |
|
| - | 8930 | r600_vram_scratch_fini(rdev); |
|
| - | 8931 | radeon_gem_fini(rdev); |
|
| - | 8932 | radeon_fence_driver_fini(rdev); |
|
| - | 8933 | radeon_bo_fini(rdev); |
|
| - | 8934 | radeon_atombios_fini(rdev); |
|
| 8591 | kfree(rdev->bios); |
8935 | kfree(rdev->bios); |
| 8592 | rdev->bios = NULL; |
8936 | rdev->bios = NULL; |
| 8593 | } |
8937 | } |
| Line 8594... | Line 8938... | ||
| 8594 | 8938 | ||
| Line 9203... | Line 9547... | ||
| 9203 | !dce8_average_bandwidth_vs_available_bandwidth(&wm_low) || |
9547 | !dce8_average_bandwidth_vs_available_bandwidth(&wm_low) || |
| 9204 | !dce8_check_latency_hiding(&wm_low) || |
9548 | !dce8_check_latency_hiding(&wm_low) || |
| 9205 | (rdev->disp_priority == 2)) { |
9549 | (rdev->disp_priority == 2)) { |
| 9206 | DRM_DEBUG_KMS("force priority to high\n"); |
9550 | DRM_DEBUG_KMS("force priority to high\n"); |
| 9207 | } |
9551 | } |
| - | 9552 | ||
| - | 9553 | /* Save number of lines the linebuffer leads before the scanout */ |
|
| - | 9554 | radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); |
|
| 9208 | } |
9555 | } |
| Line 9209... | Line 9556... | ||
| 9209 | 9556 | ||
| 9210 | /* select wm A */ |
9557 | /* select wm A */ |
| 9211 | wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); |
9558 | wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); |