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Rev 3764 | Rev 5078 | ||
---|---|---|---|
Line 181... | Line 181... | ||
181 | struct radeon_device *rdev = dev->dev_private; |
181 | struct radeon_device *rdev = dev->dev_private; |
182 | struct backlight_device *bd; |
182 | struct backlight_device *bd; |
183 | struct backlight_properties props; |
183 | struct backlight_properties props; |
184 | struct radeon_backlight_privdata *pdata; |
184 | struct radeon_backlight_privdata *pdata; |
185 | struct radeon_encoder_atom_dig *dig; |
185 | struct radeon_encoder_atom_dig *dig; |
186 | u8 backlight_level; |
- | |
187 | char bl_name[16]; |
186 | char bl_name[16]; |
Line -... | Line 187... | ||
- | 187 | ||
- | 188 | /* Mac laptops with multiple GPUs use the gmux driver for backlight |
|
- | 189 | * so don't register a backlight device |
|
- | 190 | */ |
|
- | 191 | if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && |
|
- | 192 | (rdev->pdev->device == 0x6741)) |
|
- | 193 | return; |
|
188 | 194 | ||
189 | if (!radeon_encoder->enc_priv) |
195 | if (!radeon_encoder->enc_priv) |
Line 190... | Line 196... | ||
190 | return; |
196 | return; |
191 | 197 | ||
Line 204... | Line 210... | ||
204 | memset(&props, 0, sizeof(props)); |
210 | memset(&props, 0, sizeof(props)); |
205 | props.max_brightness = RADEON_MAX_BL_LEVEL; |
211 | props.max_brightness = RADEON_MAX_BL_LEVEL; |
206 | props.type = BACKLIGHT_RAW; |
212 | props.type = BACKLIGHT_RAW; |
207 | snprintf(bl_name, sizeof(bl_name), |
213 | snprintf(bl_name, sizeof(bl_name), |
208 | "radeon_bl%d", dev->primary->index); |
214 | "radeon_bl%d", dev->primary->index); |
209 | bd = backlight_device_register(bl_name, &drm_connector->kdev, |
215 | bd = backlight_device_register(bl_name, drm_connector->kdev, |
210 | pdata, &radeon_atom_backlight_ops, &props); |
216 | pdata, &radeon_atom_backlight_ops, &props); |
211 | if (IS_ERR(bd)) { |
217 | if (IS_ERR(bd)) { |
212 | DRM_ERROR("Backlight registration failed\n"); |
218 | DRM_ERROR("Backlight registration failed\n"); |
213 | goto error; |
219 | goto error; |
214 | } |
220 | } |
Line 215... | Line 221... | ||
215 | 221 | ||
Line 216... | Line -... | ||
216 | pdata->encoder = radeon_encoder; |
- | |
217 | - | ||
218 | backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); |
222 | pdata->encoder = radeon_encoder; |
219 | 223 | ||
Line 220... | Line 224... | ||
220 | dig = radeon_encoder->enc_priv; |
224 | dig = radeon_encoder->enc_priv; |
- | 225 | dig->bl_dev = bd; |
|
- | 226 | ||
- | 227 | bd->props.brightness = radeon_atom_backlight_get_brightness(bd); |
|
- | 228 | /* Set a reasonable default here if the level is 0 otherwise |
|
- | 229 | * fbdev will attempt to turn the backlight on after console |
|
- | 230 | * unblanking and it will try and restore 0 which turns the backlight |
|
- | 231 | * off again. |
|
221 | dig->bl_dev = bd; |
232 | */ |
222 | 233 | if (bd->props.brightness == 0) |
|
Line 223... | Line 234... | ||
223 | bd->props.brightness = radeon_atom_backlight_get_brightness(bd); |
234 | bd->props.brightness = RADEON_MAX_BL_LEVEL; |
Line 294... | Line 305... | ||
294 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
305 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
295 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
306 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
296 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
307 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
297 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
308 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
298 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
309 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
- | 310 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
|
299 | return true; |
311 | return true; |
300 | default: |
312 | default: |
301 | return false; |
313 | return false; |
302 | } |
314 | } |
303 | } |
315 | } |
Line 317... | Line 329... | ||
317 | /* hw bug */ |
329 | /* hw bug */ |
318 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
330 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
319 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
331 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
320 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
332 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
Line 321... | Line 333... | ||
321 | 333 | ||
322 | /* get the native mode for LVDS */ |
334 | /* get the native mode for scaling */ |
323 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT|ATOM_DEVICE_DFP_SUPPORT)) |
335 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT|ATOM_DEVICE_DFP_SUPPORT)) { |
324 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
- | |
325 | - | ||
326 | /* get the native mode for TV */ |
336 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
327 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
337 | } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
328 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
338 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
329 | if (tv_dac) { |
339 | if (tv_dac) { |
330 | if (tv_dac->tv_std == TV_STD_NTSC || |
340 | if (tv_dac->tv_std == TV_STD_NTSC || |
331 | tv_dac->tv_std == TV_STD_NTSC_J || |
341 | tv_dac->tv_std == TV_STD_NTSC_J || |
332 | tv_dac->tv_std == TV_STD_PAL_M) |
342 | tv_dac->tv_std == TV_STD_PAL_M) |
333 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
343 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
334 | else |
344 | else |
335 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
345 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
- | 346 | } |
|
- | 347 | } else if (radeon_encoder->rmx_type != RMX_OFF) { |
|
336 | } |
348 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
Line 337... | Line 349... | ||
337 | } |
349 | } |
338 | 350 | ||
339 | if (ASIC_IS_DCE3(rdev) && |
351 | if (ASIC_IS_DCE3(rdev) && |
Line 454... | Line 466... | ||
454 | 466 | ||
Line 455... | Line 467... | ||
455 | } |
467 | } |
456 | 468 | ||
457 | static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) |
- | |
458 | { |
469 | static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) |
Line 459... | Line 470... | ||
459 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
470 | { |
- | 471 | int bpc = 8; |
|
460 | int bpc = 8; |
472 | |
- | 473 | if (encoder->crtc) { |
|
Line 461... | Line 474... | ||
461 | 474 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
|
462 | if (connector) |
475 | bpc = radeon_crtc->bpc; |
463 | bpc = radeon_get_monitor_bpc(connector); |
476 | } |
464 | 477 | ||
Line 477... | Line 490... | ||
477 | case 16: |
490 | case 16: |
478 | return PANEL_16BIT_PER_COLOR; |
491 | return PANEL_16BIT_PER_COLOR; |
479 | } |
492 | } |
480 | } |
493 | } |
Line 481... | Line -... | ||
481 | - | ||
482 | 494 | ||
483 | union dvo_encoder_control { |
495 | union dvo_encoder_control { |
484 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; |
496 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; |
485 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; |
497 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; |
- | 498 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; |
|
486 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; |
499 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; |
Line 487... | Line 500... | ||
487 | }; |
500 | }; |
488 | 501 | ||
489 | void |
502 | void |
Line 531... | Line 544... | ||
531 | /* R6xx */ |
544 | /* R6xx */ |
532 | args.dvo_v3.ucAction = action; |
545 | args.dvo_v3.ucAction = action; |
533 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
546 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
534 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ |
547 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ |
535 | break; |
548 | break; |
- | 549 | case 4: |
|
- | 550 | /* DCE8 */ |
|
- | 551 | args.dvo_v4.ucAction = action; |
|
- | 552 | args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
|
- | 553 | args.dvo_v4.ucDVOConfig = 0; /* XXX */ |
|
- | 554 | args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
|
- | 555 | break; |
|
536 | default: |
556 | default: |
537 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
557 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
538 | break; |
558 | break; |
539 | } |
559 | } |
540 | break; |
560 | break; |
Line 665... | Line 685... | ||
665 | } |
685 | } |
Line 666... | Line 686... | ||
666 | 686 | ||
667 | int |
687 | int |
668 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
688 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
669 | { |
- | |
670 | struct drm_device *dev = encoder->dev; |
- | |
671 | struct radeon_device *rdev = dev->dev_private; |
689 | { |
672 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
690 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
673 | struct drm_connector *connector; |
691 | struct drm_connector *connector; |
674 | struct radeon_connector *radeon_connector; |
692 | struct radeon_connector *radeon_connector; |
Line 692... | Line 710... | ||
692 | radeon_connector = to_radeon_connector(connector); |
710 | radeon_connector = to_radeon_connector(connector); |
Line 693... | Line 711... | ||
693 | 711 | ||
694 | switch (connector->connector_type) { |
712 | switch (connector->connector_type) { |
695 | case DRM_MODE_CONNECTOR_DVII: |
713 | case DRM_MODE_CONNECTOR_DVII: |
- | 714 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
|
696 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
715 | if (radeon_audio != 0) { |
697 | if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
716 | if (radeon_connector->use_digital && |
- | 717 | (radeon_connector->audio == RADEON_AUDIO_ENABLE)) |
|
698 | radeon_audio && |
718 | return ATOM_ENCODER_MODE_HDMI; |
- | 719 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
|
699 | !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ |
720 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
700 | return ATOM_ENCODER_MODE_HDMI; |
721 | return ATOM_ENCODER_MODE_HDMI; |
701 | else if (radeon_connector->use_digital) |
722 | else if (radeon_connector->use_digital) |
702 | return ATOM_ENCODER_MODE_DVI; |
723 | return ATOM_ENCODER_MODE_DVI; |
703 | else |
724 | else |
- | 725 | return ATOM_ENCODER_MODE_CRT; |
|
- | 726 | } else if (radeon_connector->use_digital) { |
|
- | 727 | return ATOM_ENCODER_MODE_DVI; |
|
- | 728 | } else { |
|
- | 729 | return ATOM_ENCODER_MODE_CRT; |
|
704 | return ATOM_ENCODER_MODE_CRT; |
730 | } |
705 | break; |
731 | break; |
706 | case DRM_MODE_CONNECTOR_DVID: |
732 | case DRM_MODE_CONNECTOR_DVID: |
707 | case DRM_MODE_CONNECTOR_HDMIA: |
733 | case DRM_MODE_CONNECTOR_HDMIA: |
- | 734 | default: |
|
708 | default: |
735 | if (radeon_audio != 0) { |
709 | if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
736 | if (radeon_connector->audio == RADEON_AUDIO_ENABLE) |
710 | radeon_audio && |
737 | return ATOM_ENCODER_MODE_HDMI; |
- | 738 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
|
711 | !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ |
739 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
712 | return ATOM_ENCODER_MODE_HDMI; |
740 | return ATOM_ENCODER_MODE_HDMI; |
713 | else |
741 | else |
- | 742 | return ATOM_ENCODER_MODE_DVI; |
|
- | 743 | } else { |
|
- | 744 | return ATOM_ENCODER_MODE_DVI; |
|
714 | return ATOM_ENCODER_MODE_DVI; |
745 | } |
715 | break; |
746 | break; |
716 | case DRM_MODE_CONNECTOR_LVDS: |
747 | case DRM_MODE_CONNECTOR_LVDS: |
717 | return ATOM_ENCODER_MODE_LVDS; |
748 | return ATOM_ENCODER_MODE_LVDS; |
718 | break; |
749 | break; |
719 | case DRM_MODE_CONNECTOR_DisplayPort: |
750 | case DRM_MODE_CONNECTOR_DisplayPort: |
720 | dig_connector = radeon_connector->con_priv; |
751 | dig_connector = radeon_connector->con_priv; |
721 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
752 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
722 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) |
753 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
- | 754 | return ATOM_ENCODER_MODE_DP; |
|
723 | return ATOM_ENCODER_MODE_DP; |
755 | } else if (radeon_audio != 0) { |
724 | else if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
756 | if (radeon_connector->audio == RADEON_AUDIO_ENABLE) |
725 | radeon_audio && |
757 | return ATOM_ENCODER_MODE_HDMI; |
- | 758 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
|
726 | !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ |
759 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
727 | return ATOM_ENCODER_MODE_HDMI; |
760 | return ATOM_ENCODER_MODE_HDMI; |
728 | else |
761 | else |
- | 762 | return ATOM_ENCODER_MODE_DVI; |
|
- | 763 | } else { |
|
- | 764 | return ATOM_ENCODER_MODE_DVI; |
|
729 | return ATOM_ENCODER_MODE_DVI; |
765 | } |
730 | break; |
766 | break; |
731 | case DRM_MODE_CONNECTOR_eDP: |
767 | case DRM_MODE_CONNECTOR_eDP: |
732 | return ATOM_ENCODER_MODE_DP; |
768 | return ATOM_ENCODER_MODE_DP; |
733 | case DRM_MODE_CONNECTOR_DVIA: |
769 | case DRM_MODE_CONNECTOR_DVIA: |
Line 913... | Line 949... | ||
913 | args.v4.ucLaneNum = 8; |
949 | args.v4.ucLaneNum = 8; |
914 | else |
950 | else |
915 | args.v4.ucLaneNum = 4; |
951 | args.v4.ucLaneNum = 4; |
Line 916... | Line 952... | ||
916 | 952 | ||
917 | if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { |
953 | if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { |
918 | if (dp_clock == 270000) |
- | |
919 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; |
- | |
920 | else if (dp_clock == 540000) |
954 | if (dp_clock == 540000) |
- | 955 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
|
- | 956 | else if (dp_clock == 324000) |
|
- | 957 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; |
|
- | 958 | else if (dp_clock == 270000) |
|
- | 959 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; |
|
- | 960 | else |
|
921 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
961 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; |
922 | } |
962 | } |
923 | args.v4.acConfig.ucDigSel = dig->dig_encoder; |
963 | args.v4.acConfig.ucDigSel = dig->dig_encoder; |
924 | args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
964 | args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
925 | if (hpd_id == RADEON_HPD_NONE) |
965 | if (hpd_id == RADEON_HPD_NONE) |
Line 1010... | Line 1050... | ||
1010 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1050 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1011 | break; |
1051 | break; |
1012 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1052 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1013 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1053 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1014 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1054 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
- | 1055 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
|
1015 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
1056 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
1016 | break; |
1057 | break; |
1017 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1058 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1018 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); |
1059 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); |
1019 | break; |
1060 | break; |
Line 1269... | Line 1310... | ||
1269 | if (dig->linkb) |
1310 | if (dig->linkb) |
1270 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; |
1311 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; |
1271 | else |
1312 | else |
1272 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; |
1313 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; |
1273 | break; |
1314 | break; |
- | 1315 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
|
- | 1316 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; |
|
- | 1317 | break; |
|
1274 | } |
1318 | } |
1275 | if (is_dp) |
1319 | if (is_dp) |
1276 | args.v5.ucLaneNum = dp_lane_count; |
1320 | args.v5.ucLaneNum = dp_lane_count; |
1277 | else if (radeon_encoder->pixel_clock > 165000) |
1321 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1278 | args.v5.ucLaneNum = 8; |
1322 | args.v5.ucLaneNum = 8; |
1279 | else |
1323 | else |
1280 | args.v5.ucLaneNum = 4; |
1324 | args.v5.ucLaneNum = 4; |
1281 | args.v5.ucConnObjId = connector_object_id; |
1325 | args.v5.ucConnObjId = connector_object_id; |
1282 | args.v5.ucDigMode = atombios_get_encoder_mode(encoder); |
1326 | args.v5.ucDigMode = atombios_get_encoder_mode(encoder); |
Line 1591... | Line 1635... | ||
1591 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
1635 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
1592 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
1636 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
1593 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1637 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1594 | struct radeon_connector *radeon_connector = NULL; |
1638 | struct radeon_connector *radeon_connector = NULL; |
1595 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; |
1639 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; |
- | 1640 | bool travis_quirk = false; |
|
Line 1596... | Line 1641... | ||
1596 | 1641 | ||
1597 | if (connector) { |
1642 | if (connector) { |
1598 | radeon_connector = to_radeon_connector(connector); |
1643 | radeon_connector = to_radeon_connector(connector); |
- | 1644 | radeon_dig_connector = radeon_connector->con_priv; |
|
- | 1645 | if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
|
- | 1646 | ENCODER_OBJECT_ID_TRAVIS) && |
|
- | 1647 | (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && |
|
- | 1648 | !ASIC_IS_DCE5(rdev)) |
|
1599 | radeon_dig_connector = radeon_connector->con_priv; |
1649 | travis_quirk = true; |
Line 1600... | Line 1650... | ||
1600 | } |
1650 | } |
1601 | 1651 | ||
1602 | switch (mode) { |
1652 | switch (mode) { |
Line 1615... | Line 1665... | ||
1615 | if (ext_encoder) { |
1665 | if (ext_encoder) { |
1616 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) |
1666 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) |
1617 | atombios_external_encoder_setup(encoder, ext_encoder, |
1667 | atombios_external_encoder_setup(encoder, ext_encoder, |
1618 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); |
1668 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); |
1619 | } |
1669 | } |
1620 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
- | |
1621 | } else if (ASIC_IS_DCE4(rdev)) { |
1670 | } else if (ASIC_IS_DCE4(rdev)) { |
1622 | /* setup and enable the encoder */ |
1671 | /* setup and enable the encoder */ |
1623 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
1672 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
1624 | /* enable the transmitter */ |
- | |
1625 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
- | |
1626 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
- | |
1627 | } else { |
1673 | } else { |
1628 | /* setup and enable the encoder and transmitter */ |
1674 | /* setup and enable the encoder and transmitter */ |
1629 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); |
1675 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); |
1630 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
1676 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
1631 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
- | |
1632 | /* some early dce3.2 boards have a bug in their transmitter control table */ |
- | |
1633 | if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730)) |
- | |
1634 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
- | |
1635 | } |
1677 | } |
1636 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1678 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1637 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1679 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1638 | atombios_set_edp_panel_power(connector, |
1680 | atombios_set_edp_panel_power(connector, |
1639 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
1681 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
1640 | radeon_dig_connector->edp_on = true; |
1682 | radeon_dig_connector->edp_on = true; |
1641 | } |
1683 | } |
- | 1684 | } |
|
- | 1685 | /* enable the transmitter */ |
|
- | 1686 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
|
- | 1687 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
|
- | 1688 | /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ |
|
1642 | radeon_dp_link_train(encoder, connector); |
1689 | radeon_dp_link_train(encoder, connector); |
1643 | if (ASIC_IS_DCE4(rdev)) |
1690 | if (ASIC_IS_DCE4(rdev)) |
1644 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); |
1691 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); |
1645 | } |
1692 | } |
1646 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1693 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
- | 1694 | atombios_dig_transmitter_setup(encoder, |
|
1647 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
1695 | ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
- | 1696 | if (ext_encoder) |
|
- | 1697 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
|
1648 | break; |
1698 | break; |
1649 | case DRM_MODE_DPMS_STANDBY: |
1699 | case DRM_MODE_DPMS_STANDBY: |
1650 | case DRM_MODE_DPMS_SUSPEND: |
1700 | case DRM_MODE_DPMS_SUSPEND: |
1651 | case DRM_MODE_DPMS_OFF: |
1701 | case DRM_MODE_DPMS_OFF: |
1652 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
1702 | if (ASIC_IS_DCE4(rdev)) { |
- | 1703 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) |
|
- | 1704 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
|
- | 1705 | } |
|
1653 | /* disable the transmitter */ |
1706 | if (ext_encoder) |
1654 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1707 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); |
- | 1708 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
|
- | 1709 | atombios_dig_transmitter_setup(encoder, |
|
- | 1710 | ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
|
- | 1711 | ||
- | 1712 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && |
|
- | 1713 | connector && !travis_quirk) |
|
- | 1714 | radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); |
|
1655 | } else if (ASIC_IS_DCE4(rdev)) { |
1715 | if (ASIC_IS_DCE4(rdev)) { |
1656 | /* disable the transmitter */ |
1716 | /* disable the transmitter */ |
1657 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
1717 | atombios_dig_transmitter_setup(encoder, |
1658 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1718 | ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1659 | } else { |
1719 | } else { |
1660 | /* disable the encoder and transmitter */ |
1720 | /* disable the encoder and transmitter */ |
1661 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
1721 | atombios_dig_transmitter_setup(encoder, |
1662 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1722 | ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1663 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
1723 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
1664 | } |
1724 | } |
1665 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1725 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1666 | if (ASIC_IS_DCE4(rdev)) |
1726 | if (travis_quirk) |
1667 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
1727 | radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); |
1668 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1728 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1669 | atombios_set_edp_panel_power(connector, |
1729 | atombios_set_edp_panel_power(connector, |
1670 | ATOM_TRANSMITTER_ACTION_POWER_OFF); |
1730 | ATOM_TRANSMITTER_ACTION_POWER_OFF); |
1671 | radeon_dig_connector->edp_on = false; |
1731 | radeon_dig_connector->edp_on = false; |
1672 | } |
1732 | } |
1673 | } |
1733 | } |
1674 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
- | |
1675 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
- | |
1676 | break; |
- | |
1677 | } |
- | |
1678 | } |
- | |
1679 | - | ||
1680 | static void |
- | |
1681 | radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, |
- | |
1682 | struct drm_encoder *ext_encoder, |
- | |
1683 | int mode) |
- | |
1684 | { |
- | |
1685 | struct drm_device *dev = encoder->dev; |
- | |
1686 | struct radeon_device *rdev = dev->dev_private; |
- | |
1687 | - | ||
1688 | switch (mode) { |
- | |
1689 | case DRM_MODE_DPMS_ON: |
- | |
1690 | default: |
- | |
1691 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { |
- | |
1692 | atombios_external_encoder_setup(encoder, ext_encoder, |
- | |
1693 | EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); |
- | |
1694 | atombios_external_encoder_setup(encoder, ext_encoder, |
- | |
1695 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); |
- | |
1696 | } else |
- | |
1697 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
- | |
1698 | break; |
- | |
1699 | case DRM_MODE_DPMS_STANDBY: |
- | |
1700 | case DRM_MODE_DPMS_SUSPEND: |
- | |
1701 | case DRM_MODE_DPMS_OFF: |
- | |
1702 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { |
- | |
1703 | atombios_external_encoder_setup(encoder, ext_encoder, |
- | |
1704 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); |
- | |
1705 | atombios_external_encoder_setup(encoder, ext_encoder, |
- | |
1706 | EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); |
- | |
1707 | } else |
- | |
1708 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); |
- | |
1709 | break; |
1734 | break; |
1710 | } |
1735 | } |
1711 | } |
1736 | } |
Line 1712... | Line 1737... | ||
1712 | 1737 | ||
1713 | static void |
1738 | static void |
1714 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
1739 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
1715 | { |
1740 | { |
1716 | struct drm_device *dev = encoder->dev; |
1741 | struct drm_device *dev = encoder->dev; |
1717 | struct radeon_device *rdev = dev->dev_private; |
1742 | struct radeon_device *rdev = dev->dev_private; |
1718 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
- | |
Line 1719... | Line 1743... | ||
1719 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
1743 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1720 | 1744 | ||
1721 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1745 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1722 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1746 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
Line 1733... | Line 1757... | ||
1733 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
1757 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
1734 | break; |
1758 | break; |
1735 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1759 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1736 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1760 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1737 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1761 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
- | 1762 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
|
1738 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1763 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1739 | radeon_atom_encoder_dpms_dig(encoder, mode); |
1764 | radeon_atom_encoder_dpms_dig(encoder, mode); |
1740 | break; |
1765 | break; |
1741 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1766 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1742 | if (ASIC_IS_DCE5(rdev)) { |
1767 | if (ASIC_IS_DCE5(rdev)) { |
Line 1773... | Line 1798... | ||
1773 | break; |
1798 | break; |
1774 | default: |
1799 | default: |
1775 | return; |
1800 | return; |
1776 | } |
1801 | } |
Line 1777... | Line -... | ||
1777 | - | ||
1778 | if (ext_encoder) |
- | |
1779 | radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); |
- | |
1780 | 1802 | ||
Line 1781... | Line 1803... | ||
1781 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
1803 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Line 1782... | Line 1804... | ||
1782 | 1804 | ||
Line 1864... | Line 1886... | ||
1864 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; |
1886 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; |
1865 | else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) |
1887 | else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) |
1866 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; |
1888 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; |
1867 | else |
1889 | else |
1868 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1890 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
- | 1891 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
|
- | 1892 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; |
|
1869 | } else |
1893 | } else { |
1870 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1894 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
- | 1895 | } |
|
1871 | switch (radeon_encoder->encoder_id) { |
1896 | switch (radeon_encoder->encoder_id) { |
1872 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1897 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1873 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1898 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1874 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1899 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
- | 1900 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
|
1875 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1901 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1876 | dig = radeon_encoder->enc_priv; |
1902 | dig = radeon_encoder->enc_priv; |
1877 | switch (dig->dig_encoder) { |
1903 | switch (dig->dig_encoder) { |
1878 | case 0: |
1904 | case 0: |
1879 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1905 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
Line 1891... | Line 1917... | ||
1891 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; |
1917 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; |
1892 | break; |
1918 | break; |
1893 | case 5: |
1919 | case 5: |
1894 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; |
1920 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; |
1895 | break; |
1921 | break; |
- | 1922 | case 6: |
|
- | 1923 | args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; |
|
- | 1924 | break; |
|
1896 | } |
1925 | } |
1897 | break; |
1926 | break; |
1898 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1927 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1899 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
1928 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
1900 | break; |
1929 | break; |
Line 1953... | Line 1982... | ||
1953 | } |
1982 | } |
Line 1954... | Line 1983... | ||
1954 | 1983 | ||
1955 | /* set scaler clears this on some chips */ |
1984 | /* set scaler clears this on some chips */ |
1956 | if (ASIC_IS_AVIVO(rdev) && |
1985 | if (ASIC_IS_AVIVO(rdev) && |
1957 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { |
1986 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { |
- | 1987 | if (ASIC_IS_DCE8(rdev)) { |
|
- | 1988 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
|
- | 1989 | WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, |
|
- | 1990 | CIK_INTERLEAVE_EN); |
|
- | 1991 | else |
|
- | 1992 | WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
|
1958 | if (ASIC_IS_DCE4(rdev)) { |
1993 | } else if (ASIC_IS_DCE4(rdev)) { |
1959 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1994 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1960 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
1995 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
1961 | EVERGREEN_INTERLEAVE_EN); |
1996 | EVERGREEN_INTERLEAVE_EN); |
1962 | else |
1997 | else |
Line 2000... | Line 2035... | ||
2000 | if (dig->linkb) |
2035 | if (dig->linkb) |
2001 | return 5; |
2036 | return 5; |
2002 | else |
2037 | else |
2003 | return 4; |
2038 | return 4; |
2004 | break; |
2039 | break; |
- | 2040 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
|
- | 2041 | return 6; |
|
- | 2042 | break; |
|
2005 | } |
2043 | } |
2006 | } else if (ASIC_IS_DCE4(rdev)) { |
2044 | } else if (ASIC_IS_DCE4(rdev)) { |
2007 | /* DCE4/5 */ |
2045 | /* DCE4/5 */ |
2008 | if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { |
2046 | if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { |
2009 | /* ontario follows DCE4 */ |
2047 | /* ontario follows DCE4 */ |
Line 2084... | Line 2122... | ||
2084 | 2122 | ||
2085 | switch (radeon_encoder->encoder_id) { |
2123 | switch (radeon_encoder->encoder_id) { |
2086 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2124 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2087 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2125 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
- | 2126 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
|
2088 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2127 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2089 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2128 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2090 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
2129 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
2091 | break; |
2130 | break; |
2092 | default: |
2131 | default: |
Line 2128... | Line 2167... | ||
2128 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
2167 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
2129 | break; |
2168 | break; |
2130 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2169 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2131 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2132 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2171 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
- | 2172 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
|
2133 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2173 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2134 | /* handled in dpms */ |
2174 | /* handled in dpms */ |
2135 | break; |
2175 | break; |
2136 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2176 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2137 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2177 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
Line 2349... | Line 2389... | ||
2349 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
2389 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
2350 | } |
2390 | } |
Line 2351... | Line 2391... | ||
2351 | 2391 | ||
2352 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
2392 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
- | 2393 | atombios_set_encoder_crtc_source(encoder); |
|
- | 2394 | /* set up the FMT blocks */ |
|
- | 2395 | if (ASIC_IS_DCE8(rdev)) |
|
- | 2396 | dce8_program_fmt(encoder); |
|
- | 2397 | else if (ASIC_IS_DCE4(rdev)) |
|
- | 2398 | dce4_program_fmt(encoder); |
|
- | 2399 | else if (ASIC_IS_DCE3(rdev)) |
|
- | 2400 | dce3_program_fmt(encoder); |
|
- | 2401 | else if (ASIC_IS_AVIVO(rdev)) |
|
2353 | atombios_set_encoder_crtc_source(encoder); |
2402 | avivo_program_fmt(encoder); |
Line 2354... | Line 2403... | ||
2354 | } |
2403 | } |
2355 | 2404 | ||
2356 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
2405 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
Line 2393... | Line 2442... | ||
2393 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); |
2442 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); |
2394 | break; |
2443 | break; |
2395 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2444 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2396 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2445 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2397 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2446 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
- | 2447 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
|
2398 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2448 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2399 | /* handled in dpms */ |
2449 | /* handled in dpms */ |
2400 | break; |
2450 | break; |
2401 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2451 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2402 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2452 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
Line 2624... | Line 2674... | ||
2624 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2674 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2625 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2675 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2626 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2676 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2627 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2677 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2628 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2678 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
- | 2679 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
|
2629 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2680 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2630 | radeon_encoder->rmx_type = RMX_FULL; |
2681 | radeon_encoder->rmx_type = RMX_FULL; |
2631 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2682 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2632 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2683 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2633 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
2684 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |