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Rev 5271 | Rev 6104 | ||
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Line 156... | Line 156... | ||
156 | 156 | ||
157 | #define BARE_ADDRESS_SIZE 3 |
157 | #define BARE_ADDRESS_SIZE 3 |
Line 158... | Line 158... | ||
158 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
158 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
159 | 159 | ||
160 | static ssize_t |
160 | static ssize_t |
161 | radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
161 | radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
162 | { |
162 | { |
163 | struct radeon_i2c_chan *chan = |
163 | struct radeon_i2c_chan *chan = |
164 | container_of(aux, struct radeon_i2c_chan, aux); |
164 | container_of(aux, struct radeon_i2c_chan, aux); |
Line 169... | Line 169... | ||
169 | 169 | ||
170 | if (WARN_ON(msg->size > 16)) |
170 | if (WARN_ON(msg->size > 16)) |
Line 171... | Line 171... | ||
171 | return -E2BIG; |
171 | return -E2BIG; |
172 | 172 | ||
173 | tx_buf[0] = msg->address & 0xff; |
173 | tx_buf[0] = msg->address & 0xff; |
- | 174 | tx_buf[1] = (msg->address >> 8) & 0xff; |
|
174 | tx_buf[1] = msg->address >> 8; |
175 | tx_buf[2] = (msg->request << 4) | |
Line 175... | Line 176... | ||
175 | tx_buf[2] = msg->request << 4; |
176 | ((msg->address >> 16) & 0xf); |
176 | tx_buf[3] = msg->size ? (msg->size - 1) : 0; |
177 | tx_buf[3] = msg->size ? (msg->size - 1) : 0; |
177 | 178 | ||
- | 179 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
|
- | 180 | case DP_AUX_NATIVE_WRITE: |
|
- | 181 | case DP_AUX_I2C_WRITE: |
|
- | 182 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
|
- | 183 | /* The atom implementation only supports writes with a max payload of |
|
- | 184 | * 12 bytes since it uses 4 bits for the total count (header + payload) |
|
- | 185 | * in the parameter space. The atom interface supports 16 byte |
|
- | 186 | * payloads for reads. The hw itself supports up to 16 bytes of payload. |
|
178 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
187 | */ |
179 | case DP_AUX_NATIVE_WRITE: |
188 | if (WARN_ON_ONCE(msg->size > 12)) |
180 | case DP_AUX_I2C_WRITE: |
189 | return -E2BIG; |
181 | /* tx_size needs to be 4 even for bare address packets since the atom |
190 | /* tx_size needs to be 4 even for bare address packets since the atom |
182 | * table needs the info in tx_buf[3]. |
191 | * table needs the info in tx_buf[3]. |
Line 217... | Line 226... | ||
217 | return ret; |
226 | return ret; |
218 | } |
227 | } |
Line 219... | Line 228... | ||
219 | 228 | ||
220 | void radeon_dp_aux_init(struct radeon_connector *radeon_connector) |
229 | void radeon_dp_aux_init(struct radeon_connector *radeon_connector) |
- | 230 | { |
|
- | 231 | struct drm_device *dev = radeon_connector->base.dev; |
|
221 | { |
232 | struct radeon_device *rdev = dev->dev_private; |
Line 222... | Line 233... | ||
222 | int ret; |
233 | int ret; |
223 | 234 | ||
- | 235 | radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; |
|
- | 236 | radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; |
|
- | 237 | if (ASIC_IS_DCE5(rdev)) { |
|
- | 238 | if (radeon_auxch) |
|
- | 239 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; |
|
- | 240 | else |
|
224 | radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; |
241 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; |
- | 242 | } else { |
|
Line 225... | Line 243... | ||
225 | radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; |
243 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; |
226 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer; |
244 | } |
227 | 245 | ||
Line 235... | Line 253... | ||
235 | /***** general DP utility functions *****/ |
253 | /***** general DP utility functions *****/ |
Line 236... | Line 254... | ||
236 | 254 | ||
237 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 |
255 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 |
Line 238... | Line 256... | ||
238 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 |
256 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 |
239 | 257 | ||
240 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], |
258 | static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], |
241 | int lane_count, |
259 | int lane_count, |
242 | u8 train_set[4]) |
260 | u8 train_set[4]) |
243 | { |
261 | { |
Line 292... | Line 310... | ||
292 | return (link_rate * lane_num * 8) / bpp; |
310 | return (link_rate * lane_num * 8) / bpp; |
293 | } |
311 | } |
Line 294... | Line 312... | ||
294 | 312 | ||
Line 295... | Line 313... | ||
295 | /***** radeon specific DP functions *****/ |
313 | /***** radeon specific DP functions *****/ |
296 | 314 | ||
297 | static int radeon_dp_get_max_link_rate(struct drm_connector *connector, |
315 | int radeon_dp_get_max_link_rate(struct drm_connector *connector, |
298 | u8 dpcd[DP_DPCD_SIZE]) |
316 | const u8 dpcd[DP_DPCD_SIZE]) |
Line 299... | Line 317... | ||
299 | { |
317 | { |
300 | int max_link_rate; |
318 | int max_link_rate; |
Line 310... | Line 328... | ||
310 | /* First get the min lane# when low rate is used according to pixel clock |
328 | /* First get the min lane# when low rate is used according to pixel clock |
311 | * (prefer low rate), second check max lane# supported by DP panel, |
329 | * (prefer low rate), second check max lane# supported by DP panel, |
312 | * if the max lane# < low rate lane# then use max lane# instead. |
330 | * if the max lane# < low rate lane# then use max lane# instead. |
313 | */ |
331 | */ |
314 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, |
332 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, |
315 | u8 dpcd[DP_DPCD_SIZE], |
333 | const u8 dpcd[DP_DPCD_SIZE], |
316 | int pix_clock) |
334 | int pix_clock) |
317 | { |
335 | { |
318 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
336 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
319 | int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); |
337 | int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); |
320 | int max_lane_num = drm_dp_max_lane_count(dpcd); |
338 | int max_lane_num = drm_dp_max_lane_count(dpcd); |
Line 329... | Line 347... | ||
329 | 347 | ||
330 | return lane_num; |
348 | return lane_num; |
Line 331... | Line 349... | ||
331 | } |
349 | } |
332 | 350 | ||
333 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
351 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
334 | u8 dpcd[DP_DPCD_SIZE], |
352 | const u8 dpcd[DP_DPCD_SIZE], |
335 | int pix_clock) |
353 | int pix_clock) |
336 | { |
354 | { |
Line 403... | Line 421... | ||
403 | 421 | ||
404 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
422 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
405 | { |
423 | { |
406 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
424 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
407 | u8 msg[DP_DPCD_SIZE]; |
425 | u8 msg[DP_DPCD_SIZE]; |
Line -... | Line 426... | ||
- | 426 | int ret, i; |
|
408 | int ret; |
427 | |
409 | 428 | for (i = 0; i < 7; i++) { |
|
410 | ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, |
429 | ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, |
411 | DP_DPCD_SIZE); |
430 | DP_DPCD_SIZE); |
Line 412... | Line 431... | ||
412 | if (ret > 0) { |
431 | if (ret == DP_DPCD_SIZE) { |
413 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
432 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
Line 414... | Line 433... | ||
414 | 433 | ||
Line 415... | Line 434... | ||
415 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), |
434 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), |
416 | dig_connector->dpcd); |
435 | dig_connector->dpcd); |
- | 436 | ||
417 | 437 | radeon_dp_probe_oui(radeon_connector); |
|
418 | radeon_dp_probe_oui(radeon_connector); |
438 | |
419 | 439 | return true; |
|
Line 420... | Line 440... | ||
420 | return true; |
440 | } |
Line 490... | Line 510... | ||
490 | { |
510 | { |
491 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
511 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
492 | struct radeon_connector_atom_dig *dig_connector; |
512 | struct radeon_connector_atom_dig *dig_connector; |
493 | int dp_clock; |
513 | int dp_clock; |
Line -... | Line 514... | ||
- | 514 | ||
- | 515 | if ((mode->clock > 340000) && |
|
- | 516 | (!radeon_connector_is_dp12_capable(connector))) |
|
- | 517 | return MODE_CLOCK_HIGH; |
|
494 | 518 | ||
495 | if (!radeon_connector->con_priv) |
519 | if (!radeon_connector->con_priv) |
496 | return MODE_CLOCK_HIGH; |
520 | return MODE_CLOCK_HIGH; |
Line 497... | Line 521... | ||
497 | dig_connector = radeon_connector->con_priv; |
521 | dig_connector = radeon_connector->con_priv; |
Line 617... | Line 641... | ||
617 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
641 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
618 | else |
642 | else |
619 | drm_dp_dpcd_writeb(dp_info->aux, |
643 | drm_dp_dpcd_writeb(dp_info->aux, |
620 | DP_DOWNSPREAD_CTRL, 0); |
644 | DP_DOWNSPREAD_CTRL, 0); |
Line 621... | Line -... | ||
621 | - | ||
622 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
645 | |
623 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { |
646 | if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) |
624 | drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); |
- | |
Line 625... | Line 647... | ||
625 | } |
647 | drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); |
626 | 648 | ||
627 | /* set the lane count on the sink */ |
649 | /* set the lane count on the sink */ |
628 | tmp = dp_info->dp_lane_count; |
650 | tmp = dp_info->dp_lane_count; |