Rev 1963 | Rev 2997 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1963 | Rev 2160 | ||
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Line 625... | Line 625... | ||
625 | bool tp3_supported; |
625 | bool tp3_supported; |
626 | u8 dpcd[8]; |
626 | u8 dpcd[8]; |
627 | u8 train_set[4]; |
627 | u8 train_set[4]; |
628 | u8 link_status[DP_LINK_STATUS_SIZE]; |
628 | u8 link_status[DP_LINK_STATUS_SIZE]; |
629 | u8 tries; |
629 | u8 tries; |
- | 630 | bool use_dpencoder; |
|
630 | }; |
631 | }; |
Line 631... | Line 632... | ||
631 | 632 | ||
632 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
633 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
633 | { |
634 | { |
Line 644... | Line 645... | ||
644 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
645 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
645 | { |
646 | { |
646 | int rtp = 0; |
647 | int rtp = 0; |
Line 647... | Line 648... | ||
647 | 648 | ||
648 | /* set training pattern on the source */ |
649 | /* set training pattern on the source */ |
649 | if (ASIC_IS_DCE4(dp_info->rdev)) { |
650 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
650 | switch (tp) { |
651 | switch (tp) { |
651 | case DP_TRAINING_PATTERN_1: |
652 | case DP_TRAINING_PATTERN_1: |
652 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; |
653 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; |
653 | break; |
654 | break; |
Line 704... | Line 705... | ||
704 | /* set the link rate on the sink */ |
705 | /* set the link rate on the sink */ |
705 | tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock); |
706 | tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock); |
706 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); |
707 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); |
Line 707... | Line 708... | ||
707 | 708 | ||
708 | /* start training on the source */ |
709 | /* start training on the source */ |
709 | if (ASIC_IS_DCE4(dp_info->rdev)) |
710 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
710 | atombios_dig_encoder_setup(dp_info->encoder, |
711 | atombios_dig_encoder_setup(dp_info->encoder, |
711 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); |
712 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); |
712 | else |
713 | else |
713 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
714 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
Line 729... | Line 730... | ||
729 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
730 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
730 | DP_TRAINING_PATTERN_SET, |
731 | DP_TRAINING_PATTERN_SET, |
731 | DP_TRAINING_PATTERN_DISABLE); |
732 | DP_TRAINING_PATTERN_DISABLE); |
Line 732... | Line 733... | ||
732 | 733 | ||
733 | /* disable the training pattern on the source */ |
734 | /* disable the training pattern on the source */ |
734 | if (ASIC_IS_DCE4(dp_info->rdev)) |
735 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
735 | atombios_dig_encoder_setup(dp_info->encoder, |
736 | atombios_dig_encoder_setup(dp_info->encoder, |
736 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); |
737 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); |
737 | else |
738 | else |
738 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, |
739 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, |
Line 867... | Line 868... | ||
867 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
868 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
868 | struct radeon_encoder_atom_dig *dig; |
869 | struct radeon_encoder_atom_dig *dig; |
869 | struct radeon_connector *radeon_connector; |
870 | struct radeon_connector *radeon_connector; |
870 | struct radeon_connector_atom_dig *dig_connector; |
871 | struct radeon_connector_atom_dig *dig_connector; |
871 | struct radeon_dp_link_train_info dp_info; |
872 | struct radeon_dp_link_train_info dp_info; |
872 | u8 tmp; |
873 | int index; |
- | 874 | u8 tmp, frev, crev; |
|
Line 873... | Line 875... | ||
873 | 875 | ||
874 | if (!radeon_encoder->enc_priv) |
876 | if (!radeon_encoder->enc_priv) |
875 | return; |
877 | return; |
Line 882... | Line 884... | ||
882 | 884 | ||
883 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
885 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
884 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) |
886 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) |
Line -... | Line 887... | ||
- | 887 | return; |
|
- | 888 | ||
- | 889 | /* DPEncoderService newer than 1.1 can't program properly the |
|
- | 890 | * training pattern. When facing such version use the |
|
- | 891 | * DIGXEncoderControl (X== 1 | 2) |
|
- | 892 | */ |
|
- | 893 | dp_info.use_dpencoder = true; |
|
- | 894 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
|
- | 895 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { |
|
- | 896 | if (crev > 1) { |
|
- | 897 | dp_info.use_dpencoder = false; |
|
- | 898 | } |
|
885 | return; |
899 | } |
886 | 900 | ||
887 | dp_info.enc_id = 0; |
901 | dp_info.enc_id = 0; |
888 | if (dig->dig_encoder) |
902 | if (dig->dig_encoder) |
889 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; |
903 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; |