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Rev 6104 | Rev 6661 | ||
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Line 1737... | Line 1737... | ||
1737 | * crtcs/encoders. |
1737 | * crtcs/encoders. |
1738 | */ |
1738 | */ |
1739 | static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) |
1739 | static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) |
1740 | { |
1740 | { |
1741 | struct drm_device *dev = crtc->dev; |
1741 | struct drm_device *dev = crtc->dev; |
- | 1742 | struct radeon_device *rdev = dev->dev_private; |
|
1742 | struct drm_crtc *test_crtc; |
1743 | struct drm_crtc *test_crtc; |
1743 | struct radeon_crtc *test_radeon_crtc; |
1744 | struct radeon_crtc *test_radeon_crtc; |
Line 1744... | Line 1745... | ||
1744 | 1745 | ||
1745 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1746 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1746 | if (crtc == test_crtc) |
1747 | if (crtc == test_crtc) |
1747 | continue; |
1748 | continue; |
1748 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1749 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1749 | if (test_radeon_crtc->encoder && |
1750 | if (test_radeon_crtc->encoder && |
- | 1751 | ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
|
- | 1752 | /* PPLL2 is exclusive to UNIPHYA on DCE61 */ |
|
- | 1753 | if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && |
|
- | 1754 | test_radeon_crtc->pll_id == ATOM_PPLL2) |
|
1750 | ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
1755 | continue; |
1751 | /* for DP use the same PLL for all */ |
1756 | /* for DP use the same PLL for all */ |
1752 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1757 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1753 | return test_radeon_crtc->pll_id; |
1758 | return test_radeon_crtc->pll_id; |
1754 | } |
1759 | } |
Line 1767... | Line 1772... | ||
1767 | */ |
1772 | */ |
1768 | static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) |
1773 | static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) |
1769 | { |
1774 | { |
1770 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1775 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1771 | struct drm_device *dev = crtc->dev; |
1776 | struct drm_device *dev = crtc->dev; |
- | 1777 | struct radeon_device *rdev = dev->dev_private; |
|
1772 | struct drm_crtc *test_crtc; |
1778 | struct drm_crtc *test_crtc; |
1773 | struct radeon_crtc *test_radeon_crtc; |
1779 | struct radeon_crtc *test_radeon_crtc; |
1774 | u32 adjusted_clock, test_adjusted_clock; |
1780 | u32 adjusted_clock, test_adjusted_clock; |
Line 1775... | Line 1781... | ||
1775 | 1781 | ||
Line 1782... | Line 1788... | ||
1782 | if (crtc == test_crtc) |
1788 | if (crtc == test_crtc) |
1783 | continue; |
1789 | continue; |
1784 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1790 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1785 | if (test_radeon_crtc->encoder && |
1791 | if (test_radeon_crtc->encoder && |
1786 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
1792 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
- | 1793 | /* PPLL2 is exclusive to UNIPHYA on DCE61 */ |
|
- | 1794 | if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && |
|
- | 1795 | test_radeon_crtc->pll_id == ATOM_PPLL2) |
|
- | 1796 | continue; |
|
1787 | /* check if we are already driving this connector with another crtc */ |
1797 | /* check if we are already driving this connector with another crtc */ |
1788 | if (test_radeon_crtc->connector == radeon_crtc->connector) { |
1798 | if (test_radeon_crtc->connector == radeon_crtc->connector) { |
1789 | /* if we are, return that pll */ |
1799 | /* if we are, return that pll */ |
1790 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1800 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1791 | return test_radeon_crtc->pll_id; |
1801 | return test_radeon_crtc->pll_id; |