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Rev 3764 | Rev 5078 | ||
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Line 207... | Line 207... | ||
207 | args.ucEnable = state; |
207 | args.ucEnable = state; |
Line 208... | Line 208... | ||
208 | 208 | ||
209 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
209 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Line -... | Line 210... | ||
- | 210 | } |
|
- | 211 | ||
- | 212 | static const u32 vga_control_regs[6] = |
|
- | 213 | { |
|
- | 214 | AVIVO_D1VGA_CONTROL, |
|
- | 215 | AVIVO_D2VGA_CONTROL, |
|
- | 216 | EVERGREEN_D3VGA_CONTROL, |
|
- | 217 | EVERGREEN_D4VGA_CONTROL, |
|
- | 218 | EVERGREEN_D5VGA_CONTROL, |
|
- | 219 | EVERGREEN_D6VGA_CONTROL, |
|
210 | } |
220 | }; |
211 | 221 | ||
212 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
222 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
213 | { |
223 | { |
214 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
224 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
215 | struct drm_device *dev = crtc->dev; |
225 | struct drm_device *dev = crtc->dev; |
216 | struct radeon_device *rdev = dev->dev_private; |
226 | struct radeon_device *rdev = dev->dev_private; |
- | 227 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
|
Line 217... | Line 228... | ||
217 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
228 | BLANK_CRTC_PS_ALLOCATION args; |
Line -... | Line 229... | ||
- | 229 | u32 vga_control = 0; |
|
- | 230 | ||
- | 231 | memset(&args, 0, sizeof(args)); |
|
- | 232 | ||
- | 233 | if (ASIC_IS_DCE8(rdev)) { |
|
218 | BLANK_CRTC_PS_ALLOCATION args; |
234 | vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); |
219 | 235 | WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); |
|
Line 220... | Line 236... | ||
220 | memset(&args, 0, sizeof(args)); |
236 | } |
- | 237 | ||
- | 238 | args.ucCRTC = radeon_crtc->crtc_id; |
|
- | 239 | args.ucBlanking = state; |
|
- | 240 | ||
221 | 241 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
Line 222... | Line 242... | ||
222 | args.ucCRTC = radeon_crtc->crtc_id; |
242 | |
223 | args.ucBlanking = state; |
243 | if (ASIC_IS_DCE8(rdev)) { |
224 | 244 | WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); |
|
Line 248... | Line 268... | ||
248 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
268 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Line 249... | Line 269... | ||
249 | 269 | ||
250 | switch (mode) { |
270 | switch (mode) { |
251 | case DRM_MODE_DPMS_ON: |
271 | case DRM_MODE_DPMS_ON: |
252 | radeon_crtc->enabled = true; |
- | |
253 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
- | |
254 | radeon_pm_compute_clocks(rdev); |
272 | radeon_crtc->enabled = true; |
255 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
273 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
256 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
274 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
257 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
275 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
258 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
276 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
Line 267... | Line 285... | ||
267 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
285 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
268 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
286 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
269 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
287 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
270 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
288 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
271 | radeon_crtc->enabled = false; |
289 | radeon_crtc->enabled = false; |
272 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
- | |
273 | radeon_pm_compute_clocks(rdev); |
- | |
274 | break; |
290 | break; |
275 | } |
291 | } |
- | 292 | /* adjust pm to dpms */ |
|
- | 293 | radeon_pm_compute_clocks(rdev); |
|
276 | } |
294 | } |
Line 277... | Line 295... | ||
277 | 295 | ||
278 | static void |
296 | static void |
279 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
297 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
Line 421... | Line 439... | ||
421 | { |
439 | { |
422 | unsigned i; |
440 | unsigned i; |
423 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
441 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
424 | union atom_enable_ss args; |
442 | union atom_enable_ss args; |
Line 425... | Line 443... | ||
425 | 443 | ||
- | 444 | if (enable) { |
|
- | 445 | /* Don't mess with SS if percentage is 0 or external ss. |
|
- | 446 | * SS is already disabled previously, and disabling it |
|
- | 447 | * again can cause display problems if the pll is already |
|
- | 448 | * programmed. |
|
- | 449 | */ |
|
- | 450 | if (ss->percentage == 0) |
|
- | 451 | return; |
|
- | 452 | if (ss->type & ATOM_EXTERNAL_SS_MASK) |
|
- | 453 | return; |
|
426 | if (!enable) { |
454 | } else { |
427 | for (i = 0; i < rdev->num_crtc; i++) { |
455 | for (i = 0; i < rdev->num_crtc; i++) { |
428 | if (rdev->mode_info.crtcs[i] && |
456 | if (rdev->mode_info.crtcs[i] && |
429 | rdev->mode_info.crtcs[i]->enabled && |
457 | rdev->mode_info.crtcs[i]->enabled && |
430 | i != crtc_id && |
458 | i != crtc_id && |
Line 457... | Line 485... | ||
457 | return; |
485 | return; |
458 | } |
486 | } |
459 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
487 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
460 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
488 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
461 | args.v3.ucEnable = enable; |
489 | args.v3.ucEnable = enable; |
462 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) |
- | |
463 | args.v3.ucEnable = ATOM_DISABLE; |
- | |
464 | } else if (ASIC_IS_DCE4(rdev)) { |
490 | } else if (ASIC_IS_DCE4(rdev)) { |
465 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
491 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
466 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
492 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
467 | switch (pll_id) { |
493 | switch (pll_id) { |
468 | case ATOM_PPLL1: |
494 | case ATOM_PPLL1: |
Line 478... | Line 504... | ||
478 | return; |
504 | return; |
479 | } |
505 | } |
480 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
506 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
481 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
507 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
482 | args.v2.ucEnable = enable; |
508 | args.v2.ucEnable = enable; |
483 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) |
- | |
484 | args.v2.ucEnable = ATOM_DISABLE; |
- | |
485 | } else if (ASIC_IS_DCE3(rdev)) { |
509 | } else if (ASIC_IS_DCE3(rdev)) { |
486 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
510 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
487 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
511 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
488 | args.v1.ucSpreadSpectrumStep = ss->step; |
512 | args.v1.ucSpreadSpectrumStep = ss->step; |
489 | args.v1.ucSpreadSpectrumDelay = ss->delay; |
513 | args.v1.ucSpreadSpectrumDelay = ss->delay; |
Line 501... | Line 525... | ||
501 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
525 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
502 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; |
526 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; |
503 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; |
527 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; |
504 | args.lvds_ss_2.ucEnable = enable; |
528 | args.lvds_ss_2.ucEnable = enable; |
505 | } else { |
529 | } else { |
506 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
530 | if (enable == ATOM_DISABLE) { |
507 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { |
- | |
508 | atombios_disable_ss(rdev, pll_id); |
531 | atombios_disable_ss(rdev, pll_id); |
509 | return; |
532 | return; |
510 | } |
533 | } |
511 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
534 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
512 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
535 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Line 532... | Line 555... | ||
532 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
555 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
533 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
556 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
534 | u32 adjusted_clock = mode->clock; |
557 | u32 adjusted_clock = mode->clock; |
535 | int encoder_mode = atombios_get_encoder_mode(encoder); |
558 | int encoder_mode = atombios_get_encoder_mode(encoder); |
536 | u32 dp_clock = mode->clock; |
559 | u32 dp_clock = mode->clock; |
- | 560 | u32 clock = mode->clock; |
|
537 | int bpc = radeon_get_monitor_bpc(connector); |
561 | int bpc = radeon_crtc->bpc; |
538 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
562 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
Line 539... | Line 563... | ||
539 | 563 | ||
540 | /* reset the pll flags */ |
564 | /* reset the pll flags */ |
Line 553... | Line 577... | ||
553 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
577 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
Line 554... | Line 578... | ||
554 | 578 | ||
555 | if (rdev->family < CHIP_RV770) |
579 | if (rdev->family < CHIP_RV770) |
556 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
580 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
557 | /* use frac fb div on APUs */ |
581 | /* use frac fb div on APUs */ |
558 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) |
582 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) |
559 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
583 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
560 | /* use frac fb div on RS780/RS880 */ |
584 | /* use frac fb div on RS780/RS880 */ |
561 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
585 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
562 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
586 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
Line 607... | Line 631... | ||
607 | radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
631 | radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
608 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
632 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
609 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
633 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
610 | } |
634 | } |
Line -... | Line 635... | ||
- | 635 | ||
- | 636 | /* adjust pll for deep color modes */ |
|
- | 637 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
|
- | 638 | switch (bpc) { |
|
- | 639 | case 8: |
|
- | 640 | default: |
|
- | 641 | break; |
|
- | 642 | case 10: |
|
- | 643 | clock = (clock * 5) / 4; |
|
- | 644 | break; |
|
- | 645 | case 12: |
|
- | 646 | clock = (clock * 3) / 2; |
|
- | 647 | break; |
|
- | 648 | case 16: |
|
- | 649 | clock = clock * 2; |
|
- | 650 | break; |
|
- | 651 | } |
|
- | 652 | } |
|
611 | 653 | ||
612 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
654 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
613 | * accordingly based on the encoder/transmitter to work around |
655 | * accordingly based on the encoder/transmitter to work around |
614 | * special hw requirements. |
656 | * special hw requirements. |
615 | */ |
657 | */ |
Line 628... | Line 670... | ||
628 | switch (frev) { |
670 | switch (frev) { |
629 | case 1: |
671 | case 1: |
630 | switch (crev) { |
672 | switch (crev) { |
631 | case 1: |
673 | case 1: |
632 | case 2: |
674 | case 2: |
633 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
675 | args.v1.usPixelClock = cpu_to_le16(clock / 10); |
634 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
676 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
635 | args.v1.ucEncodeMode = encoder_mode; |
677 | args.v1.ucEncodeMode = encoder_mode; |
636 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
678 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
637 | args.v1.ucConfig |= |
679 | args.v1.ucConfig |= |
638 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; |
680 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; |
Line 640... | Line 682... | ||
640 | atom_execute_table(rdev->mode_info.atom_context, |
682 | atom_execute_table(rdev->mode_info.atom_context, |
641 | index, (uint32_t *)&args); |
683 | index, (uint32_t *)&args); |
642 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
684 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
643 | break; |
685 | break; |
644 | case 3: |
686 | case 3: |
645 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); |
687 | args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); |
646 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
688 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
647 | args.v3.sInput.ucEncodeMode = encoder_mode; |
689 | args.v3.sInput.ucEncodeMode = encoder_mode; |
648 | args.v3.sInput.ucDispPllConfig = 0; |
690 | args.v3.sInput.ucDispPllConfig = 0; |
649 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
691 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
650 | args.v3.sInput.ucDispPllConfig |= |
692 | args.v3.sInput.ucDispPllConfig |= |
Line 654... | Line 696... | ||
654 | DISPPLL_CONFIG_COHERENT_MODE; |
696 | DISPPLL_CONFIG_COHERENT_MODE; |
655 | /* 16200 or 27000 */ |
697 | /* 16200 or 27000 */ |
656 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); |
698 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); |
657 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
699 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
658 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
700 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
659 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) |
- | |
660 | /* deep color support */ |
- | |
661 | args.v3.sInput.usPixelClock = |
- | |
662 | cpu_to_le16((mode->clock * bpc / 8) / 10); |
- | |
663 | if (dig->coherent_mode) |
701 | if (dig->coherent_mode) |
664 | args.v3.sInput.ucDispPllConfig |= |
702 | args.v3.sInput.ucDispPllConfig |= |
665 | DISPPLL_CONFIG_COHERENT_MODE; |
703 | DISPPLL_CONFIG_COHERENT_MODE; |
666 | if (is_duallink) |
704 | if (is_duallink) |
667 | args.v3.sInput.ucDispPllConfig |= |
705 | args.v3.sInput.ucDispPllConfig |= |
Line 741... | Line 779... | ||
741 | case 6: |
779 | case 6: |
742 | /* if the default dcpll clock is specified, |
780 | /* if the default dcpll clock is specified, |
743 | * SetPixelClock provides the dividers |
781 | * SetPixelClock provides the dividers |
744 | */ |
782 | */ |
745 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
783 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
746 | if (ASIC_IS_DCE61(rdev)) |
784 | if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) |
747 | args.v6.ucPpll = ATOM_EXT_PLL1; |
785 | args.v6.ucPpll = ATOM_EXT_PLL1; |
748 | else if (ASIC_IS_DCE6(rdev)) |
786 | else if (ASIC_IS_DCE6(rdev)) |
749 | args.v6.ucPpll = ATOM_PPLL0; |
787 | args.v6.ucPpll = ATOM_PPLL0; |
750 | else |
788 | else |
751 | args.v6.ucPpll = ATOM_DCPLL; |
789 | args.v6.ucPpll = ATOM_DCPLL; |
Line 837... | Line 875... | ||
837 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
875 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
838 | args.v5.ucPostDiv = post_div; |
876 | args.v5.ucPostDiv = post_div; |
839 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
877 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
840 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
878 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
841 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; |
879 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; |
- | 880 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
|
842 | switch (bpc) { |
881 | switch (bpc) { |
843 | case 8: |
882 | case 8: |
844 | default: |
883 | default: |
845 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; |
884 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; |
846 | break; |
885 | break; |
847 | case 10: |
886 | case 10: |
- | 887 | /* yes this is correct, the atom define is wrong */ |
|
- | 888 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; |
|
- | 889 | break; |
|
- | 890 | case 12: |
|
- | 891 | /* yes this is correct, the atom define is wrong */ |
|
848 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; |
892 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; |
849 | break; |
893 | break; |
850 | } |
894 | } |
- | 895 | } |
|
851 | args.v5.ucTransmitterID = encoder_id; |
896 | args.v5.ucTransmitterID = encoder_id; |
852 | args.v5.ucEncoderMode = encoder_mode; |
897 | args.v5.ucEncoderMode = encoder_mode; |
853 | args.v5.ucPpll = pll_id; |
898 | args.v5.ucPpll = pll_id; |
854 | break; |
899 | break; |
855 | case 6: |
900 | case 6: |
Line 859... | Line 904... | ||
859 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
904 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
860 | args.v6.ucPostDiv = post_div; |
905 | args.v6.ucPostDiv = post_div; |
861 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ |
906 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ |
862 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
907 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
863 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; |
908 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; |
- | 909 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
|
864 | switch (bpc) { |
910 | switch (bpc) { |
865 | case 8: |
911 | case 8: |
866 | default: |
912 | default: |
867 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; |
913 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; |
868 | break; |
914 | break; |
869 | case 10: |
915 | case 10: |
870 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; |
916 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; |
871 | break; |
917 | break; |
872 | case 12: |
918 | case 12: |
873 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; |
919 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; |
874 | break; |
920 | break; |
875 | case 16: |
921 | case 16: |
876 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; |
922 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; |
877 | break; |
923 | break; |
878 | } |
924 | } |
- | 925 | } |
|
879 | args.v6.ucTransmitterID = encoder_id; |
926 | args.v6.ucTransmitterID = encoder_id; |
880 | args.v6.ucEncoderMode = encoder_mode; |
927 | args.v6.ucEncoderMode = encoder_mode; |
881 | args.v6.ucPpll = pll_id; |
928 | args.v6.ucPpll = pll_id; |
882 | break; |
929 | break; |
883 | default: |
930 | default: |
Line 913... | Line 960... | ||
913 | struct radeon_connector *radeon_connector = |
960 | struct radeon_connector *radeon_connector = |
914 | to_radeon_connector(connector); |
961 | to_radeon_connector(connector); |
915 | struct radeon_connector_atom_dig *dig_connector = |
962 | struct radeon_connector_atom_dig *dig_connector = |
916 | radeon_connector->con_priv; |
963 | radeon_connector->con_priv; |
917 | int dp_clock; |
964 | int dp_clock; |
- | 965 | ||
- | 966 | /* Assign mode clock for hdmi deep color max clock limit check */ |
|
- | 967 | radeon_connector->pixelclock_for_modeset = mode->clock; |
|
918 | radeon_crtc->bpc = radeon_get_monitor_bpc(connector); |
968 | radeon_crtc->bpc = radeon_get_monitor_bpc(connector); |
Line 919... | Line 969... | ||
919 | 969 | ||
920 | switch (encoder_mode) { |
970 | switch (encoder_mode) { |
921 | case ATOM_ENCODER_MODE_DP_MST: |
971 | case ATOM_ENCODER_MODE_DP_MST: |
Line 936... | Line 986... | ||
936 | if (!radeon_crtc->ss_enabled) |
986 | if (!radeon_crtc->ss_enabled) |
937 | radeon_crtc->ss_enabled = |
987 | radeon_crtc->ss_enabled = |
938 | radeon_atombios_get_ppll_ss_info(rdev, |
988 | radeon_atombios_get_ppll_ss_info(rdev, |
939 | &radeon_crtc->ss, |
989 | &radeon_crtc->ss, |
940 | ATOM_DP_SS_ID1); |
990 | ATOM_DP_SS_ID1); |
941 | } else |
991 | } else { |
942 | radeon_crtc->ss_enabled = |
992 | radeon_crtc->ss_enabled = |
943 | radeon_atombios_get_ppll_ss_info(rdev, |
993 | radeon_atombios_get_ppll_ss_info(rdev, |
944 | &radeon_crtc->ss, |
994 | &radeon_crtc->ss, |
945 | ATOM_DP_SS_ID1); |
995 | ATOM_DP_SS_ID1); |
946 | } |
996 | } |
- | 997 | /* disable spread spectrum on DCE3 DP */ |
|
- | 998 | radeon_crtc->ss_enabled = false; |
|
- | 999 | } |
|
947 | break; |
1000 | break; |
948 | case ATOM_ENCODER_MODE_LVDS: |
1001 | case ATOM_ENCODER_MODE_LVDS: |
949 | if (ASIC_IS_DCE4(rdev)) |
1002 | if (ASIC_IS_DCE4(rdev)) |
950 | radeon_crtc->ss_enabled = |
1003 | radeon_crtc->ss_enabled = |
951 | radeon_atombios_get_asic_ss_info(rdev, |
1004 | radeon_atombios_get_asic_ss_info(rdev, |
Line 991... | Line 1044... | ||
991 | struct drm_device *dev = crtc->dev; |
1044 | struct drm_device *dev = crtc->dev; |
992 | struct radeon_device *rdev = dev->dev_private; |
1045 | struct radeon_device *rdev = dev->dev_private; |
993 | struct radeon_encoder *radeon_encoder = |
1046 | struct radeon_encoder *radeon_encoder = |
994 | to_radeon_encoder(radeon_crtc->encoder); |
1047 | to_radeon_encoder(radeon_crtc->encoder); |
995 | u32 pll_clock = mode->clock; |
1048 | u32 pll_clock = mode->clock; |
- | 1049 | u32 clock = mode->clock; |
|
996 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
1050 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
997 | struct radeon_pll *pll; |
1051 | struct radeon_pll *pll; |
998 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
1052 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
Line -... | Line 1053... | ||
- | 1053 | ||
- | 1054 | /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ |
|
- | 1055 | if (ASIC_IS_DCE5(rdev) && |
|
- | 1056 | (encoder_mode == ATOM_ENCODER_MODE_HDMI) && |
|
- | 1057 | (radeon_crtc->bpc > 8)) |
|
- | 1058 | clock = radeon_crtc->adjusted_clock; |
|
999 | 1059 | ||
1000 | switch (radeon_crtc->pll_id) { |
1060 | switch (radeon_crtc->pll_id) { |
1001 | case ATOM_PPLL1: |
1061 | case ATOM_PPLL1: |
1002 | pll = &rdev->clock.p1pll; |
1062 | pll = &rdev->clock.p1pll; |
1003 | break; |
1063 | break; |
Line 1029... | Line 1089... | ||
1029 | 1089 | ||
1030 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, |
1090 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, |
Line 1031... | Line 1091... | ||
1031 | radeon_crtc->crtc_id, &radeon_crtc->ss); |
1091 | radeon_crtc->crtc_id, &radeon_crtc->ss); |
1032 | 1092 | ||
1033 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
1093 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
1034 | encoder_mode, radeon_encoder->encoder_id, mode->clock, |
1094 | encoder_mode, radeon_encoder->encoder_id, clock, |
Line 1035... | Line 1095... | ||
1035 | ref_div, fb_div, frac_fb_div, post_div, |
1095 | ref_div, fb_div, frac_fb_div, post_div, |
1036 | radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); |
1096 | radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); |
1037 | 1097 | ||
1038 | if (radeon_crtc->ss_enabled) { |
1098 | if (radeon_crtc->ss_enabled) { |
1039 | /* calculate ss amount and step size */ |
1099 | /* calculate ss amount and step size */ |
- | 1100 | if (ASIC_IS_DCE4(rdev)) { |
|
- | 1101 | u32 step_size; |
|
1040 | if (ASIC_IS_DCE4(rdev)) { |
1102 | u32 amount = (((fb_div * 10) + frac_fb_div) * |
1041 | u32 step_size; |
1103 | (u32)radeon_crtc->ss.percentage) / |
1042 | u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; |
1104 | (100 * (u32)radeon_crtc->ss.percentage_divider); |
1043 | radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; |
1105 | radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; |
1044 | radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & |
1106 | radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & |
1045 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
1107 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
1046 | if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) |
1108 | if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) |
1047 | step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / |
1109 | step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / |
1048 | (125 * 25 * pll->reference_freq / 100); |
1110 | (125 * 25 * pll->reference_freq / 100); |
1049 | else |
1111 | else |
1050 | step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / |
1112 | step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / |
Line 1051... | Line 1113... | ||
1051 | (125 * 25 * pll->reference_freq / 100); |
1113 | (125 * 25 * pll->reference_freq / 100); |
Line 1072... | Line 1134... | ||
1072 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1134 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1073 | unsigned bankw, bankh, mtaspect, tile_split; |
1135 | unsigned bankw, bankh, mtaspect, tile_split; |
1074 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
1136 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
1075 | u32 tmp, viewport_w, viewport_h; |
1137 | u32 tmp, viewport_w, viewport_h; |
1076 | int r; |
1138 | int r; |
- | 1139 | bool bypass_lut = false; |
|
Line 1077... | Line 1140... | ||
1077 | 1140 | ||
1078 | /* no fb bound */ |
1141 | /* no fb bound */ |
1079 | if (!atomic && !crtc->fb) { |
1142 | if (!atomic && !crtc->primary->fb) { |
1080 | DRM_DEBUG_KMS("No FB bound\n"); |
1143 | DRM_DEBUG_KMS("No FB bound\n"); |
1081 | return 0; |
1144 | return 0; |
Line 1082... | Line 1145... | ||
1082 | } |
1145 | } |
1083 | 1146 | ||
1084 | if (atomic) { |
1147 | if (atomic) { |
1085 | radeon_fb = to_radeon_framebuffer(fb); |
1148 | radeon_fb = to_radeon_framebuffer(fb); |
1086 | target_fb = fb; |
1149 | target_fb = fb; |
1087 | } |
1150 | } |
1088 | else { |
1151 | else { |
1089 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
1152 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
Line 1090... | Line 1153... | ||
1090 | target_fb = crtc->fb; |
1153 | target_fb = crtc->primary->fb; |
1091 | } |
1154 | } |
1092 | 1155 | ||
Line 1110... | Line 1173... | ||
1110 | } |
1173 | } |
Line 1111... | Line 1174... | ||
1111 | 1174 | ||
1112 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1175 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
Line 1113... | Line 1176... | ||
1113 | radeon_bo_unreserve(rbo); |
1176 | radeon_bo_unreserve(rbo); |
1114 | 1177 | ||
1115 | switch (target_fb->bits_per_pixel) { |
1178 | switch (target_fb->pixel_format) { |
1116 | case 8: |
1179 | case DRM_FORMAT_C8: |
1117 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
1180 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
- | 1181 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
|
- | 1182 | break; |
|
- | 1183 | case DRM_FORMAT_XRGB4444: |
|
- | 1184 | case DRM_FORMAT_ARGB4444: |
|
- | 1185 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
|
- | 1186 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); |
|
- | 1187 | #ifdef __BIG_ENDIAN |
|
1118 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
1188 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
- | 1189 | #endif |
|
- | 1190 | break; |
|
1119 | break; |
1191 | case DRM_FORMAT_XRGB1555: |
1120 | case 15: |
1192 | case DRM_FORMAT_ARGB1555: |
- | 1193 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
|
- | 1194 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
|
- | 1195 | #ifdef __BIG_ENDIAN |
|
1121 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1196 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
- | 1197 | #endif |
|
- | 1198 | break; |
|
- | 1199 | case DRM_FORMAT_BGRX5551: |
|
- | 1200 | case DRM_FORMAT_BGRA5551: |
|
- | 1201 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
|
- | 1202 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); |
|
- | 1203 | #ifdef __BIG_ENDIAN |
|
1122 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
1204 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
- | 1205 | #endif |
|
1123 | break; |
1206 | break; |
1124 | case 16: |
1207 | case DRM_FORMAT_RGB565: |
1125 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1208 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1126 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
1209 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
1127 | #ifdef __BIG_ENDIAN |
1210 | #ifdef __BIG_ENDIAN |
1128 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1211 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1129 | #endif |
1212 | #endif |
1130 | break; |
1213 | break; |
1131 | case 24: |
1214 | case DRM_FORMAT_XRGB8888: |
1132 | case 32: |
1215 | case DRM_FORMAT_ARGB8888: |
1133 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
1216 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
1134 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
1217 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
1135 | #ifdef __BIG_ENDIAN |
1218 | #ifdef __BIG_ENDIAN |
1136 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
1219 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
- | 1220 | #endif |
|
- | 1221 | break; |
|
- | 1222 | case DRM_FORMAT_XRGB2101010: |
|
- | 1223 | case DRM_FORMAT_ARGB2101010: |
|
- | 1224 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
|
- | 1225 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); |
|
- | 1226 | #ifdef __BIG_ENDIAN |
|
- | 1227 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
|
- | 1228 | #endif |
|
- | 1229 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
|
- | 1230 | bypass_lut = true; |
|
- | 1231 | break; |
|
- | 1232 | case DRM_FORMAT_BGRX1010102: |
|
- | 1233 | case DRM_FORMAT_BGRA1010102: |
|
- | 1234 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
|
- | 1235 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); |
|
- | 1236 | #ifdef __BIG_ENDIAN |
|
- | 1237 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
|
- | 1238 | #endif |
|
- | 1239 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
|
1137 | #endif |
1240 | bypass_lut = true; |
1138 | break; |
1241 | break; |
1139 | default: |
1242 | default: |
1140 | DRM_ERROR("Unsupported screen depth %d\n", |
1243 | DRM_ERROR("Unsupported screen format %s\n", |
1141 | target_fb->bits_per_pixel); |
1244 | drm_get_format_name(target_fb->pixel_format)); |
Line 1142... | Line 1245... | ||
1142 | return -EINVAL; |
1245 | return -EINVAL; |
- | 1246 | } |
|
- | 1247 | ||
- | 1248 | if (tiling_flags & RADEON_TILING_MACRO) { |
|
1143 | } |
1249 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); |
- | 1250 | ||
- | 1251 | /* Set NUM_BANKS. */ |
|
- | 1252 | if (rdev->family >= CHIP_TAHITI) { |
|
- | 1253 | unsigned index, num_banks; |
|
- | 1254 | ||
- | 1255 | if (rdev->family >= CHIP_BONAIRE) { |
|
- | 1256 | unsigned tileb, tile_split_bytes; |
|
- | 1257 | ||
- | 1258 | /* Calculate the macrotile mode index. */ |
|
- | 1259 | tile_split_bytes = 64 << tile_split; |
|
- | 1260 | tileb = 8 * 8 * target_fb->bits_per_pixel / 8; |
|
- | 1261 | tileb = min(tile_split_bytes, tileb); |
|
- | 1262 | ||
- | 1263 | for (index = 0; tileb > 64; index++) |
|
- | 1264 | tileb >>= 1; |
|
- | 1265 | ||
- | 1266 | if (index >= 16) { |
|
- | 1267 | DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", |
|
- | 1268 | target_fb->bits_per_pixel, tile_split); |
|
- | 1269 | return -EINVAL; |
|
- | 1270 | } |
|
- | 1271 | ||
- | 1272 | num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; |
|
- | 1273 | } else { |
|
- | 1274 | switch (target_fb->bits_per_pixel) { |
|
- | 1275 | case 8: |
|
- | 1276 | index = 10; |
|
- | 1277 | break; |
|
- | 1278 | case 16: |
|
- | 1279 | index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; |
|
- | 1280 | break; |
|
- | 1281 | default: |
|
- | 1282 | case 32: |
|
- | 1283 | index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; |
|
1144 | 1284 | break; |
|
- | 1285 | } |
|
- | 1286 | ||
- | 1287 | num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; |
|
- | 1288 | } |
|
- | 1289 | ||
1145 | if (tiling_flags & RADEON_TILING_MACRO) { |
1290 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); |
1146 | if (rdev->family >= CHIP_TAHITI) |
1291 | } else { |
1147 | tmp = rdev->config.si.tile_config; |
1292 | /* NI and older. */ |
1148 | else if (rdev->family >= CHIP_CAYMAN) |
1293 | if (rdev->family >= CHIP_CAYMAN) |
Line 1149... | Line 1294... | ||
1149 | tmp = rdev->config.cayman.tile_config; |
1294 | tmp = rdev->config.cayman.tile_config; |
Line 1160... | Line 1305... | ||
1160 | break; |
1305 | break; |
1161 | case 2: /* 16 banks */ |
1306 | case 2: /* 16 banks */ |
1162 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); |
1307 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); |
1163 | break; |
1308 | break; |
1164 | } |
1309 | } |
- | 1310 | } |
|
Line 1165... | Line 1311... | ||
1165 | 1311 | ||
1166 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
- | |
1167 | - | ||
1168 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); |
1312 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
1169 | fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); |
1313 | fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); |
1170 | fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); |
1314 | fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); |
1171 | fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); |
1315 | fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); |
- | 1316 | fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); |
|
- | 1317 | if (rdev->family >= CHIP_BONAIRE) { |
|
- | 1318 | /* XXX need to know more about the surface tiling mode */ |
|
- | 1319 | fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); |
|
1172 | fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); |
1320 | } |
1173 | } else if (tiling_flags & RADEON_TILING_MICRO) |
1321 | } else if (tiling_flags & RADEON_TILING_MICRO) |
Line -... | Line 1322... | ||
- | 1322 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
|
- | 1323 | ||
- | 1324 | if (rdev->family >= CHIP_BONAIRE) { |
|
- | 1325 | /* Read the pipe config from the 2D TILED SCANOUT mode. |
|
- | 1326 | * It should be the same for the other modes too, but not all |
|
- | 1327 | * modes set the pipe config field. */ |
|
- | 1328 | u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; |
|
1174 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
1329 | |
1175 | 1330 | fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); |
|
1176 | if ((rdev->family == CHIP_TAHITI) || |
1331 | } else if ((rdev->family == CHIP_TAHITI) || |
1177 | (rdev->family == CHIP_PITCAIRN)) |
1332 | (rdev->family == CHIP_PITCAIRN)) |
- | 1333 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); |
|
- | 1334 | else if ((rdev->family == CHIP_VERDE) || |
|
1178 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); |
1335 | (rdev->family == CHIP_OLAND) || |
Line 1179... | Line 1336... | ||
1179 | else if (rdev->family == CHIP_VERDE) |
1336 | (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ |
1180 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); |
1337 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); |
1181 | 1338 | ||
Line 1211... | Line 1368... | ||
1211 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1368 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1212 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
1369 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
1213 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1370 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1214 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1371 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
Line -... | Line 1372... | ||
- | 1372 | ||
- | 1373 | /* |
|
- | 1374 | * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT |
|
- | 1375 | * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to |
|
- | 1376 | * retain the full precision throughout the pipeline. |
|
- | 1377 | */ |
|
- | 1378 | WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, |
|
- | 1379 | (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), |
|
- | 1380 | ~EVERGREEN_LUT_10BIT_BYPASS_EN); |
|
- | 1381 | ||
- | 1382 | if (bypass_lut) |
|
- | 1383 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); |
|
1215 | 1384 | ||
1216 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1385 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1217 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1386 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1218 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
1387 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
1219 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
1388 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
Line 1222... | Line 1391... | ||
1222 | 1391 | ||
1223 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1392 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1224 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1393 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
Line -... | Line 1394... | ||
- | 1394 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
|
- | 1395 | ||
- | 1396 | if (rdev->family >= CHIP_BONAIRE) |
|
- | 1397 | WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
|
1225 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
1398 | target_fb->height); |
1226 | 1399 | else |
|
1227 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1400 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1228 | target_fb->height); |
1401 | target_fb->height); |
1229 | x &= ~3; |
1402 | x &= ~3; |
Line 1239... | Line 1412... | ||
1239 | /* make sure flip is at vb rather than hb */ |
1412 | /* make sure flip is at vb rather than hb */ |
1240 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
1413 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
1241 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
1414 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
1242 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
1415 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
Line 1243... | Line 1416... | ||
1243 | 1416 | ||
1244 | /* set pageflip to happen anywhere in vblank interval */ |
1417 | /* set pageflip to happen only at start of vblank interval (front porch) */ |
Line 1245... | Line 1418... | ||
1245 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); |
1418 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); |
1246 | 1419 | ||
1247 | if (!atomic && fb && fb != crtc->fb) { |
1420 | if (!atomic && fb && fb != crtc->primary->fb) { |
1248 | radeon_fb = to_radeon_framebuffer(fb); |
1421 | radeon_fb = to_radeon_framebuffer(fb); |
1249 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1422 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1250 | r = radeon_bo_reserve(rbo, false); |
1423 | r = radeon_bo_reserve(rbo, false); |
Line 1274... | Line 1447... | ||
1274 | uint64_t fb_location; |
1447 | uint64_t fb_location; |
1275 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1448 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1276 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
1449 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
1277 | u32 tmp, viewport_w, viewport_h; |
1450 | u32 tmp, viewport_w, viewport_h; |
1278 | int r; |
1451 | int r; |
- | 1452 | bool bypass_lut = false; |
|
Line 1279... | Line 1453... | ||
1279 | 1453 | ||
1280 | /* no fb bound */ |
1454 | /* no fb bound */ |
1281 | if (!atomic && !crtc->fb) { |
1455 | if (!atomic && !crtc->primary->fb) { |
1282 | DRM_DEBUG_KMS("No FB bound\n"); |
1456 | DRM_DEBUG_KMS("No FB bound\n"); |
1283 | return 0; |
1457 | return 0; |
Line 1284... | Line 1458... | ||
1284 | } |
1458 | } |
1285 | 1459 | ||
1286 | if (atomic) { |
1460 | if (atomic) { |
1287 | radeon_fb = to_radeon_framebuffer(fb); |
1461 | radeon_fb = to_radeon_framebuffer(fb); |
1288 | target_fb = fb; |
1462 | target_fb = fb; |
1289 | } |
1463 | } |
1290 | else { |
1464 | else { |
1291 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
1465 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
Line 1292... | Line 1466... | ||
1292 | target_fb = crtc->fb; |
1466 | target_fb = crtc->primary->fb; |
1293 | } |
1467 | } |
1294 | 1468 | ||
Line 1311... | Line 1485... | ||
1311 | } |
1485 | } |
1312 | } |
1486 | } |
1313 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1487 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1314 | radeon_bo_unreserve(rbo); |
1488 | radeon_bo_unreserve(rbo); |
Line 1315... | Line 1489... | ||
1315 | 1489 | ||
1316 | switch (target_fb->bits_per_pixel) { |
1490 | switch (target_fb->pixel_format) { |
1317 | case 8: |
1491 | case DRM_FORMAT_C8: |
1318 | fb_format = |
1492 | fb_format = |
1319 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
1493 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
1320 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
1494 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
- | 1495 | break; |
|
- | 1496 | case DRM_FORMAT_XRGB4444: |
|
- | 1497 | case DRM_FORMAT_ARGB4444: |
|
- | 1498 | fb_format = |
|
- | 1499 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
|
- | 1500 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444; |
|
- | 1501 | #ifdef __BIG_ENDIAN |
|
- | 1502 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
|
1321 | break; |
1503 | #endif |
- | 1504 | break; |
|
1322 | case 15: |
1505 | case DRM_FORMAT_XRGB1555: |
1323 | fb_format = |
1506 | fb_format = |
1324 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1507 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
- | 1508 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
|
- | 1509 | #ifdef __BIG_ENDIAN |
|
- | 1510 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
|
1325 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
1511 | #endif |
1326 | break; |
1512 | break; |
1327 | case 16: |
1513 | case DRM_FORMAT_RGB565: |
1328 | fb_format = |
1514 | fb_format = |
1329 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1515 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1330 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
1516 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
1331 | #ifdef __BIG_ENDIAN |
1517 | #ifdef __BIG_ENDIAN |
1332 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
1518 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
1333 | #endif |
1519 | #endif |
1334 | break; |
1520 | break; |
1335 | case 24: |
1521 | case DRM_FORMAT_XRGB8888: |
1336 | case 32: |
1522 | case DRM_FORMAT_ARGB8888: |
1337 | fb_format = |
1523 | fb_format = |
1338 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
1524 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
1339 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
1525 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
1340 | #ifdef __BIG_ENDIAN |
1526 | #ifdef __BIG_ENDIAN |
1341 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
1527 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
1342 | #endif |
1528 | #endif |
- | 1529 | break; |
|
- | 1530 | case DRM_FORMAT_XRGB2101010: |
|
- | 1531 | case DRM_FORMAT_ARGB2101010: |
|
- | 1532 | fb_format = |
|
- | 1533 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
|
- | 1534 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010; |
|
- | 1535 | #ifdef __BIG_ENDIAN |
|
- | 1536 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
|
- | 1537 | #endif |
|
- | 1538 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
|
- | 1539 | bypass_lut = true; |
|
1343 | break; |
1540 | break; |
1344 | default: |
1541 | default: |
1345 | DRM_ERROR("Unsupported screen depth %d\n", |
1542 | DRM_ERROR("Unsupported screen format %s\n", |
1346 | target_fb->bits_per_pixel); |
1543 | drm_get_format_name(target_fb->pixel_format)); |
1347 | return -EINVAL; |
1544 | return -EINVAL; |
Line 1348... | Line 1545... | ||
1348 | } |
1545 | } |
1349 | 1546 | ||
Line 1380... | Line 1577... | ||
1380 | radeon_crtc->crtc_offset, (u32) fb_location); |
1577 | radeon_crtc->crtc_offset, (u32) fb_location); |
1381 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1578 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1382 | if (rdev->family >= CHIP_R600) |
1579 | if (rdev->family >= CHIP_R600) |
1383 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1580 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
Line -... | Line 1581... | ||
- | 1581 | ||
- | 1582 | /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ |
|
- | 1583 | WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, |
|
- | 1584 | (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN); |
|
- | 1585 | ||
- | 1586 | if (bypass_lut) |
|
- | 1587 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); |
|
1384 | 1588 | ||
1385 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1589 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1386 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1590 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1387 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
1591 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
1388 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
1592 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
Line 1408... | Line 1612... | ||
1408 | /* make sure flip is at vb rather than hb */ |
1612 | /* make sure flip is at vb rather than hb */ |
1409 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
1613 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
1410 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
1614 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
1411 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
1615 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
Line 1412... | Line 1616... | ||
1412 | 1616 | ||
1413 | /* set pageflip to happen anywhere in vblank interval */ |
1617 | /* set pageflip to happen only at start of vblank interval (front porch) */ |
Line 1414... | Line 1618... | ||
1414 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); |
1618 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); |
1415 | 1619 | ||
1416 | if (!atomic && fb && fb != crtc->fb) { |
1620 | if (!atomic && fb && fb != crtc->primary->fb) { |
1417 | radeon_fb = to_radeon_framebuffer(fb); |
1621 | radeon_fb = to_radeon_framebuffer(fb); |
1418 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1622 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1419 | r = radeon_bo_reserve(rbo, false); |
1623 | r = radeon_bo_reserve(rbo, false); |
Line 1595... | Line 1799... | ||
1595 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to |
1799 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to |
1596 | * avoid messing up an existing monitor. |
1800 | * avoid messing up an existing monitor. |
1597 | * |
1801 | * |
1598 | * Asic specific PLL information |
1802 | * Asic specific PLL information |
1599 | * |
1803 | * |
- | 1804 | * DCE 8.x |
|
- | 1805 | * KB/KV |
|
- | 1806 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) |
|
- | 1807 | * CI |
|
- | 1808 | * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
|
- | 1809 | * |
|
1600 | * DCE 6.1 |
1810 | * DCE 6.1 |
1601 | * - PPLL2 is only available to UNIPHYA (both DP and non-DP) |
1811 | * - PPLL2 is only available to UNIPHYA (both DP and non-DP) |
1602 | * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) |
1812 | * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) |
1603 | * |
1813 | * |
1604 | * DCE 6.0 |
1814 | * DCE 6.0 |
Line 1621... | Line 1831... | ||
1621 | struct radeon_encoder *radeon_encoder = |
1831 | struct radeon_encoder *radeon_encoder = |
1622 | to_radeon_encoder(radeon_crtc->encoder); |
1832 | to_radeon_encoder(radeon_crtc->encoder); |
1623 | u32 pll_in_use; |
1833 | u32 pll_in_use; |
1624 | int pll; |
1834 | int pll; |
Line 1625... | Line 1835... | ||
1625 | 1835 | ||
- | 1836 | if (ASIC_IS_DCE8(rdev)) { |
|
- | 1837 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
|
- | 1838 | if (rdev->clock.dp_extclk) |
|
- | 1839 | /* skip PPLL programming if using ext clock */ |
|
- | 1840 | return ATOM_PPLL_INVALID; |
|
- | 1841 | else { |
|
- | 1842 | /* use the same PPLL for all DP monitors */ |
|
- | 1843 | pll = radeon_get_shared_dp_ppll(crtc); |
|
- | 1844 | if (pll != ATOM_PPLL_INVALID) |
|
- | 1845 | return pll; |
|
- | 1846 | } |
|
- | 1847 | } else { |
|
- | 1848 | /* use the same PPLL for all monitors with the same clock */ |
|
- | 1849 | pll = radeon_get_shared_nondp_ppll(crtc); |
|
- | 1850 | if (pll != ATOM_PPLL_INVALID) |
|
- | 1851 | return pll; |
|
- | 1852 | } |
|
- | 1853 | /* otherwise, pick one of the plls */ |
|
- | 1854 | if ((rdev->family == CHIP_KAVERI) || |
|
- | 1855 | (rdev->family == CHIP_KABINI) || |
|
- | 1856 | (rdev->family == CHIP_MULLINS)) { |
|
- | 1857 | /* KB/KV/ML has PPLL1 and PPLL2 */ |
|
- | 1858 | pll_in_use = radeon_get_pll_use_mask(crtc); |
|
- | 1859 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
|
- | 1860 | return ATOM_PPLL2; |
|
- | 1861 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
|
- | 1862 | return ATOM_PPLL1; |
|
- | 1863 | DRM_ERROR("unable to allocate a PPLL\n"); |
|
- | 1864 | return ATOM_PPLL_INVALID; |
|
- | 1865 | } else { |
|
- | 1866 | /* CI has PPLL0, PPLL1, and PPLL2 */ |
|
- | 1867 | pll_in_use = radeon_get_pll_use_mask(crtc); |
|
- | 1868 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
|
- | 1869 | return ATOM_PPLL2; |
|
- | 1870 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
|
- | 1871 | return ATOM_PPLL1; |
|
- | 1872 | if (!(pll_in_use & (1 << ATOM_PPLL0))) |
|
- | 1873 | return ATOM_PPLL0; |
|
- | 1874 | DRM_ERROR("unable to allocate a PPLL\n"); |
|
- | 1875 | return ATOM_PPLL_INVALID; |
|
- | 1876 | } |
|
1626 | if (ASIC_IS_DCE61(rdev)) { |
1877 | } else if (ASIC_IS_DCE61(rdev)) { |
1627 | struct radeon_encoder_atom_dig *dig = |
1878 | struct radeon_encoder_atom_dig *dig = |
Line 1628... | Line 1879... | ||
1628 | radeon_encoder->enc_priv; |
1879 | radeon_encoder->enc_priv; |
1629 | 1880 | ||
Line 1654... | Line 1905... | ||
1654 | return ATOM_PPLL0; |
1905 | return ATOM_PPLL0; |
1655 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1906 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1656 | return ATOM_PPLL1; |
1907 | return ATOM_PPLL1; |
1657 | DRM_ERROR("unable to allocate a PPLL\n"); |
1908 | DRM_ERROR("unable to allocate a PPLL\n"); |
1658 | return ATOM_PPLL_INVALID; |
1909 | return ATOM_PPLL_INVALID; |
- | 1910 | } else if (ASIC_IS_DCE41(rdev)) { |
|
- | 1911 | /* Don't share PLLs on DCE4.1 chips */ |
|
- | 1912 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
|
- | 1913 | if (rdev->clock.dp_extclk) |
|
- | 1914 | /* skip PPLL programming if using ext clock */ |
|
- | 1915 | return ATOM_PPLL_INVALID; |
|
- | 1916 | } |
|
- | 1917 | pll_in_use = radeon_get_pll_use_mask(crtc); |
|
- | 1918 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
|
- | 1919 | return ATOM_PPLL1; |
|
- | 1920 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
|
- | 1921 | return ATOM_PPLL2; |
|
- | 1922 | DRM_ERROR("unable to allocate a PPLL\n"); |
|
- | 1923 | return ATOM_PPLL_INVALID; |
|
1659 | } else if (ASIC_IS_DCE4(rdev)) { |
1924 | } else if (ASIC_IS_DCE4(rdev)) { |
1660 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1925 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1661 | * depending on the asic: |
1926 | * depending on the asic: |
1662 | * DCE4: PPLL or ext clock |
1927 | * DCE4: PPLL or ext clock |
1663 | * DCE5: PPLL, DCPLL, or ext clock |
1928 | * DCE5: PPLL, DCPLL, or ext clock |
Line 1751... | Line 2016... | ||
1751 | 2016 | ||
1752 | if (radeon_encoder->active_device & |
2017 | if (radeon_encoder->active_device & |
1753 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
2018 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
Line -... | Line 2019... | ||
- | 2019 | is_tvcv = true; |
|
- | 2020 | ||
- | 2021 | if (!radeon_crtc->adjusted_clock) |
|
1754 | is_tvcv = true; |
2022 | return -EINVAL; |
Line 1755... | Line 2023... | ||
1755 | 2023 | ||
1756 | atombios_crtc_set_pll(crtc, adjusted_mode); |
2024 | atombios_crtc_set_pll(crtc, adjusted_mode); |
1757 | 2025 | ||
Line 1769... | Line 2037... | ||
1769 | radeon_legacy_atom_fixup(crtc); |
2037 | radeon_legacy_atom_fixup(crtc); |
1770 | } |
2038 | } |
1771 | atombios_crtc_set_base(crtc, x, y, old_fb); |
2039 | atombios_crtc_set_base(crtc, x, y, old_fb); |
1772 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
2040 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
1773 | atombios_scaler_setup(crtc); |
2041 | atombios_scaler_setup(crtc); |
- | 2042 | /* update the hw version fpr dpm */ |
|
- | 2043 | radeon_crtc->hw_mode = *adjusted_mode; |
|
- | 2044 | ||
1774 | return 0; |
2045 | return 0; |
1775 | } |
2046 | } |
Line 1776... | Line 2047... | ||
1776 | 2047 | ||
1777 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
2048 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
Line 1835... | Line 2106... | ||
1835 | struct radeon_device *rdev = dev->dev_private; |
2106 | struct radeon_device *rdev = dev->dev_private; |
1836 | struct radeon_atom_ss ss; |
2107 | struct radeon_atom_ss ss; |
1837 | int i; |
2108 | int i; |
Line 1838... | Line 2109... | ||
1838 | 2109 | ||
- | 2110 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
|
- | 2111 | if (crtc->primary->fb) { |
|
- | 2112 | int r; |
|
- | 2113 | struct radeon_framebuffer *radeon_fb; |
|
- | 2114 | struct radeon_bo *rbo; |
|
- | 2115 | ||
- | 2116 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
|
- | 2117 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
|
- | 2118 | r = radeon_bo_reserve(rbo, false); |
|
- | 2119 | if (unlikely(r)) |
|
- | 2120 | DRM_ERROR("failed to reserve rbo before unpin\n"); |
|
- | 2121 | else { |
|
- | 2122 | radeon_bo_unpin(rbo); |
|
- | 2123 | radeon_bo_unreserve(rbo); |
|
- | 2124 | } |
|
- | 2125 | } |
|
- | 2126 | /* disable the GRPH */ |
|
- | 2127 | if (ASIC_IS_DCE4(rdev)) |
|
- | 2128 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); |
|
- | 2129 | else if (ASIC_IS_AVIVO(rdev)) |
|
- | 2130 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); |
|
1839 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
2131 | |
1840 | if (ASIC_IS_DCE6(rdev)) |
2132 | if (ASIC_IS_DCE6(rdev)) |
Line 1841... | Line 2133... | ||
1841 | atombios_powergate_crtc(crtc, ATOM_ENABLE); |
2133 | atombios_powergate_crtc(crtc, ATOM_ENABLE); |
1842 | 2134 | ||
Line 1859... | Line 2151... | ||
1859 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
2151 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
1860 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
2152 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
1861 | break; |
2153 | break; |
1862 | case ATOM_PPLL0: |
2154 | case ATOM_PPLL0: |
1863 | /* disable the ppll */ |
2155 | /* disable the ppll */ |
1864 | if (ASIC_IS_DCE61(rdev)) |
2156 | if ((rdev->family == CHIP_ARUBA) || |
- | 2157 | (rdev->family == CHIP_BONAIRE) || |
|
- | 2158 | (rdev->family == CHIP_HAWAII)) |
|
1865 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
2159 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
1866 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
2160 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
1867 | break; |
2161 | break; |
1868 | default: |
2162 | default: |
1869 | break; |
2163 | break; |