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Rev 3031 | Rev 3120 | ||
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Line 1694... | Line 1694... | ||
1694 | return ATOM_PPLL1; |
1694 | return ATOM_PPLL1; |
1695 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1695 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1696 | return ATOM_PPLL2; |
1696 | return ATOM_PPLL2; |
1697 | DRM_ERROR("unable to allocate a PPLL\n"); |
1697 | DRM_ERROR("unable to allocate a PPLL\n"); |
1698 | return ATOM_PPLL_INVALID; |
1698 | return ATOM_PPLL_INVALID; |
1699 | } else if (ASIC_IS_AVIVO(rdev)) { |
- | |
1700 | /* in DP mode, the DP ref clock can come from either PPLL |
- | |
1701 | * depending on the asic: |
- | |
1702 | * DCE3: PPLL1 or PPLL2 |
- | |
1703 | */ |
- | |
1704 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
- | |
1705 | /* use the same PPLL for all DP monitors */ |
- | |
1706 | pll = radeon_get_shared_dp_ppll(crtc); |
- | |
1707 | if (pll != ATOM_PPLL_INVALID) |
- | |
1708 | return pll; |
- | |
1709 | } else { |
- | |
1710 | /* use the same PPLL for all monitors with the same clock */ |
- | |
1711 | pll = radeon_get_shared_nondp_ppll(crtc); |
- | |
1712 | if (pll != ATOM_PPLL_INVALID) |
- | |
1713 | return pll; |
- | |
1714 | } |
- | |
1715 | /* all other cases */ |
- | |
1716 | pll_in_use = radeon_get_pll_use_mask(crtc); |
- | |
1717 | /* the order shouldn't matter here, but we probably |
- | |
1718 | * need this until we have atomic modeset |
- | |
1719 | */ |
- | |
1720 | if (rdev->flags & RADEON_IS_IGP) { |
- | |
1721 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
- | |
1722 | return ATOM_PPLL1; |
- | |
1723 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
- | |
1724 | return ATOM_PPLL2; |
- | |
1725 | } else { |
- | |
1726 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
- | |
1727 | return ATOM_PPLL2; |
- | |
1728 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
- | |
1729 | return ATOM_PPLL1; |
- | |
1730 | } |
- | |
1731 | DRM_ERROR("unable to allocate a PPLL\n"); |
- | |
1732 | return ATOM_PPLL_INVALID; |
- | |
1733 | } else { |
1699 | } else { |
1734 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ |
1700 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ |
- | 1701 | /* some atombios (observed in some DCE2/DCE3) code have a bug, |
|
- | 1702 | * the matching btw pll and crtc is done through |
|
- | 1703 | * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the |
|
- | 1704 | * pll (1 or 2) to select which register to write. ie if using |
|
- | 1705 | * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 |
|
- | 1706 | * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to |
|
- | 1707 | * choose which value to write. Which is reverse order from |
|
- | 1708 | * register logic. So only case that works is when pllid is |
|
- | 1709 | * same as crtcid or when both pll and crtc are enabled and |
|
- | 1710 | * both use same clock. |
|
- | 1711 | * |
|
- | 1712 | * So just return crtc id as if crtc and pll were hard linked |
|
- | 1713 | * together even if they aren't |
|
- | 1714 | */ |
|
1735 | return radeon_crtc->crtc_id; |
1715 | return radeon_crtc->crtc_id; |
1736 | } |
1716 | } |
1737 | } |
1717 | } |
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1738 | 1718 |