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Rev 1404 | Rev 1430 | ||
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Line 243... | Line 243... | ||
243 | struct radeon_device *rdev = dev->dev_private; |
243 | struct radeon_device *rdev = dev->dev_private; |
244 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
244 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Line 245... | Line 245... | ||
245 | 245 | ||
246 | switch (mode) { |
246 | switch (mode) { |
247 | case DRM_MODE_DPMS_ON: |
247 | case DRM_MODE_DPMS_ON: |
248 | atombios_enable_crtc(crtc, 1); |
248 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
249 | if (ASIC_IS_DCE3(rdev)) |
249 | if (ASIC_IS_DCE3(rdev)) |
250 | atombios_enable_crtc_memreq(crtc, 1); |
250 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
- | 251 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
|
- | 252 | /* XXX re-enable when interrupt support is added */ |
|
- | 253 | if (!ASIC_IS_DCE4(rdev)) |
|
251 | atombios_blank_crtc(crtc, 0); |
254 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
252 | radeon_crtc_load_lut(crtc); |
255 | radeon_crtc_load_lut(crtc); |
253 | break; |
256 | break; |
254 | case DRM_MODE_DPMS_STANDBY: |
257 | case DRM_MODE_DPMS_STANDBY: |
255 | case DRM_MODE_DPMS_SUSPEND: |
258 | case DRM_MODE_DPMS_SUSPEND: |
- | 259 | case DRM_MODE_DPMS_OFF: |
|
- | 260 | /* XXX re-enable when interrupt support is added */ |
|
- | 261 | if (!ASIC_IS_DCE4(rdev)) |
|
256 | case DRM_MODE_DPMS_OFF: |
262 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
257 | atombios_blank_crtc(crtc, 1); |
263 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
258 | if (ASIC_IS_DCE3(rdev)) |
264 | if (ASIC_IS_DCE3(rdev)) |
259 | atombios_enable_crtc_memreq(crtc, 0); |
265 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
260 | atombios_enable_crtc(crtc, 0); |
266 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
261 | break; |
267 | break; |
262 | } |
268 | } |
Line 263... | Line 269... | ||
263 | } |
269 | } |
Line 345... | Line 351... | ||
345 | args.ucCRTC = radeon_crtc->crtc_id; |
351 | args.ucCRTC = radeon_crtc->crtc_id; |
Line 346... | Line 352... | ||
346 | 352 | ||
347 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
353 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Line -... | Line 354... | ||
- | 354 | } |
|
- | 355 | ||
- | 356 | union atom_enable_ss { |
|
- | 357 | ENABLE_LVDS_SS_PARAMETERS legacy; |
|
- | 358 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
|
348 | } |
359 | }; |
349 | 360 | ||
350 | static void atombios_set_ss(struct drm_crtc *crtc, int enable) |
361 | static void atombios_set_ss(struct drm_crtc *crtc, int enable) |
351 | { |
362 | { |
352 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
363 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
353 | struct drm_device *dev = crtc->dev; |
364 | struct drm_device *dev = crtc->dev; |
354 | struct radeon_device *rdev = dev->dev_private; |
365 | struct radeon_device *rdev = dev->dev_private; |
355 | struct drm_encoder *encoder = NULL; |
366 | struct drm_encoder *encoder = NULL; |
356 | struct radeon_encoder *radeon_encoder = NULL; |
367 | struct radeon_encoder *radeon_encoder = NULL; |
357 | struct radeon_encoder_atom_dig *dig = NULL; |
- | |
358 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
368 | struct radeon_encoder_atom_dig *dig = NULL; |
359 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION args; |
369 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
360 | ENABLE_LVDS_SS_PARAMETERS legacy_args; |
370 | union atom_enable_ss args; |
Line -... | Line 371... | ||
- | 371 | uint16_t percentage = 0; |
|
- | 372 | uint8_t type = 0, step = 0, delay = 0, range = 0; |
|
- | 373 | ||
- | 374 | /* XXX add ss support for DCE4 */ |
|
361 | uint16_t percentage = 0; |
375 | if (ASIC_IS_DCE4(rdev)) |
362 | uint8_t type = 0, step = 0, delay = 0, range = 0; |
376 | return; |
363 | 377 | ||
364 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
378 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
365 | if (encoder->crtc == crtc) { |
379 | if (encoder->crtc == crtc) { |
Line 382... | Line 396... | ||
382 | } |
396 | } |
Line 383... | Line 397... | ||
383 | 397 | ||
384 | if (!radeon_encoder) |
398 | if (!radeon_encoder) |
Line 385... | Line -... | ||
385 | return; |
- | |
386 | 399 | return; |
|
- | 400 | ||
387 | if (ASIC_IS_AVIVO(rdev)) { |
401 | memset(&args, 0, sizeof(args)); |
388 | memset(&args, 0, sizeof(args)); |
402 | if (ASIC_IS_AVIVO(rdev)) { |
389 | args.usSpreadSpectrumPercentage = cpu_to_le16(percentage); |
403 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage); |
390 | args.ucSpreadSpectrumType = type; |
404 | args.v1.ucSpreadSpectrumType = type; |
391 | args.ucSpreadSpectrumStep = step; |
405 | args.v1.ucSpreadSpectrumStep = step; |
392 | args.ucSpreadSpectrumDelay = delay; |
406 | args.v1.ucSpreadSpectrumDelay = delay; |
393 | args.ucSpreadSpectrumRange = range; |
407 | args.v1.ucSpreadSpectrumRange = range; |
394 | args.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
- | |
395 | args.ucEnable = enable; |
408 | args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
396 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
- | |
397 | } else { |
409 | args.v1.ucEnable = enable; |
398 | memset(&legacy_args, 0, sizeof(legacy_args)); |
410 | } else { |
399 | legacy_args.usSpreadSpectrumPercentage = cpu_to_le16(percentage); |
411 | args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage); |
400 | legacy_args.ucSpreadSpectrumType = type; |
412 | args.legacy.ucSpreadSpectrumType = type; |
401 | legacy_args.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2; |
413 | args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2; |
402 | legacy_args.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4; |
- | |
403 | legacy_args.ucEnable = enable; |
414 | args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4; |
- | 415 | args.legacy.ucEnable = enable; |
|
404 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&legacy_args); |
416 | } |
Line 405... | Line 417... | ||
405 | } |
417 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
406 | } |
418 | } |
- | 419 | ||
407 | 420 | union adjust_pixel_clock { |
|
Line 408... | Line 421... | ||
408 | union adjust_pixel_clock { |
421 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; |
409 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; |
422 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
410 | }; |
423 | }; |
Line 416... | Line 429... | ||
416 | struct drm_device *dev = crtc->dev; |
429 | struct drm_device *dev = crtc->dev; |
417 | struct radeon_device *rdev = dev->dev_private; |
430 | struct radeon_device *rdev = dev->dev_private; |
418 | struct drm_encoder *encoder = NULL; |
431 | struct drm_encoder *encoder = NULL; |
419 | struct radeon_encoder *radeon_encoder = NULL; |
432 | struct radeon_encoder *radeon_encoder = NULL; |
420 | u32 adjusted_clock = mode->clock; |
433 | u32 adjusted_clock = mode->clock; |
- | 434 | int encoder_mode = 0; |
|
Line 421... | Line 435... | ||
421 | 435 | ||
422 | /* reset the pll flags */ |
436 | /* reset the pll flags */ |
Line -... | Line 437... | ||
- | 437 | pll->flags = 0; |
|
- | 438 | ||
- | 439 | /* select the PLL algo */ |
|
- | 440 | if (ASIC_IS_AVIVO(rdev)) { |
|
- | 441 | if (radeon_new_pll == 0) |
|
- | 442 | pll->algo = PLL_ALGO_LEGACY; |
|
- | 443 | else |
|
- | 444 | pll->algo = PLL_ALGO_NEW; |
|
- | 445 | } else { |
|
- | 446 | if (radeon_new_pll == 1) |
|
- | 447 | pll->algo = PLL_ALGO_NEW; |
|
- | 448 | else |
|
- | 449 | pll->algo = PLL_ALGO_LEGACY; |
|
423 | pll->flags = 0; |
450 | } |
424 | 451 | ||
425 | if (ASIC_IS_AVIVO(rdev)) { |
452 | if (ASIC_IS_AVIVO(rdev)) { |
426 | if ((rdev->family == CHIP_RS600) || |
453 | if ((rdev->family == CHIP_RS600) || |
427 | (rdev->family == CHIP_RS690) || |
454 | (rdev->family == CHIP_RS690) || |
Line 444... | Line 471... | ||
444 | } |
471 | } |
Line 445... | Line 472... | ||
445 | 472 | ||
446 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
473 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
447 | if (encoder->crtc == crtc) { |
474 | if (encoder->crtc == crtc) { |
- | 475 | radeon_encoder = to_radeon_encoder(encoder); |
|
448 | radeon_encoder = to_radeon_encoder(encoder); |
476 | encoder_mode = atombios_get_encoder_mode(encoder); |
449 | if (ASIC_IS_AVIVO(rdev)) { |
477 | if (ASIC_IS_AVIVO(rdev)) { |
450 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
478 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
451 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
479 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
- | 480 | adjusted_clock = mode->clock * 2; |
|
- | 481 | /* LVDS PLL quirks */ |
|
- | 482 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { |
|
- | 483 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
|
- | 484 | pll->algo = dig->pll_algo; |
|
452 | adjusted_clock = mode->clock * 2; |
485 | } |
453 | } else { |
486 | } else { |
454 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
487 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
455 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
488 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
456 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
489 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
Line 464... | Line 497... | ||
464 | * accordingly based on the encoder/transmitter to work around |
497 | * accordingly based on the encoder/transmitter to work around |
465 | * special hw requirements. |
498 | * special hw requirements. |
466 | */ |
499 | */ |
467 | if (ASIC_IS_DCE3(rdev)) { |
500 | if (ASIC_IS_DCE3(rdev)) { |
468 | union adjust_pixel_clock args; |
501 | union adjust_pixel_clock args; |
469 | struct radeon_encoder_atom_dig *dig; |
- | |
470 | u8 frev, crev; |
502 | u8 frev, crev; |
471 | int index; |
503 | int index; |
Line 472... | Line -... | ||
472 | - | ||
473 | if (!radeon_encoder->enc_priv) |
- | |
474 | return adjusted_clock; |
- | |
475 | dig = radeon_encoder->enc_priv; |
- | |
476 | 504 | ||
477 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
505 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
478 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
506 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
Line 479... | Line 507... | ||
479 | &crev); |
507 | &crev); |
Line 485... | Line 513... | ||
485 | switch (crev) { |
513 | switch (crev) { |
486 | case 1: |
514 | case 1: |
487 | case 2: |
515 | case 2: |
488 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
516 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
489 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
517 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
490 | args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder); |
518 | args.v1.ucEncodeMode = encoder_mode; |
Line 491... | Line 519... | ||
491 | 519 | ||
492 | atom_execute_table(rdev->mode_info.atom_context, |
520 | atom_execute_table(rdev->mode_info.atom_context, |
493 | index, (uint32_t *)&args); |
521 | index, (uint32_t *)&args); |
494 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
522 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
- | 523 | break; |
|
- | 524 | case 3: |
|
- | 525 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); |
|
- | 526 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
|
- | 527 | args.v3.sInput.ucEncodeMode = encoder_mode; |
|
- | 528 | args.v3.sInput.ucDispPllConfig = 0; |
|
- | 529 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
|
- | 530 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
|
- | 531 | ||
- | 532 | if (encoder_mode == ATOM_ENCODER_MODE_DP) |
|
- | 533 | args.v3.sInput.ucDispPllConfig |= |
|
- | 534 | DISPPLL_CONFIG_COHERENT_MODE; |
|
- | 535 | else { |
|
- | 536 | if (dig->coherent_mode) |
|
- | 537 | args.v3.sInput.ucDispPllConfig |= |
|
- | 538 | DISPPLL_CONFIG_COHERENT_MODE; |
|
- | 539 | if (mode->clock > 165000) |
|
- | 540 | args.v3.sInput.ucDispPllConfig |= |
|
- | 541 | DISPPLL_CONFIG_DUAL_LINK; |
|
- | 542 | } |
|
- | 543 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
|
- | 544 | /* may want to enable SS on DP/eDP eventually */ |
|
- | 545 | args.v3.sInput.ucDispPllConfig |= |
|
- | 546 | DISPPLL_CONFIG_SS_ENABLE; |
|
- | 547 | if (mode->clock > 165000) |
|
- | 548 | args.v3.sInput.ucDispPllConfig |= |
|
- | 549 | DISPPLL_CONFIG_DUAL_LINK; |
|
- | 550 | } |
|
- | 551 | atom_execute_table(rdev->mode_info.atom_context, |
|
- | 552 | index, (uint32_t *)&args); |
|
- | 553 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
|
- | 554 | if (args.v3.sOutput.ucRefDiv) { |
|
- | 555 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
|
- | 556 | pll->reference_div = args.v3.sOutput.ucRefDiv; |
|
- | 557 | } |
|
- | 558 | if (args.v3.sOutput.ucPostDiv) { |
|
- | 559 | pll->flags |= RADEON_PLL_USE_POST_DIV; |
|
- | 560 | pll->post_div = args.v3.sOutput.ucPostDiv; |
|
- | 561 | } |
|
495 | break; |
562 | break; |
496 | default: |
563 | default: |
497 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
564 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
498 | return adjusted_clock; |
565 | return adjusted_clock; |
499 | } |
566 | } |
Line 509... | Line 576... | ||
509 | union set_pixel_clock { |
576 | union set_pixel_clock { |
510 | SET_PIXEL_CLOCK_PS_ALLOCATION base; |
577 | SET_PIXEL_CLOCK_PS_ALLOCATION base; |
511 | PIXEL_CLOCK_PARAMETERS v1; |
578 | PIXEL_CLOCK_PARAMETERS v1; |
512 | PIXEL_CLOCK_PARAMETERS_V2 v2; |
579 | PIXEL_CLOCK_PARAMETERS_V2 v2; |
513 | PIXEL_CLOCK_PARAMETERS_V3 v3; |
580 | PIXEL_CLOCK_PARAMETERS_V3 v3; |
- | 581 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
|
514 | }; |
582 | }; |
Line -... | Line 583... | ||
- | 583 | ||
- | 584 | static void atombios_crtc_set_dcpll(struct drm_crtc *crtc) |
|
- | 585 | { |
|
- | 586 | struct drm_device *dev = crtc->dev; |
|
- | 587 | struct radeon_device *rdev = dev->dev_private; |
|
- | 588 | u8 frev, crev; |
|
- | 589 | int index; |
|
- | 590 | union set_pixel_clock args; |
|
- | 591 | ||
- | 592 | memset(&args, 0, sizeof(args)); |
|
- | 593 | ||
- | 594 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
|
- | 595 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
|
- | 596 | &crev); |
|
- | 597 | ||
- | 598 | switch (frev) { |
|
- | 599 | case 1: |
|
- | 600 | switch (crev) { |
|
- | 601 | case 5: |
|
- | 602 | /* if the default dcpll clock is specified, |
|
- | 603 | * SetPixelClock provides the dividers |
|
- | 604 | */ |
|
- | 605 | args.v5.ucCRTC = ATOM_CRTC_INVALID; |
|
- | 606 | args.v5.usPixelClock = rdev->clock.default_dispclk; |
|
- | 607 | args.v5.ucPpll = ATOM_DCPLL; |
|
- | 608 | break; |
|
- | 609 | default: |
|
- | 610 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
|
- | 611 | return; |
|
- | 612 | } |
|
- | 613 | break; |
|
- | 614 | default: |
|
- | 615 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
|
- | 616 | return; |
|
- | 617 | } |
|
- | 618 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
- | 619 | } |
|
515 | 620 | ||
516 | void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
621 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
517 | { |
622 | { |
518 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
623 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
519 | struct drm_device *dev = crtc->dev; |
624 | struct drm_device *dev = crtc->dev; |
520 | struct radeon_device *rdev = dev->dev_private; |
625 | struct radeon_device *rdev = dev->dev_private; |
Line 525... | Line 630... | ||
525 | union set_pixel_clock args; |
630 | union set_pixel_clock args; |
526 | u32 pll_clock = mode->clock; |
631 | u32 pll_clock = mode->clock; |
527 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
632 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
528 | struct radeon_pll *pll; |
633 | struct radeon_pll *pll; |
529 | u32 adjusted_clock; |
634 | u32 adjusted_clock; |
- | 635 | int encoder_mode = 0; |
|
Line 530... | Line 636... | ||
530 | 636 | ||
Line 531... | Line 637... | ||
531 | memset(&args, 0, sizeof(args)); |
637 | memset(&args, 0, sizeof(args)); |
532 | 638 | ||
533 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
639 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
- | 640 | if (encoder->crtc == crtc) { |
|
534 | if (encoder->crtc == crtc) { |
641 | radeon_encoder = to_radeon_encoder(encoder); |
535 | radeon_encoder = to_radeon_encoder(encoder); |
642 | encoder_mode = atombios_get_encoder_mode(encoder); |
536 | break; |
643 | break; |
Line 537... | Line 644... | ||
537 | } |
644 | } |
538 | } |
645 | } |
Line 539... | Line 646... | ||
539 | 646 | ||
- | 647 | if (!radeon_encoder) |
|
540 | if (!radeon_encoder) |
648 | return; |
541 | return; |
649 | |
- | 650 | switch (radeon_crtc->pll_id) { |
|
542 | 651 | case ATOM_PPLL1: |
|
- | 652 | pll = &rdev->clock.p1pll; |
|
- | 653 | break; |
|
- | 654 | case ATOM_PPLL2: |
|
- | 655 | pll = &rdev->clock.p2pll; |
|
- | 656 | break; |
|
- | 657 | case ATOM_DCPLL: |
|
Line 543... | Line 658... | ||
543 | if (radeon_crtc->crtc_id == 0) |
658 | case ATOM_PPLL_INVALID: |
544 | pll = &rdev->clock.p1pll; |
659 | pll = &rdev->clock.dcpll; |
Line 545... | Line -... | ||
545 | else |
- | |
546 | pll = &rdev->clock.p2pll; |
- | |
547 | - | ||
548 | /* adjust pixel clock as needed */ |
- | |
549 | adjusted_clock = atombios_adjust_pll(crtc, mode, pll); |
- | |
550 | - | ||
551 | if (ASIC_IS_AVIVO(rdev)) { |
- | |
552 | if (radeon_new_pll) |
- | |
553 | radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, |
- | |
554 | &fb_div, &frac_fb_div, |
- | |
555 | &ref_div, &post_div); |
660 | break; |
556 | else |
661 | } |
Line 557... | Line 662... | ||
557 | radeon_compute_pll(pll, adjusted_clock, &pll_clock, |
662 | |
558 | &fb_div, &frac_fb_div, |
663 | /* adjust pixel clock as needed */ |
Line 572... | Line 677... | ||
572 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
677 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
573 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
678 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
574 | args.v1.usFbDiv = cpu_to_le16(fb_div); |
679 | args.v1.usFbDiv = cpu_to_le16(fb_div); |
575 | args.v1.ucFracFbDiv = frac_fb_div; |
680 | args.v1.ucFracFbDiv = frac_fb_div; |
576 | args.v1.ucPostDiv = post_div; |
681 | args.v1.ucPostDiv = post_div; |
577 | args.v1.ucPpll = |
682 | args.v1.ucPpll = radeon_crtc->pll_id; |
578 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
- | |
579 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
683 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
580 | args.v1.ucRefDivSrc = 1; |
684 | args.v1.ucRefDivSrc = 1; |
581 | break; |
685 | break; |
582 | case 2: |
686 | case 2: |
583 | args.v2.usPixelClock = cpu_to_le16(mode->clock / 10); |
687 | args.v2.usPixelClock = cpu_to_le16(mode->clock / 10); |
584 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
688 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
585 | args.v2.usFbDiv = cpu_to_le16(fb_div); |
689 | args.v2.usFbDiv = cpu_to_le16(fb_div); |
586 | args.v2.ucFracFbDiv = frac_fb_div; |
690 | args.v2.ucFracFbDiv = frac_fb_div; |
587 | args.v2.ucPostDiv = post_div; |
691 | args.v2.ucPostDiv = post_div; |
588 | args.v2.ucPpll = |
692 | args.v2.ucPpll = radeon_crtc->pll_id; |
589 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
- | |
590 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
693 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
591 | args.v2.ucRefDivSrc = 1; |
694 | args.v2.ucRefDivSrc = 1; |
592 | break; |
695 | break; |
593 | case 3: |
696 | case 3: |
594 | args.v3.usPixelClock = cpu_to_le16(mode->clock / 10); |
697 | args.v3.usPixelClock = cpu_to_le16(mode->clock / 10); |
595 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
698 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
596 | args.v3.usFbDiv = cpu_to_le16(fb_div); |
699 | args.v3.usFbDiv = cpu_to_le16(fb_div); |
597 | args.v3.ucFracFbDiv = frac_fb_div; |
700 | args.v3.ucFracFbDiv = frac_fb_div; |
598 | args.v3.ucPostDiv = post_div; |
701 | args.v3.ucPostDiv = post_div; |
599 | args.v3.ucPpll = |
702 | args.v3.ucPpll = radeon_crtc->pll_id; |
600 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
- | |
601 | args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2); |
703 | args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2); |
602 | args.v3.ucTransmitterId = radeon_encoder->encoder_id; |
704 | args.v3.ucTransmitterId = radeon_encoder->encoder_id; |
603 | args.v3.ucEncoderMode = |
705 | args.v3.ucEncoderMode = encoder_mode; |
- | 706 | break; |
|
- | 707 | case 5: |
|
- | 708 | args.v5.ucCRTC = radeon_crtc->crtc_id; |
|
- | 709 | args.v5.usPixelClock = cpu_to_le16(mode->clock / 10); |
|
- | 710 | args.v5.ucRefDiv = ref_div; |
|
- | 711 | args.v5.usFbDiv = cpu_to_le16(fb_div); |
|
- | 712 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
|
- | 713 | args.v5.ucPostDiv = post_div; |
|
- | 714 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
|
- | 715 | args.v5.ucTransmitterID = radeon_encoder->encoder_id; |
|
604 | atombios_get_encoder_mode(encoder); |
716 | args.v5.ucEncoderMode = encoder_mode; |
- | 717 | args.v5.ucPpll = radeon_crtc->pll_id; |
|
605 | break; |
718 | break; |
606 | default: |
719 | default: |
607 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
720 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
608 | return; |
721 | return; |
609 | } |
722 | } |
Line 614... | Line 727... | ||
614 | } |
727 | } |
Line 615... | Line 728... | ||
615 | 728 | ||
616 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
729 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Line 617... | Line 730... | ||
617 | } |
730 | } |
618 | 731 | ||
619 | static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
732 | static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
- | 733 | struct drm_framebuffer *old_fb) |
|
- | 734 | { |
|
- | 735 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
|
- | 736 | struct drm_device *dev = crtc->dev; |
|
- | 737 | struct radeon_device *rdev = dev->dev_private; |
|
- | 738 | struct radeon_framebuffer *radeon_fb; |
|
- | 739 | struct drm_gem_object *obj; |
|
- | 740 | struct radeon_bo *rbo; |
|
- | 741 | uint64_t fb_location; |
|
- | 742 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
|
- | 743 | int r; |
|
- | 744 | ||
- | 745 | /* no fb bound */ |
|
- | 746 | if (!crtc->fb) { |
|
- | 747 | DRM_DEBUG("No FB bound\n"); |
|
- | 748 | return 0; |
|
- | 749 | } |
|
- | 750 | ||
- | 751 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
|
- | 752 | ||
- | 753 | /* Pin framebuffer & get tilling informations */ |
|
- | 754 | obj = radeon_fb->obj; |
|
- | 755 | rbo = obj->driver_private; |
|
- | 756 | r = radeon_bo_reserve(rbo, false); |
|
- | 757 | if (unlikely(r != 0)) |
|
- | 758 | return r; |
|
- | 759 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
|
- | 760 | if (unlikely(r != 0)) { |
|
- | 761 | radeon_bo_unreserve(rbo); |
|
- | 762 | return -EINVAL; |
|
- | 763 | } |
|
- | 764 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
|
- | 765 | radeon_bo_unreserve(rbo); |
|
- | 766 | ||
- | 767 | switch (crtc->fb->bits_per_pixel) { |
|
- | 768 | case 8: |
|
- | 769 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
|
- | 770 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
|
- | 771 | break; |
|
- | 772 | case 15: |
|
- | 773 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
|
- | 774 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
|
- | 775 | break; |
|
- | 776 | case 16: |
|
- | 777 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
|
- | 778 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
|
- | 779 | break; |
|
- | 780 | case 24: |
|
- | 781 | case 32: |
|
- | 782 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
|
- | 783 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
|
- | 784 | break; |
|
- | 785 | default: |
|
- | 786 | DRM_ERROR("Unsupported screen depth %d\n", |
|
- | 787 | crtc->fb->bits_per_pixel); |
|
- | 788 | return -EINVAL; |
|
- | 789 | } |
|
- | 790 | ||
- | 791 | switch (radeon_crtc->crtc_id) { |
|
- | 792 | case 0: |
|
- | 793 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
|
- | 794 | break; |
|
- | 795 | case 1: |
|
- | 796 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
|
- | 797 | break; |
|
- | 798 | case 2: |
|
- | 799 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
|
- | 800 | break; |
|
- | 801 | case 3: |
|
- | 802 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
|
- | 803 | break; |
|
- | 804 | case 4: |
|
- | 805 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
|
- | 806 | break; |
|
- | 807 | case 5: |
|
- | 808 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
|
- | 809 | break; |
|
- | 810 | default: |
|
- | 811 | break; |
|
- | 812 | } |
|
- | 813 | ||
- | 814 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
|
- | 815 | upper_32_bits(fb_location)); |
|
- | 816 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
|
- | 817 | upper_32_bits(fb_location)); |
|
- | 818 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
|
- | 819 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
|
- | 820 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
|
- | 821 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
|
- | 822 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
|
- | 823 | ||
- | 824 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
|
- | 825 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
|
- | 826 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
|
- | 827 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
|
- | 828 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); |
|
- | 829 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); |
|
- | 830 | ||
- | 831 | fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
|
- | 832 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
|
- | 833 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
|
- | 834 | ||
- | 835 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
|
- | 836 | crtc->mode.vdisplay); |
|
- | 837 | x &= ~3; |
|
- | 838 | y &= ~1; |
|
- | 839 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, |
|
- | 840 | (x << 16) | y); |
|
- | 841 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
|
- | 842 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
|
- | 843 | ||
- | 844 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) |
|
- | 845 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
|
- | 846 | EVERGREEN_INTERLEAVE_EN); |
|
- | 847 | else |
|
- | 848 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
|
- | 849 | ||
- | 850 | if (old_fb && old_fb != crtc->fb) { |
|
- | 851 | radeon_fb = to_radeon_framebuffer(old_fb); |
|
- | 852 | rbo = radeon_fb->obj->driver_private; |
|
620 | struct drm_framebuffer *old_fb) |
853 | r = radeon_bo_reserve(rbo, false); |
- | 854 | if (unlikely(r != 0)) |
|
- | 855 | return r; |
|
- | 856 | radeon_bo_unpin(rbo); |
|
Line -... | Line 857... | ||
- | 857 | radeon_bo_unreserve(rbo); |
|
- | 858 | } |
|
- | 859 | ||
- | 860 | /* Bytes per pixel may have changed */ |
|
- | 861 | radeon_bandwidth_update(rdev); |
|
- | 862 | ||
- | 863 | return 0; |
|
- | 864 | } |
|
- | 865 | ||
621 | { |
866 | static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
622 | ENTER(); |
867 | struct drm_framebuffer *old_fb) |
623 | 868 | { |
|
624 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
869 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
625 | struct drm_device *dev = crtc->dev; |
870 | struct drm_device *dev = crtc->dev; |
Line 744... | Line 989... | ||
744 | } |
989 | } |
Line 745... | Line 990... | ||
745 | 990 | ||
746 | /* Bytes per pixel may have changed */ |
991 | /* Bytes per pixel may have changed */ |
Line 747... | Line -... | ||
747 | radeon_bandwidth_update(rdev); |
- | |
748 | - | ||
749 | LEAVE(); |
992 | radeon_bandwidth_update(rdev); |
750 | 993 | ||
Line 751... | Line 994... | ||
751 | return 0; |
994 | return 0; |
752 | } |
995 | } |
753 | 996 | ||
754 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
997 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
755 | struct drm_framebuffer *old_fb) |
998 | struct drm_framebuffer *old_fb) |
Line -... | Line 999... | ||
- | 999 | { |
|
- | 1000 | struct drm_device *dev = crtc->dev; |
|
756 | { |
1001 | struct radeon_device *rdev = dev->dev_private; |
757 | struct drm_device *dev = crtc->dev; |
1002 | |
758 | struct radeon_device *rdev = dev->dev_private; |
1003 | if (ASIC_IS_DCE4(rdev)) |
759 | 1004 | return evergreen_crtc_set_base(crtc, x, y, old_fb); |
|
760 | if (ASIC_IS_AVIVO(rdev)) |
1005 | else if (ASIC_IS_AVIVO(rdev)) |
Line 785... | Line 1030... | ||
785 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
1030 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
786 | break; |
1031 | break; |
787 | } |
1032 | } |
788 | } |
1033 | } |
Line -... | Line 1034... | ||
- | 1034 | ||
- | 1035 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
|
- | 1036 | { |
|
- | 1037 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
|
- | 1038 | struct drm_device *dev = crtc->dev; |
|
- | 1039 | struct radeon_device *rdev = dev->dev_private; |
|
- | 1040 | struct drm_encoder *test_encoder; |
|
- | 1041 | struct drm_crtc *test_crtc; |
|
- | 1042 | uint32_t pll_in_use = 0; |
|
- | 1043 | ||
- | 1044 | if (ASIC_IS_DCE4(rdev)) { |
|
- | 1045 | /* if crtc is driving DP and we have an ext clock, use that */ |
|
- | 1046 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
|
- | 1047 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { |
|
- | 1048 | if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { |
|
- | 1049 | if (rdev->clock.dp_extclk) |
|
- | 1050 | return ATOM_PPLL_INVALID; |
|
- | 1051 | } |
|
- | 1052 | } |
|
- | 1053 | } |
|
- | 1054 | ||
- | 1055 | /* otherwise, pick one of the plls */ |
|
- | 1056 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
|
- | 1057 | struct radeon_crtc *radeon_test_crtc; |
|
- | 1058 | ||
- | 1059 | if (crtc == test_crtc) |
|
- | 1060 | continue; |
|
- | 1061 | ||
- | 1062 | radeon_test_crtc = to_radeon_crtc(test_crtc); |
|
- | 1063 | if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && |
|
- | 1064 | (radeon_test_crtc->pll_id <= ATOM_PPLL2)) |
|
- | 1065 | pll_in_use |= (1 << radeon_test_crtc->pll_id); |
|
- | 1066 | } |
|
- | 1067 | if (!(pll_in_use & 1)) |
|
- | 1068 | return ATOM_PPLL1; |
|
- | 1069 | return ATOM_PPLL2; |
|
- | 1070 | } else |
|
- | 1071 | return radeon_crtc->crtc_id; |
|
- | 1072 | ||
- | 1073 | } |
|
789 | 1074 | ||
790 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
1075 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
791 | struct drm_display_mode *mode, |
1076 | struct drm_display_mode *mode, |
792 | struct drm_display_mode *adjusted_mode, |
1077 | struct drm_display_mode *adjusted_mode, |
793 | int x, int y, struct drm_framebuffer *old_fb) |
1078 | int x, int y, struct drm_framebuffer *old_fb) |
Line 796... | Line 1081... | ||
796 | struct drm_device *dev = crtc->dev; |
1081 | struct drm_device *dev = crtc->dev; |
797 | struct radeon_device *rdev = dev->dev_private; |
1082 | struct radeon_device *rdev = dev->dev_private; |
Line 798... | Line 1083... | ||
798 | 1083 | ||
Line -... | Line 1084... | ||
- | 1084 | /* TODO color tiling */ |
|
- | 1085 | ||
- | 1086 | /* pick pll */ |
|
799 | /* TODO color tiling */ |
1087 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); |
- | 1088 | ||
- | 1089 | atombios_set_ss(crtc, 0); |
|
- | 1090 | /* always set DCPLL */ |
|
800 | 1091 | if (ASIC_IS_DCE4(rdev)) |
|
801 | atombios_set_ss(crtc, 0); |
1092 | atombios_crtc_set_dcpll(crtc); |
802 | atombios_crtc_set_pll(crtc, adjusted_mode); |
- | |
Line -... | Line 1093... | ||
- | 1093 | atombios_crtc_set_pll(crtc, adjusted_mode); |
|
- | 1094 | atombios_set_ss(crtc, 1); |
|
803 | atombios_set_ss(crtc, 1); |
1095 | |
804 | atombios_crtc_set_timing(crtc, adjusted_mode); |
1096 | if (ASIC_IS_DCE4(rdev)) |
805 | 1097 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
|
- | 1098 | else if (ASIC_IS_AVIVO(rdev)) |
|
806 | if (ASIC_IS_AVIVO(rdev)) |
1099 | atombios_crtc_set_timing(crtc, adjusted_mode); |
807 | atombios_crtc_set_base(crtc, x, y, old_fb); |
1100 | else { |
808 | else { |
- | |
809 | if (radeon_crtc->crtc_id == 0) |
1101 | atombios_crtc_set_timing(crtc, adjusted_mode); |
810 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
1102 | if (radeon_crtc->crtc_id == 0) |
- | 1103 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
|
811 | atombios_crtc_set_base(crtc, x, y, old_fb); |
1104 | radeon_legacy_atom_fixup(crtc); |
812 | radeon_legacy_atom_fixup(crtc); |
1105 | } |
813 | } |
1106 | atombios_crtc_set_base(crtc, x, y, old_fb); |
814 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
1107 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
Line 825... | Line 1118... | ||
825 | return true; |
1118 | return true; |
826 | } |
1119 | } |
Line 827... | Line 1120... | ||
827 | 1120 | ||
828 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
1121 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
829 | { |
1122 | { |
830 | atombios_lock_crtc(crtc, 1); |
1123 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
831 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
1124 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
Line 832... | Line 1125... | ||
832 | } |
1125 | } |
833 | 1126 | ||
834 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
1127 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
835 | { |
1128 | { |
836 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
1129 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
Line 837... | Line 1130... | ||
837 | atombios_lock_crtc(crtc, 0); |
1130 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
838 | } |
1131 | } |
839 | 1132 | ||
Line 848... | Line 1141... | ||
848 | }; |
1141 | }; |
Line 849... | Line 1142... | ||
849 | 1142 | ||
850 | void radeon_atombios_init_crtc(struct drm_device *dev, |
1143 | void radeon_atombios_init_crtc(struct drm_device *dev, |
851 | struct radeon_crtc *radeon_crtc) |
1144 | struct radeon_crtc *radeon_crtc) |
- | 1145 | { |
|
- | 1146 | struct radeon_device *rdev = dev->dev_private; |
|
- | 1147 | ||
- | 1148 | if (ASIC_IS_DCE4(rdev)) { |
|
- | 1149 | switch (radeon_crtc->crtc_id) { |
|
- | 1150 | case 0: |
|
- | 1151 | default: |
|
- | 1152 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
|
- | 1153 | break; |
|
- | 1154 | case 1: |
|
- | 1155 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
|
- | 1156 | break; |
|
- | 1157 | case 2: |
|
- | 1158 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
|
- | 1159 | break; |
|
- | 1160 | case 3: |
|
- | 1161 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
|
- | 1162 | break; |
|
- | 1163 | case 4: |
|
- | 1164 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
|
- | 1165 | break; |
|
- | 1166 | case 5: |
|
- | 1167 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
|
- | 1168 | break; |
|
- | 1169 | } |
|
852 | { |
1170 | } else { |
853 | if (radeon_crtc->crtc_id == 1) |
1171 | if (radeon_crtc->crtc_id == 1) |
854 | radeon_crtc->crtc_offset = |
1172 | radeon_crtc->crtc_offset = |
- | 1173 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
|
- | 1174 | else |
|
- | 1175 | radeon_crtc->crtc_offset = 0; |
|
- | 1176 | } |
|
855 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
1177 | radeon_crtc->pll_id = -1; |
856 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
1178 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |