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Rev 1125 | Rev 1126 | ||
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Line 309... | Line 309... | ||
309 | 309 | ||
310 | printk("executing set pll\n"); |
310 | printk("executing set pll\n"); |
311 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
311 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Line 312... | Line -... | ||
312 | } |
- | |
313 | 312 | } |
|
314 | 313 | ||
315 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
314 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
316 | struct drm_framebuffer *old_fb) |
315 | struct drm_framebuffer *old_fb) |
317 | { |
316 | { |
Line 322... | Line 321... | ||
322 | struct drm_gem_object *obj; |
321 | struct drm_gem_object *obj; |
323 | struct drm_radeon_gem_object *obj_priv; |
322 | struct drm_radeon_gem_object *obj_priv; |
324 | uint64_t fb_location; |
323 | uint64_t fb_location; |
325 | uint32_t fb_format, fb_pitch_pixels; |
324 | uint32_t fb_format, fb_pitch_pixels; |
Line -... | Line 325... | ||
- | 325 | ||
- | 326 | ENTRY(); |
|
326 | 327 | ||
327 | if (!crtc->fb) |
328 | if (!crtc->fb) |
Line 328... | Line 329... | ||
328 | return -EINVAL; |
329 | return -EINVAL; |
Line 334... | Line 335... | ||
334 | 335 | ||
335 | // if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) { |
336 | //if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) { |
336 | // return -EINVAL; |
337 | // return -EINVAL; |
Line -... | Line 338... | ||
- | 338 | //} |
|
- | 339 | ||
- | 340 | fb_location = rdev->mc.vram_location; |
|
- | 341 | ||
- | 342 | dbgprintf("fb_location %x\n", fb_location); |
|
337 | // } |
343 | dbgprintf("bpp %x\n", crtc->fb->bits_per_pixel); |
338 | 344 | ||
339 | switch (crtc->fb->bits_per_pixel) { |
345 | switch (crtc->fb->bits_per_pixel) { |
340 | case 15: |
346 | case 15: |
341 | fb_format = |
347 | fb_format = |
Line 398... | Line 404... | ||
398 | 404 | ||
399 | if (old_fb && old_fb != crtc->fb) { |
405 | if (old_fb && old_fb != crtc->fb) { |
400 | radeon_fb = to_radeon_framebuffer(old_fb); |
406 | radeon_fb = to_radeon_framebuffer(old_fb); |
401 | // radeon_gem_object_unpin(radeon_fb->obj); |
407 | // radeon_gem_object_unpin(radeon_fb->obj); |
- | 408 | } |
|
402 | } |
409 | LEAVE(); |
403 | return 0; |
410 | return 0; |
Line 404... | Line -... | ||
404 | } |
- | |
405 | 411 | } |
|
406 | 412 | ||
407 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
413 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
408 | struct drm_display_mode *mode, |
414 | struct drm_display_mode *mode, |
409 | struct drm_display_mode *adjusted_mode, |
415 | struct drm_display_mode *adjusted_mode, |
Line 413... | Line 419... | ||
413 | struct drm_device *dev = crtc->dev; |
419 | struct drm_device *dev = crtc->dev; |
414 | struct radeon_device *rdev = dev->dev_private; |
420 | struct radeon_device *rdev = dev->dev_private; |
415 | struct drm_encoder *encoder; |
421 | struct drm_encoder *encoder; |
416 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; |
422 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; |
Line -... | Line 423... | ||
- | 423 | ||
- | 424 | ENTRY(); |
|
417 | 425 | ||
418 | /* TODO color tiling */ |
426 | /* TODO color tiling */ |
Line 419... | Line 427... | ||
419 | memset(&crtc_timing, 0, sizeof(crtc_timing)); |
427 | memset(&crtc_timing, 0, sizeof(crtc_timing)); |
420 | 428 | ||
Line 509... | Line 517... | ||
509 | atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing); |
517 | atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing); |
510 | } |
518 | } |
511 | radeon_crtc_set_base(crtc, x, y, old_fb); |
519 | radeon_crtc_set_base(crtc, x, y, old_fb); |
512 | radeon_legacy_atom_set_surface(crtc); |
520 | radeon_legacy_atom_set_surface(crtc); |
513 | } |
521 | } |
- | 522 | LEAVE(); |
|
- | 523 | ||
514 | return 0; |
524 | return 0; |
515 | } |
525 | } |
Line 516... | Line 526... | ||
516 | 526 | ||
517 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
527 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |