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Rev 1430 | Rev 1963 | ||
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Line 71... | Line 71... | ||
71 | #define ATOM_DIGB 1 |
71 | #define ATOM_DIGB 1 |
Line 72... | Line 72... | ||
72 | 72 | ||
73 | #define ATOM_PPLL1 0 |
73 | #define ATOM_PPLL1 0 |
74 | #define ATOM_PPLL2 1 |
74 | #define ATOM_PPLL2 1 |
- | 75 | #define ATOM_DCPLL 2 |
|
- | 76 | #define ATOM_PPLL0 2 |
|
- | 77 | #define ATOM_EXT_PLL1 8 |
|
- | 78 | #define ATOM_EXT_PLL2 9 |
|
75 | #define ATOM_DCPLL 2 |
79 | #define ATOM_EXT_CLOCK 10 |
Line -... | Line 80... | ||
- | 80 | #define ATOM_PPLL_INVALID 0xFF |
|
- | 81 | ||
- | 82 | #define ENCODER_REFCLK_SRC_P1PLL 0 |
|
- | 83 | #define ENCODER_REFCLK_SRC_P2PLL 1 |
|
- | 84 | #define ENCODER_REFCLK_SRC_DCPLL 2 |
|
- | 85 | #define ENCODER_REFCLK_SRC_EXTCLK 3 |
|
76 | #define ATOM_PPLL_INVALID 0xFF |
86 | #define ENCODER_REFCLK_SRC_INVALID 0xFF |
77 | 87 | ||
Line 78... | Line 88... | ||
78 | #define ATOM_SCALER1 0 |
88 | #define ATOM_SCALER1 0 |
79 | #define ATOM_SCALER2 1 |
89 | #define ATOM_SCALER2 1 |
Line 190... | Line 200... | ||
190 | UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ |
200 | UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ |
191 | UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ |
201 | UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ |
192 | /*Image can't be updated, while Driver needs to carry the new table! */ |
202 | /*Image can't be updated, while Driver needs to carry the new table! */ |
193 | }ATOM_COMMON_TABLE_HEADER; |
203 | }ATOM_COMMON_TABLE_HEADER; |
Line -... | Line 204... | ||
- | 204 | ||
- | 205 | /****************************************************************************/ |
|
- | 206 | // Structure stores the ROM header. |
|
194 | 207 | /****************************************************************************/ |
|
195 | typedef struct _ATOM_ROM_HEADER |
208 | typedef struct _ATOM_ROM_HEADER |
196 | { |
209 | { |
197 | ATOM_COMMON_TABLE_HEADER sHeader; |
210 | ATOM_COMMON_TABLE_HEADER sHeader; |
198 | UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, |
211 | UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, |
Line 219... | Line 232... | ||
219 | #ifdef UEFI_BUILD |
232 | #ifdef UEFI_BUILD |
220 | #define UTEMP USHORT |
233 | #define UTEMP USHORT |
221 | #define USHORT void* |
234 | #define USHORT void* |
222 | #endif |
235 | #endif |
Line -... | Line 236... | ||
- | 236 | ||
- | 237 | /****************************************************************************/ |
|
- | 238 | // Structures used in Command.mtb |
|
223 | 239 | /****************************************************************************/ |
|
224 | typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ |
240 | typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ |
225 | USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 |
241 | USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 |
226 | USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON |
242 | USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON |
227 | USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init |
243 | USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init |
Line 310... | Line 326... | ||
310 | #define LVTMATransmitterControl DIG2TransmitterControl |
326 | #define LVTMATransmitterControl DIG2TransmitterControl |
311 | #define SetCRTC_DPM_State GetConditionalGoldenSetting |
327 | #define SetCRTC_DPM_State GetConditionalGoldenSetting |
312 | #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange |
328 | #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange |
313 | #define HPDInterruptService ReadHWAssistedI2CStatus |
329 | #define HPDInterruptService ReadHWAssistedI2CStatus |
314 | #define EnableVGA_Access GetSCLKOverMCLKRatio |
330 | #define EnableVGA_Access GetSCLKOverMCLKRatio |
- | 331 | #define GetDispObjectInfo EnableYUV |
|
Line 315... | Line 332... | ||
315 | 332 | ||
316 | typedef struct _ATOM_MASTER_COMMAND_TABLE |
333 | typedef struct _ATOM_MASTER_COMMAND_TABLE |
317 | { |
334 | { |
318 | ATOM_COMMON_TABLE_HEADER sHeader; |
335 | ATOM_COMMON_TABLE_HEADER sHeader; |
Line 355... | Line 372... | ||
355 | /****************************************************************************/ |
372 | /****************************************************************************/ |
356 | // Structures used by ComputeMemoryEnginePLLTable |
373 | // Structures used by ComputeMemoryEnginePLLTable |
357 | /****************************************************************************/ |
374 | /****************************************************************************/ |
358 | #define COMPUTE_MEMORY_PLL_PARAM 1 |
375 | #define COMPUTE_MEMORY_PLL_PARAM 1 |
359 | #define COMPUTE_ENGINE_PLL_PARAM 2 |
376 | #define COMPUTE_ENGINE_PLL_PARAM 2 |
- | 377 | #define ADJUST_MC_SETTING_PARAM 3 |
|
- | 378 | ||
- | 379 | /****************************************************************************/ |
|
- | 380 | // Structures used by AdjustMemoryControllerTable |
|
- | 381 | /****************************************************************************/ |
|
- | 382 | typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ |
|
- | 383 | { |
|
- | 384 | #if ATOM_BIG_ENDIAN |
|
- | 385 | ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block |
|
- | 386 | ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] |
|
- | 387 | ULONG ulClockFreq:24; |
|
- | 388 | #else |
|
- | 389 | ULONG ulClockFreq:24; |
|
- | 390 | ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] |
|
- | 391 | ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block |
|
- | 392 | #endif |
|
- | 393 | }ATOM_ADJUST_MEMORY_CLOCK_FREQ; |
|
- | 394 | #define POINTER_RETURN_FLAG 0x80 |
|
Line 360... | Line 395... | ||
360 | 395 | ||
361 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS |
396 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS |
362 | { |
397 | { |
363 | ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div |
398 | ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div |
Line 438... | Line 473... | ||
438 | ULONG ulClock:24; //Input= target clock, output = actual clock |
473 | ULONG ulClock:24; //Input= target clock, output = actual clock |
439 | ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly |
474 | ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly |
440 | #endif |
475 | #endif |
441 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; |
476 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; |
Line -... | Line 477... | ||
- | 477 | ||
- | 478 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 |
|
- | 479 | { |
|
- | 480 | union |
|
- | 481 | { |
|
- | 482 | ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter |
|
- | 483 | ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter |
|
- | 484 | }; |
|
- | 485 | UCHAR ucRefDiv; //Output Parameter |
|
- | 486 | UCHAR ucPostDiv; //Output Parameter |
|
- | 487 | union |
|
- | 488 | { |
|
- | 489 | UCHAR ucCntlFlag; //Output Flags |
|
- | 490 | UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode |
|
- | 491 | }; |
|
- | 492 | UCHAR ucReserved; |
|
- | 493 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; |
|
- | 494 | ||
- | 495 | // ucInputFlag |
|
- | 496 | #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode |
|
442 | 497 | ||
443 | typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER |
498 | typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER |
444 | { |
499 | { |
445 | ATOM_COMPUTE_CLOCK_FREQ ulClock; |
500 | ATOM_COMPUTE_CLOCK_FREQ ulClock; |
446 | ULONG ulReserved[2]; |
501 | ULONG ulReserved[2]; |
Line 581... | Line 636... | ||
581 | 636 | ||
582 | //ucConfig |
637 | //ucConfig |
583 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 |
638 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 |
584 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 |
639 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 |
- | 640 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 |
|
585 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 |
641 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 |
586 | #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 |
642 | #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 |
587 | #define ATOM_ENCODER_CONFIG_LINKA 0x00 |
643 | #define ATOM_ENCODER_CONFIG_LINKA 0x00 |
588 | #define ATOM_ENCODER_CONFIG_LINKB 0x04 |
644 | #define ATOM_ENCODER_CONFIG_LINKB 0x04 |
589 | #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA |
645 | #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA |
Line 606... | Line 662... | ||
606 | #define ATOM_ENCODER_MODE_SDVO 4 |
662 | #define ATOM_ENCODER_MODE_SDVO 4 |
607 | #define ATOM_ENCODER_MODE_DP_AUDIO 5 |
663 | #define ATOM_ENCODER_MODE_DP_AUDIO 5 |
608 | #define ATOM_ENCODER_MODE_TV 13 |
664 | #define ATOM_ENCODER_MODE_TV 13 |
609 | #define ATOM_ENCODER_MODE_CV 14 |
665 | #define ATOM_ENCODER_MODE_CV 14 |
610 | #define ATOM_ENCODER_MODE_CRT 15 |
666 | #define ATOM_ENCODER_MODE_CRT 15 |
- | 667 | #define ATOM_ENCODER_MODE_DVO 16 |
|
- | 668 | #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 |
|
- | 669 | #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 |
|
Line 611... | Line 670... | ||
611 | 670 | ||
612 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 |
671 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 |
613 | { |
672 | { |
614 | #if ATOM_BIG_ENDIAN |
673 | #if ATOM_BIG_ENDIAN |
Line 659... | Line 718... | ||
659 | // ATOM_DISABLE |
718 | // ATOM_DISABLE |
660 | // ATOM_ENABLE |
719 | // ATOM_ENABLE |
661 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 |
720 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 |
662 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 |
721 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 |
663 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a |
722 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a |
- | 723 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 |
|
664 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b |
724 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b |
665 | #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c |
725 | #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c |
666 | #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d |
726 | #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d |
667 | #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e |
727 | #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e |
668 | #define ATOM_ENCODER_CMD_SETUP 0x0f |
728 | #define ATOM_ENCODER_CMD_SETUP 0x0f |
- | 729 | #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 |
|
Line 669... | Line 730... | ||
669 | 730 | ||
670 | // ucStatus |
731 | // ucStatus |
671 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 |
732 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 |
Line -... | Line 733... | ||
- | 733 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 |
|
- | 734 | ||
672 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 |
735 | //ucTableFormatRevision=1 |
673 | 736 | //ucTableContentRevision=3 |
|
674 | // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver |
737 | // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver |
675 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 |
738 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 |
676 | { |
739 | { |
677 | #if ATOM_BIG_ENDIAN |
740 | #if ATOM_BIG_ENDIAN |
678 | UCHAR ucReserved1:1; |
741 | UCHAR ucReserved1:1; |
679 | UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F |
742 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
680 | UCHAR ucReserved:3; |
743 | UCHAR ucReserved:3; |
681 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
744 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
682 | #else |
745 | #else |
683 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
746 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
684 | UCHAR ucReserved:3; |
747 | UCHAR ucReserved:3; |
685 | UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F |
748 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
686 | UCHAR ucReserved1:1; |
749 | UCHAR ucReserved1:1; |
Line -... | Line 750... | ||
- | 750 | #endif |
|
- | 751 | }ATOM_DIG_ENCODER_CONFIG_V3; |
|
- | 752 | ||
687 | #endif |
753 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 |
- | 754 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 |
|
- | 755 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 |
|
- | 756 | #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 |
|
- | 757 | #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 |
|
- | 758 | #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 |
|
- | 759 | #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 |
|
688 | }ATOM_DIG_ENCODER_CONFIG_V3; |
- | |
Line 689... | Line 760... | ||
689 | 760 | #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 |
|
690 | #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 |
761 | #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 |
691 | 762 | #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 |
|
692 | 763 | ||
693 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 |
764 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 |
- | 765 | { |
|
694 | { |
766 | USHORT usPixelClock; // in 10KHz; for bios convenient |
695 | USHORT usPixelClock; // in 10KHz; for bios convenient |
767 | ATOM_DIG_ENCODER_CONFIG_V3 acConfig; |
696 | ATOM_DIG_ENCODER_CONFIG_V3 acConfig; |
768 | UCHAR ucAction; |
697 | UCHAR ucAction; |
769 | union { |
698 | UCHAR ucEncoderMode; |
770 | UCHAR ucEncoderMode; |
699 | // =0: DP encoder |
771 | // =0: DP encoder |
700 | // =1: LVDS encoder |
772 | // =1: LVDS encoder |
- | 773 | // =2: DVI encoder |
|
- | 774 | // =3: HDMI encoder |
|
- | 775 | // =4: SDVO encoder |
|
- | 776 | // =5: DP audio |
|
- | 777 | UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE |
|
701 | // =2: DVI encoder |
778 | // =0: external DP |
702 | // =3: HDMI encoder |
779 | // =1: internal DP2 |
703 | // =4: SDVO encoder |
780 | // =0x11: internal DP1 for NutMeg/Travis DP translator |
704 | // =5: DP audio |
781 | }; |
Line -... | Line 782... | ||
- | 782 | UCHAR ucLaneNum; // how many lanes to enable |
|
- | 783 | UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP |
|
- | 784 | UCHAR ucReserved; |
|
- | 785 | }DIG_ENCODER_CONTROL_PARAMETERS_V3; |
|
- | 786 | ||
- | 787 | //ucTableFormatRevision=1 |
|
- | 788 | //ucTableContentRevision=4 |
|
- | 789 | // start from NI |
|
- | 790 | // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver |
|
- | 791 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 |
|
- | 792 | { |
|
- | 793 | #if ATOM_BIG_ENDIAN |
|
- | 794 | UCHAR ucReserved1:1; |
|
- | 795 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
|
- | 796 | UCHAR ucReserved:2; |
|
- | 797 | UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version |
|
- | 798 | #else |
|
- | 799 | UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version |
|
- | 800 | UCHAR ucReserved:2; |
|
- | 801 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
|
- | 802 | UCHAR ucReserved1:1; |
|
- | 803 | #endif |
|
- | 804 | }ATOM_DIG_ENCODER_CONFIG_V4; |
|
- | 805 | ||
- | 806 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 |
|
- | 807 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 |
|
- | 808 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 |
|
- | 809 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 |
|
- | 810 | #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 |
|
- | 811 | #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 |
|
- | 812 | #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 |
|
- | 813 | #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 |
|
- | 814 | #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 |
|
- | 815 | #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 |
|
- | 816 | #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 |
|
- | 817 | ||
- | 818 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 |
|
- | 819 | { |
|
- | 820 | USHORT usPixelClock; // in 10KHz; for bios convenient |
|
- | 821 | union{ |
|
- | 822 | ATOM_DIG_ENCODER_CONFIG_V4 acConfig; |
|
- | 823 | UCHAR ucConfig; |
|
- | 824 | }; |
|
- | 825 | UCHAR ucAction; |
|
- | 826 | union { |
|
- | 827 | UCHAR ucEncoderMode; |
|
- | 828 | // =0: DP encoder |
|
- | 829 | // =1: LVDS encoder |
|
- | 830 | // =2: DVI encoder |
|
- | 831 | // =3: HDMI encoder |
|
- | 832 | // =4: SDVO encoder |
|
- | 833 | // =5: DP audio |
|
- | 834 | UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE |
|
- | 835 | // =0: external DP |
|
- | 836 | // =1: internal DP2 |
|
- | 837 | // =0x11: internal DP1 for NutMeg/Travis DP translator |
|
Line 705... | Line 838... | ||
705 | UCHAR ucLaneNum; // how many lanes to enable |
838 | }; |
706 | UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP |
839 | UCHAR ucLaneNum; // how many lanes to enable |
707 | UCHAR ucReserved; |
840 | UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP |
708 | }DIG_ENCODER_CONTROL_PARAMETERS_V3; |
841 | UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version |
709 | 842 | }DIG_ENCODER_CONTROL_PARAMETERS_V4; |
|
710 | 843 | ||
711 | // define ucBitPerColor: |
844 | // define ucBitPerColor: |
Line -... | Line 845... | ||
- | 845 | #define PANEL_BPC_UNDEFINE 0x00 |
|
- | 846 | #define PANEL_6BIT_PER_COLOR 0x01 |
|
- | 847 | #define PANEL_8BIT_PER_COLOR 0x02 |
|
- | 848 | #define PANEL_10BIT_PER_COLOR 0x03 |
|
- | 849 | #define PANEL_12BIT_PER_COLOR 0x04 |
|
712 | #define PANEL_BPC_UNDEFINE 0x00 |
850 | #define PANEL_16BIT_PER_COLOR 0x05 |
713 | #define PANEL_6BIT_PER_COLOR 0x01 |
851 | |
714 | #define PANEL_8BIT_PER_COLOR 0x02 |
852 | //define ucPanelMode |
715 | #define PANEL_10BIT_PER_COLOR 0x03 |
853 | #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 |
716 | #define PANEL_12BIT_PER_COLOR 0x04 |
854 | #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 |
Line 891... | Line 1029... | ||
891 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
1029 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
892 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
1030 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
893 | #endif |
1031 | #endif |
894 | }ATOM_DIG_TRANSMITTER_CONFIG_V3; |
1032 | }ATOM_DIG_TRANSMITTER_CONFIG_V3; |
Line -... | Line 1033... | ||
- | 1033 | ||
895 | 1034 | ||
896 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 |
1035 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 |
897 | { |
1036 | { |
898 | union |
1037 | union |
899 | { |
1038 | { |
Line 934... | Line 1073... | ||
934 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 |
1073 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 |
935 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB |
1074 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB |
936 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD |
1075 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD |
937 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF |
1076 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF |
Line -... | Line 1077... | ||
- | 1077 | ||
- | 1078 | ||
- | 1079 | /****************************************************************************/ |
|
- | 1080 | // Structures used by UNIPHYTransmitterControlTable V1.4 |
|
- | 1081 | // ASIC Families: NI |
|
- | 1082 | // ucTableFormatRevision=1 |
|
- | 1083 | // ucTableContentRevision=4 |
|
- | 1084 | /****************************************************************************/ |
|
- | 1085 | typedef struct _ATOM_DP_VS_MODE_V4 |
|
- | 1086 | { |
|
- | 1087 | UCHAR ucLaneSel; |
|
- | 1088 | union |
|
- | 1089 | { |
|
- | 1090 | UCHAR ucLaneSet; |
|
- | 1091 | struct { |
|
- | 1092 | #if ATOM_BIG_ENDIAN |
|
- | 1093 | UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 |
|
- | 1094 | UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level |
|
- | 1095 | UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level |
|
- | 1096 | #else |
|
- | 1097 | UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level |
|
- | 1098 | UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level |
|
- | 1099 | UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 |
|
- | 1100 | #endif |
|
- | 1101 | }; |
|
- | 1102 | }; |
|
- | 1103 | }ATOM_DP_VS_MODE_V4; |
|
- | 1104 | ||
- | 1105 | typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 |
|
- | 1106 | { |
|
- | 1107 | #if ATOM_BIG_ENDIAN |
|
- | 1108 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
|
- | 1109 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
|
- | 1110 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
|
- | 1111 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New |
|
- | 1112 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F |
|
- | 1113 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
|
- | 1114 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
|
- | 1115 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
|
- | 1116 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
|
- | 1117 | #else |
|
- | 1118 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
|
- | 1119 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
|
- | 1120 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
|
- | 1121 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
|
- | 1122 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F |
|
- | 1123 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New |
|
- | 1124 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
|
- | 1125 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
|
- | 1126 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
|
- | 1127 | #endif |
|
- | 1128 | }ATOM_DIG_TRANSMITTER_CONFIG_V4; |
|
- | 1129 | ||
- | 1130 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 |
|
- | 1131 | { |
|
- | 1132 | union |
|
- | 1133 | { |
|
- | 1134 | USHORT usPixelClock; // in 10KHz; for bios convenient |
|
- | 1135 | USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h |
|
- | 1136 | ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version |
|
- | 1137 | }; |
|
- | 1138 | union |
|
- | 1139 | { |
|
- | 1140 | ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; |
|
- | 1141 | UCHAR ucConfig; |
|
- | 1142 | }; |
|
- | 1143 | UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX |
|
- | 1144 | UCHAR ucLaneNum; |
|
- | 1145 | UCHAR ucReserved[3]; |
|
- | 1146 | }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; |
|
- | 1147 | ||
- | 1148 | //ucConfig |
|
- | 1149 | //Bit0 |
|
- | 1150 | #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 |
|
- | 1151 | //Bit1 |
|
- | 1152 | #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 |
|
- | 1153 | //Bit2 |
|
- | 1154 | #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 |
|
- | 1155 | #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 |
|
- | 1156 | #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 |
|
- | 1157 | // Bit3 |
|
- | 1158 | #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 |
|
- | 1159 | #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 |
|
- | 1160 | #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 |
|
- | 1161 | // Bit5:4 |
|
- | 1162 | #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 |
|
- | 1163 | #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 |
|
- | 1164 | #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 |
|
- | 1165 | #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 |
|
- | 1166 | #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 |
|
- | 1167 | // Bit7:6 |
|
- | 1168 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 |
|
- | 1169 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB |
|
- | 1170 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD |
|
- | 1171 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF |
|
- | 1172 | ||
- | 1173 | ||
- | 1174 | /****************************************************************************/ |
|
- | 1175 | // Structures used by ExternalEncoderControlTable V1.3 |
|
- | 1176 | // ASIC Families: Evergreen, Llano, NI |
|
- | 1177 | // ucTableFormatRevision=1 |
|
- | 1178 | // ucTableContentRevision=3 |
|
- | 1179 | /****************************************************************************/ |
|
- | 1180 | ||
- | 1181 | typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 |
|
- | 1182 | { |
|
- | 1183 | union{ |
|
- | 1184 | USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT |
|
- | 1185 | USHORT usConnectorId; // connector id, valid when ucAction = INIT |
|
- | 1186 | }; |
|
- | 1187 | UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT |
|
- | 1188 | UCHAR ucAction; // |
|
- | 1189 | UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT |
|
- | 1190 | UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT |
|
- | 1191 | UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP |
|
- | 1192 | UCHAR ucReserved; |
|
- | 1193 | }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; |
|
- | 1194 | ||
- | 1195 | // ucAction |
|
- | 1196 | #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 |
|
- | 1197 | #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 |
|
- | 1198 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 |
|
- | 1199 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f |
|
- | 1200 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 |
|
- | 1201 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 |
|
- | 1202 | #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 |
|
- | 1203 | ||
- | 1204 | // ucConfig |
|
- | 1205 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 |
|
- | 1206 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 |
|
- | 1207 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 |
|
- | 1208 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 |
|
- | 1209 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 |
|
- | 1210 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 |
|
- | 1211 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 |
|
- | 1212 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 |
|
- | 1213 | ||
- | 1214 | typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 |
|
- | 1215 | { |
|
- | 1216 | EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; |
|
- | 1217 | ULONG ulReserved[2]; |
|
- | 1218 | }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; |
|
- | 1219 | ||
938 | 1220 | ||
939 | /****************************************************************************/ |
1221 | /****************************************************************************/ |
940 | // Structures used by DAC1OuputControlTable |
1222 | // Structures used by DAC1OuputControlTable |
941 | // DAC2OuputControlTable |
1223 | // DAC2OuputControlTable |
942 | // LVTMAOutputControlTable (Before DEC30) |
1224 | // LVTMAOutputControlTable (Before DEC30) |
Line 1140... | Line 1422... | ||
1140 | #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 |
1422 | #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 |
1141 | // V1.4 for RoadRunner |
1423 | // V1.4 for RoadRunner |
1142 | #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 |
1424 | #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 |
1143 | #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 |
1425 | #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 |
Line -... | Line 1426... | ||
- | 1426 | ||
1144 | 1427 | ||
1145 | typedef struct _PIXEL_CLOCK_PARAMETERS_V3 |
1428 | typedef struct _PIXEL_CLOCK_PARAMETERS_V3 |
1146 | { |
1429 | { |
1147 | USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) |
1430 | USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) |
1148 | // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. |
1431 | // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. |
Line 1200... | Line 1483... | ||
1200 | #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 |
1483 | #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 |
1201 | #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 |
1484 | #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 |
1202 | #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 |
1485 | #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 |
1203 | #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 |
1486 | #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 |
Line -... | Line 1487... | ||
- | 1487 | ||
- | 1488 | typedef struct _CRTC_PIXEL_CLOCK_FREQ |
|
- | 1489 | { |
|
- | 1490 | #if ATOM_BIG_ENDIAN |
|
- | 1491 | ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to |
|
- | 1492 | // drive the pixel clock. not used for DCPLL case. |
|
- | 1493 | ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. |
|
- | 1494 | // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. |
|
- | 1495 | #else |
|
- | 1496 | ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. |
|
- | 1497 | // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. |
|
- | 1498 | ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to |
|
- | 1499 | // drive the pixel clock. not used for DCPLL case. |
|
- | 1500 | #endif |
|
- | 1501 | }CRTC_PIXEL_CLOCK_FREQ; |
|
- | 1502 | ||
- | 1503 | typedef struct _PIXEL_CLOCK_PARAMETERS_V6 |
|
- | 1504 | { |
|
- | 1505 | union{ |
|
- | 1506 | CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency |
|
- | 1507 | ULONG ulDispEngClkFreq; // dispclk frequency |
|
- | 1508 | }; |
|
- | 1509 | USHORT usFbDiv; // feedback divider integer part. |
|
- | 1510 | UCHAR ucPostDiv; // post divider. |
|
- | 1511 | UCHAR ucRefDiv; // Reference divider |
|
- | 1512 | UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL |
|
- | 1513 | UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, |
|
- | 1514 | // indicate which graphic encoder will be used. |
|
- | 1515 | UCHAR ucEncoderMode; // Encoder mode: |
|
- | 1516 | UCHAR ucMiscInfo; // bit[0]= Force program PPLL |
|
- | 1517 | // bit[1]= when VGA timing is used. |
|
- | 1518 | // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp |
|
- | 1519 | // bit[4]= RefClock source for PPLL. |
|
- | 1520 | // =0: XTLAIN( default mode ) |
|
- | 1521 | // =1: other external clock source, which is pre-defined |
|
- | 1522 | // by VBIOS depend on the feature required. |
|
- | 1523 | // bit[7:5]: reserved. |
|
- | 1524 | ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) |
|
- | 1525 | ||
- | 1526 | }PIXEL_CLOCK_PARAMETERS_V6; |
|
- | 1527 | ||
- | 1528 | #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 |
|
- | 1529 | #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 |
|
- | 1530 | #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c |
|
- | 1531 | #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 |
|
- | 1532 | #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 |
|
- | 1533 | #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 |
|
- | 1534 | #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c |
|
- | 1535 | #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 |
|
1204 | 1536 | ||
1205 | typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 |
1537 | typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 |
1206 | { |
1538 | { |
1207 | PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; |
1539 | PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; |
Line 1239... | Line 1571... | ||
1239 | #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS |
1571 | #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS |
Line 1240... | Line 1572... | ||
1240 | 1572 | ||
1241 | typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 |
1573 | typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 |
1242 | { |
1574 | { |
1243 | USHORT usPixelClock; // target pixel clock |
1575 | USHORT usPixelClock; // target pixel clock |
1244 | UCHAR ucTransmitterID; // transmitter id defined in objectid.h |
1576 | UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h |
1245 | UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI |
1577 | UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI |
- | 1578 | UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX |
|
1246 | UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX |
1579 | UCHAR ucExtTransmitterID; // external encoder id. |
1247 | UCHAR ucReserved[3]; |
1580 | UCHAR ucReserved[2]; |
Line 1248... | Line 1581... | ||
1248 | }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; |
1581 | }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; |
1249 | 1582 | ||
1250 | // usDispPllConfig v1.2 for RoadRunner |
1583 | // usDispPllConfig v1.2 for RoadRunner |
Line 1312... | Line 1645... | ||
1312 | //Maxium 8 bytes,the data read in will be placed in the parameter space. |
1645 | //Maxium 8 bytes,the data read in will be placed in the parameter space. |
1313 | //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed |
1646 | //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed |
1314 | typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS |
1647 | typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS |
1315 | { |
1648 | { |
1316 | USHORT usPrescale; //Ratio between Engine clock and I2C clock |
1649 | USHORT usPrescale; //Ratio between Engine clock and I2C clock |
1317 | USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID |
1650 | USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID |
1318 | USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status |
1651 | USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status |
1319 | //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte |
1652 | //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte |
1320 | UCHAR ucSlaveAddr; //Read from which slave |
1653 | UCHAR ucSlaveAddr; //Read from which slave |
1321 | UCHAR ucLineNumber; //Read from which HW assisted line |
1654 | UCHAR ucLineNumber; //Read from which HW assisted line |
1322 | }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; |
1655 | }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; |
Line 1356... | Line 1689... | ||
1356 | 1689 | ||
1357 | 1690 | ||
Line -... | Line 1691... | ||
- | 1691 | /**************************************************************************/ |
|
1358 | /**************************************************************************/ |
1692 | #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
1359 | #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
1693 | |
1360 | 1694 | ||
1361 | /****************************************************************************/ |
1695 | /****************************************************************************/ |
1362 | // Structures used by PowerConnectorDetectionTable |
1696 | // Structures used by PowerConnectorDetectionTable |
Line 1436... | Line 1770... | ||
1436 | #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF |
1770 | #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF |
1437 | #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 |
1771 | #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 |
1438 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 |
1772 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 |
1439 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 |
1773 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 |
Line -... | Line 1774... | ||
- | 1774 | ||
- | 1775 | // Used by DCE5.0 |
|
- | 1776 | typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 |
|
- | 1777 | { |
|
- | 1778 | USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 |
|
- | 1779 | UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. |
|
- | 1780 | // Bit[1]: 1-Ext. 0-Int. |
|
- | 1781 | // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL |
|
- | 1782 | // Bits[7:4] reserved |
|
- | 1783 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
|
- | 1784 | USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] |
|
- | 1785 | USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC |
|
- | 1786 | }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; |
|
- | 1787 | ||
- | 1788 | #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 |
|
- | 1789 | #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 |
|
- | 1790 | #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 |
|
- | 1791 | #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c |
|
- | 1792 | #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 |
|
- | 1793 | #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 |
|
- | 1794 | #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 |
|
- | 1795 | #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF |
|
- | 1796 | #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 |
|
- | 1797 | #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 |
|
- | 1798 | #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 |
|
1440 | 1799 | ||
Line 1441... | Line 1800... | ||
1441 | #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL |
1800 | #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL |
Line 1442... | Line 1801... | ||
1442 | 1801 | ||
Line 1704... | Line 2063... | ||
1704 | USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios |
2063 | USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios |
1705 | USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios |
2064 | USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios |
1706 | USHORT StandardVESA_Timing; // Only used by Bios |
2065 | USHORT StandardVESA_Timing; // Only used by Bios |
1707 | USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 |
2066 | USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 |
1708 | USHORT DAC_Info; // Will be obsolete from R600 |
2067 | USHORT DAC_Info; // Will be obsolete from R600 |
1709 | USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 |
2068 | USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info |
1710 | USHORT TMDS_Info; // Will be obsolete from R600 |
2069 | USHORT TMDS_Info; // Will be obsolete from R600 |
1711 | USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 |
2070 | USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 |
1712 | USHORT SupportedDevicesInfo; // Will be obsolete from R600 |
2071 | USHORT SupportedDevicesInfo; // Will be obsolete from R600 |
1713 | USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 |
2072 | USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 |
1714 | USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 |
2073 | USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 |
Line 1734... | Line 2093... | ||
1734 | USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 |
2093 | USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 |
1735 | USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 |
2094 | USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 |
1736 | USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 |
2095 | USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 |
1737 | }ATOM_MASTER_LIST_OF_DATA_TABLES; |
2096 | }ATOM_MASTER_LIST_OF_DATA_TABLES; |
Line -... | Line 2097... | ||
- | 2097 | ||
- | 2098 | // For backward compatible |
|
- | 2099 | #define LVDS_Info LCD_Info |
|
1738 | 2100 | ||
1739 | typedef struct _ATOM_MASTER_DATA_TABLE |
2101 | typedef struct _ATOM_MASTER_DATA_TABLE |
1740 | { |
2102 | { |
1741 | ATOM_COMMON_TABLE_HEADER sHeader; |
2103 | ATOM_COMMON_TABLE_HEADER sHeader; |
1742 | ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; |
2104 | ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; |
Line -... | Line 2105... | ||
- | 2105 | }ATOM_MASTER_DATA_TABLE; |
|
1743 | }ATOM_MASTER_DATA_TABLE; |
2106 | |
1744 | 2107 | ||
1745 | /****************************************************************************/ |
2108 | /****************************************************************************/ |
1746 | // Structure used in MultimediaCapabilityInfoTable |
2109 | // Structure used in MultimediaCapabilityInfoTable |
1747 | /****************************************************************************/ |
2110 | /****************************************************************************/ |
Line 1774... | Line 2137... | ||
1774 | UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2137 | UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
1775 | UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2138 | UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
1776 | UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2139 | UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
1777 | }ATOM_MULTIMEDIA_CONFIG_INFO; |
2140 | }ATOM_MULTIMEDIA_CONFIG_INFO; |
Line -... | Line 2141... | ||
- | 2141 | ||
1778 | 2142 | ||
1779 | /****************************************************************************/ |
2143 | /****************************************************************************/ |
1780 | // Structures used in FirmwareInfoTable |
2144 | // Structures used in FirmwareInfoTable |
Line 1781... | Line 2145... | ||
1781 | /****************************************************************************/ |
2145 | /****************************************************************************/ |
1782 | 2146 | ||
1783 | // usBIOSCapability Defintion: |
2147 | // usBIOSCapability Definition: |
1784 | // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; |
2148 | // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; |
1785 | // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; |
2149 | // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; |
1786 | // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; |
2150 | // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; |
Line 2029... | Line 2393... | ||
2029 | USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock |
2393 | USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock |
2030 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2394 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2031 | UCHAR ucReserved4[3]; |
2395 | UCHAR ucReserved4[3]; |
2032 | }ATOM_FIRMWARE_INFO_V2_1; |
2396 | }ATOM_FIRMWARE_INFO_V2_1; |
Line -... | Line 2397... | ||
- | 2397 | ||
- | 2398 | //the structure below to be used from NI |
|
- | 2399 | //ucTableFormatRevision=2 |
|
- | 2400 | //ucTableContentRevision=2 |
|
- | 2401 | typedef struct _ATOM_FIRMWARE_INFO_V2_2 |
|
- | 2402 | { |
|
- | 2403 | ATOM_COMMON_TABLE_HEADER sHeader; |
|
- | 2404 | ULONG ulFirmwareRevision; |
|
- | 2405 | ULONG ulDefaultEngineClock; //In 10Khz unit |
|
- | 2406 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
|
- | 2407 | ULONG ulReserved[2]; |
|
- | 2408 | ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* |
|
- | 2409 | ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* |
|
- | 2410 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
|
- | 2411 | ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? |
|
- | 2412 | ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. |
|
- | 2413 | UCHAR ucReserved3; //Was ucASICMaxTemperature; |
|
- | 2414 | UCHAR ucMinAllowedBL_Level; |
|
- | 2415 | USHORT usBootUpVDDCVoltage; //In MV unit |
|
- | 2416 | USHORT usLcdMinPixelClockPLL_Output; // In MHz unit |
|
- | 2417 | USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit |
|
- | 2418 | ULONG ulReserved4; //Was ulAsicMaximumVoltage |
|
- | 2419 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
|
- | 2420 | ULONG ulReserved5; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input |
|
- | 2421 | ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input |
|
- | 2422 | ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output |
|
- | 2423 | USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC |
|
- | 2424 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
|
- | 2425 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
|
- | 2426 | USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; |
|
- | 2427 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
|
- | 2428 | USHORT usCoreReferenceClock; //In 10Khz unit |
|
- | 2429 | USHORT usMemoryReferenceClock; //In 10Khz unit |
|
- | 2430 | USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock |
|
- | 2431 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
|
- | 2432 | UCHAR ucReserved9[3]; |
|
- | 2433 | USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; |
|
- | 2434 | USHORT usReserved12; |
|
- | 2435 | ULONG ulReserved10[3]; // New added comparing to previous version |
|
Line 2033... | Line 2436... | ||
2033 | 2436 | }ATOM_FIRMWARE_INFO_V2_2; |
|
Line 2034... | Line 2437... | ||
2034 | 2437 | ||
2035 | #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_1 |
2438 | #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 |
2036 | 2439 | ||
2037 | /****************************************************************************/ |
2440 | /****************************************************************************/ |
Line 2210... | Line 2613... | ||
2210 | 2613 | ||
2211 | ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin |
2614 | ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin |
2212 | ucDockingPinBit: which bit in this register to read the pin status; |
2615 | ucDockingPinBit: which bit in this register to read the pin status; |
Line 2213... | Line 2616... | ||
2213 | ucDockingPinPolarity:Polarity of the pin when docked; |
2616 | ucDockingPinPolarity:Polarity of the pin when docked; |
Line 2214... | Line 2617... | ||
2214 | 2617 | ||
Line 2215... | Line 2618... | ||
2215 | ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0 |
2618 | ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 |
2216 | 2619 | ||
Line 2248... | Line 2651... | ||
2248 | usMaxDownStreamHTLinkWidth: same as above. |
2651 | usMaxDownStreamHTLinkWidth: same as above. |
2249 | usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. |
2652 | usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. |
2250 | usMinDownStreamHTLinkWidth: same as above. |
2653 | usMinDownStreamHTLinkWidth: same as above. |
2251 | */ |
2654 | */ |
Line -... | Line 2655... | ||
- | 2655 | ||
- | 2656 | // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition |
|
- | 2657 | #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 |
|
- | 2658 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 |
|
- | 2659 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 |
|
- | 2660 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 |
|
- | 2661 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 |
|
- | 2662 | ||
Line 2252... | Line 2663... | ||
2252 | 2663 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH // this deff reflects max defined CPU code |
|
2253 | 2664 | ||
2254 | #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 |
2665 | #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 |
2255 | #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 |
2666 | #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 |
Line 2776... | Line 3187... | ||
2776 | 3187 | ||
2777 | // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} |
3188 | // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} |
2778 | #define PANEL_RANDOM_DITHER 0x80 |
3189 | #define PANEL_RANDOM_DITHER 0x80 |
Line -... | Line 3190... | ||
- | 3190 | #define PANEL_RANDOM_DITHER_MASK 0x80 |
|
- | 3191 | ||
- | 3192 | #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this |
|
- | 3193 | ||
- | 3194 | /****************************************************************************/ |
|
- | 3195 | // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 |
|
- | 3196 | // ASIC Families: NI |
|
- | 3197 | // ucTableFormatRevision=1 |
|
- | 3198 | // ucTableContentRevision=3 |
|
- | 3199 | /****************************************************************************/ |
|
- | 3200 | typedef struct _ATOM_LCD_INFO_V13 |
|
- | 3201 | { |
|
- | 3202 | ATOM_COMMON_TABLE_HEADER sHeader; |
|
- | 3203 | ATOM_DTD_FORMAT sLCDTiming; |
|
- | 3204 | USHORT usExtInfoTableOffset; |
|
- | 3205 | USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. |
|
- | 3206 | ULONG ulReserved0; |
|
- | 3207 | UCHAR ucLCD_Misc; // Reorganized in V13 |
|
- | 3208 | // Bit0: {=0:single, =1:dual}, |
|
- | 3209 | // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, |
|
- | 3210 | // Bit3:2: {Grey level} |
|
- | 3211 | // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) |
|
- | 3212 | // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? |
|
- | 3213 | UCHAR ucPanelDefaultRefreshRate; |
|
- | 3214 | UCHAR ucPanelIdentification; |
|
- | 3215 | UCHAR ucSS_Id; |
|
- | 3216 | USHORT usLCDVenderID; |
|
- | 3217 | USHORT usLCDProductID; |
|
- | 3218 | UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 |
|
- | 3219 | // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own |
|
- | 3220 | // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED |
|
- | 3221 | // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) |
|
- | 3222 | // Bit7-3: Reserved |
|
- | 3223 | UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable |
|
- | 3224 | USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 |
|
- | 3225 | ||
- | 3226 | UCHAR ucPowerSequenceDIGONtoDE_in4Ms; |
|
- | 3227 | UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; |
|
- | 3228 | UCHAR ucPowerSequenceDEtoDIGON_in4Ms; |
|
- | 3229 | UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; |
|
- | 3230 | ||
- | 3231 | UCHAR ucOffDelay_in4Ms; |
|
- | 3232 | UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; |
|
- | 3233 | UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; |
|
- | 3234 | UCHAR ucReserved1; |
|
- | 3235 | ||
- | 3236 | ULONG ulReserved[4]; |
|
- | 3237 | }ATOM_LCD_INFO_V13; |
|
- | 3238 | ||
- | 3239 | #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 |
|
- | 3240 | ||
- | 3241 | //Definitions for ucLCD_Misc |
|
- | 3242 | #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 |
|
- | 3243 | #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 |
|
- | 3244 | #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C |
|
- | 3245 | #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 |
|
- | 3246 | #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 |
|
- | 3247 | #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 |
|
- | 3248 | #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 |
|
- | 3249 | ||
- | 3250 | //Color Bit Depth definition in EDID V1.4 @BYTE 14h |
|
- | 3251 | //Bit 6 5 4 |
|
- | 3252 | // 0 0 0 - Color bit depth is undefined |
|
- | 3253 | // 0 0 1 - 6 Bits per Primary Color |
|
- | 3254 | // 0 1 0 - 8 Bits per Primary Color |
|
- | 3255 | // 0 1 1 - 10 Bits per Primary Color |
|
- | 3256 | // 1 0 0 - 12 Bits per Primary Color |
|
- | 3257 | // 1 0 1 - 14 Bits per Primary Color |
|
- | 3258 | // 1 1 0 - 16 Bits per Primary Color |
|
- | 3259 | // 1 1 1 - Reserved |
|
Line -... | Line 3260... | ||
- | 3260 | ||
- | 3261 | //Definitions for ucLCDPanel_SpecialHandlingCap: |
|
- | 3262 | ||
- | 3263 | //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. |
|
- | 3264 | //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL |
|
- | 3265 | #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version |
|
2779 | #define PANEL_RANDOM_DITHER_MASK 0x80 |
3266 | |
- | 3267 | //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together |
|
- | 3268 | //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static |
|
- | 3269 | //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 |
|
- | 3270 | #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version |
|
Line 2780... | Line 3271... | ||
2780 | 3271 | ||
2781 | 3272 | //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. |
|
2782 | #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 |
3273 | #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version |
2783 | 3274 | ||
Line 2866... | Line 3357... | ||
2866 | }ATOM_SPREAD_SPECTRUM_INFO; |
3357 | }ATOM_SPREAD_SPECTRUM_INFO; |
Line 2867... | Line 3358... | ||
2867 | 3358 | ||
2868 | /****************************************************************************/ |
3359 | /****************************************************************************/ |
2869 | // Structure used in AnalogTV_InfoTable (Top level) |
3360 | // Structure used in AnalogTV_InfoTable (Top level) |
2870 | /****************************************************************************/ |
3361 | /****************************************************************************/ |
Line 2871... | Line 3362... | ||
2871 | //ucTVBootUpDefaultStd definiton: |
3362 | //ucTVBootUpDefaultStd definition: |
2872 | 3363 | ||
2873 | //ATOM_TV_NTSC 1 |
3364 | //ATOM_TV_NTSC 1 |
2874 | //ATOM_TV_NTSCJ 2 |
3365 | //ATOM_TV_NTSCJ 2 |
Line 2910... | Line 3401... | ||
2910 | ATOM_COMMON_TABLE_HEADER sHeader; |
3401 | ATOM_COMMON_TABLE_HEADER sHeader; |
2911 | UCHAR ucTV_SupportedStandard; |
3402 | UCHAR ucTV_SupportedStandard; |
2912 | UCHAR ucTV_BootUpDefaultStandard; |
3403 | UCHAR ucTV_BootUpDefaultStandard; |
2913 | UCHAR ucExt_TV_ASIC_ID; |
3404 | UCHAR ucExt_TV_ASIC_ID; |
2914 | UCHAR ucExt_TV_ASIC_SlaveAddr; |
3405 | UCHAR ucExt_TV_ASIC_SlaveAddr; |
2915 | ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; |
3406 | ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; |
2916 | }ATOM_ANALOG_TV_INFO_V1_2; |
3407 | }ATOM_ANALOG_TV_INFO_V1_2; |
Line 2917... | Line 3408... | ||
2917 | 3408 | ||
2918 | typedef struct _ATOM_DPCD_INFO |
3409 | typedef struct _ATOM_DPCD_INFO |
2919 | { |
3410 | { |
Line 2942... | Line 3433... | ||
2942 | #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes |
3433 | #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes |
2943 | #define ATOM_HWICON_INFOTABLE_SIZE 32 |
3434 | #define ATOM_HWICON_INFOTABLE_SIZE 32 |
2944 | #define MAX_DTD_MODE_IN_VRAM 6 |
3435 | #define MAX_DTD_MODE_IN_VRAM 6 |
2945 | #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) |
3436 | #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) |
2946 | #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) |
3437 | #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) |
2947 | #define DFP_ENCODER_TYPE_OFFSET 0x80 |
3438 | //20 bytes for Encoder Type and DPCD in STD EDID area |
2948 | #define DP_ENCODER_LANE_NUM_OFFSET 0x84 |
3439 | #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) |
2949 | #define DP_ENCODER_LINK_RATE_OFFSET 0x88 |
3440 | #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) |
Line 2950... | Line 3441... | ||
2950 | 3441 | ||
2951 | #define ATOM_HWICON1_SURFACE_ADDR 0 |
3442 | #define ATOM_HWICON1_SURFACE_ADDR 0 |
2952 | #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
3443 | #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
2953 | #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
3444 | #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
Line 2997... | Line 3488... | ||
2997 | #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3488 | #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
2998 | #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3489 | #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
Line 2999... | Line 3490... | ||
2999 | 3490 | ||
Line 3000... | Line 3491... | ||
3000 | #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3491 | #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3001 | 3492 | ||
Line 3002... | Line 3493... | ||
3002 | #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) |
3493 | #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) |
3003 | #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 |
3494 | #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 |
Line -... | Line 3495... | ||
- | 3495 | ||
- | 3496 | //The size below is in Kb! |
|
3004 | 3497 | #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) |
|
3005 | //The size below is in Kb! |
3498 | |
3006 | #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) |
3499 | #define ATOM_VRAM_RESERVE_V2_SIZE 32 |
3007 | 3500 | ||
Line 3204... | Line 3697... | ||
3204 | USHORT usConnObjectId; //Connector Object ID |
3697 | USHORT usConnObjectId; //Connector Object ID |
3205 | USHORT usGPUObjectId; //GPU ID |
3698 | USHORT usGPUObjectId; //GPU ID |
3206 | USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. |
3699 | USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. |
3207 | }ATOM_DISPLAY_OBJECT_PATH; |
3700 | }ATOM_DISPLAY_OBJECT_PATH; |
Line -... | Line 3701... | ||
- | 3701 | ||
- | 3702 | typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH |
|
- | 3703 | { |
|
- | 3704 | USHORT usDeviceTag; //supported device |
|
- | 3705 | USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH |
|
- | 3706 | USHORT usConnObjectId; //Connector Object ID |
|
- | 3707 | USHORT usGPUObjectId; //GPU ID |
|
- | 3708 | USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder |
|
- | 3709 | }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; |
|
3208 | 3710 | ||
3209 | typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE |
3711 | typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE |
3210 | { |
3712 | { |
3211 | UCHAR ucNumOfDispPath; |
3713 | UCHAR ucNumOfDispPath; |
3212 | UCHAR ucVersion; |
3714 | UCHAR ucVersion; |
Line 3259... | Line 3761... | ||
3259 | #define EXT_AUXDDC_LUTINDEX_5 5 |
3761 | #define EXT_AUXDDC_LUTINDEX_5 5 |
3260 | #define EXT_AUXDDC_LUTINDEX_6 6 |
3762 | #define EXT_AUXDDC_LUTINDEX_6 6 |
3261 | #define EXT_AUXDDC_LUTINDEX_7 7 |
3763 | #define EXT_AUXDDC_LUTINDEX_7 7 |
3262 | #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) |
3764 | #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) |
Line -... | Line 3765... | ||
- | 3765 | ||
- | 3766 | //ucChannelMapping are defined as following |
|
- | 3767 | //for DP connector, eDP, DP to VGA/LVDS |
|
- | 3768 | //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
|
- | 3769 | //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
|
- | 3770 | //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
|
- | 3771 | //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
|
- | 3772 | typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING |
|
- | 3773 | { |
|
- | 3774 | #if ATOM_BIG_ENDIAN |
|
- | 3775 | UCHAR ucDP_Lane3_Source:2; |
|
- | 3776 | UCHAR ucDP_Lane2_Source:2; |
|
- | 3777 | UCHAR ucDP_Lane1_Source:2; |
|
- | 3778 | UCHAR ucDP_Lane0_Source:2; |
|
- | 3779 | #else |
|
- | 3780 | UCHAR ucDP_Lane0_Source:2; |
|
- | 3781 | UCHAR ucDP_Lane1_Source:2; |
|
- | 3782 | UCHAR ucDP_Lane2_Source:2; |
|
- | 3783 | UCHAR ucDP_Lane3_Source:2; |
|
- | 3784 | #endif |
|
- | 3785 | }ATOM_DP_CONN_CHANNEL_MAPPING; |
|
- | 3786 | ||
- | 3787 | //for DVI/HDMI, in dual link case, both links have to have same mapping. |
|
- | 3788 | //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
|
- | 3789 | //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
|
- | 3790 | //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
|
- | 3791 | //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
|
- | 3792 | typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING |
|
- | 3793 | { |
|
- | 3794 | #if ATOM_BIG_ENDIAN |
|
- | 3795 | UCHAR ucDVI_CLK_Source:2; |
|
- | 3796 | UCHAR ucDVI_DATA0_Source:2; |
|
- | 3797 | UCHAR ucDVI_DATA1_Source:2; |
|
- | 3798 | UCHAR ucDVI_DATA2_Source:2; |
|
- | 3799 | #else |
|
- | 3800 | UCHAR ucDVI_DATA2_Source:2; |
|
- | 3801 | UCHAR ucDVI_DATA1_Source:2; |
|
- | 3802 | UCHAR ucDVI_DATA0_Source:2; |
|
- | 3803 | UCHAR ucDVI_CLK_Source:2; |
|
- | 3804 | #endif |
|
- | 3805 | }ATOM_DVI_CONN_CHANNEL_MAPPING; |
|
3263 | 3806 | ||
3264 | typedef struct _EXT_DISPLAY_PATH |
3807 | typedef struct _EXT_DISPLAY_PATH |
3265 | { |
3808 | { |
3266 | USHORT usDeviceTag; //A bit vector to show what devices are supported |
3809 | USHORT usDeviceTag; //A bit vector to show what devices are supported |
3267 | USHORT usDeviceACPIEnum; //16bit device ACPI id. |
3810 | USHORT usDeviceACPIEnum; //16bit device ACPI id. |
3268 | USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions |
3811 | USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions |
3269 | UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT |
3812 | UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT |
3270 | UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT |
3813 | UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT |
- | 3814 | USHORT usExtEncoderObjId; //external encoder object id |
|
- | 3815 | union{ |
|
- | 3816 | UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping |
|
- | 3817 | ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; |
|
- | 3818 | ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; |
|
- | 3819 | }; |
|
3271 | USHORT usExtEncoderObjId; //external encoder object id |
3820 | UCHAR ucReserved; |
3272 | USHORT usReserved[3]; |
3821 | USHORT usReserved[2]; |
Line 3273... | Line 3822... | ||
3273 | }EXT_DISPLAY_PATH; |
3822 | }EXT_DISPLAY_PATH; |
3274 | 3823 | ||
Line 3279... | Line 3828... | ||
3279 | { |
3828 | { |
3280 | ATOM_COMMON_TABLE_HEADER sHeader; |
3829 | ATOM_COMMON_TABLE_HEADER sHeader; |
3281 | UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string |
3830 | UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string |
3282 | EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. |
3831 | EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. |
3283 | UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. |
3832 | UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. |
- | 3833 | UCHAR uc3DStereoPinId; // use for eDP panel |
|
3284 | UCHAR Reserved [7]; // for potential expansion |
3834 | UCHAR Reserved [6]; // for potential expansion |
3285 | }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; |
3835 | }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; |
Line 3286... | Line 3836... | ||
3286 | 3836 | ||
3287 | //Related definitions, all records are differnt but they have a commond header |
3837 | //Related definitions, all records are different but they have a commond header |
3288 | typedef struct _ATOM_COMMON_RECORD_HEADER |
3838 | typedef struct _ATOM_COMMON_RECORD_HEADER |
3289 | { |
3839 | { |
3290 | UCHAR ucRecordType; //An emun to indicate the record type |
3840 | UCHAR ucRecordType; //An emun to indicate the record type |
3291 | UCHAR ucRecordSize; //The size of the whole record in byte |
3841 | UCHAR ucRecordSize; //The size of the whole record in byte |
Line 3309... | Line 3859... | ||
3309 | #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 |
3859 | #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 |
3310 | #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table |
3860 | #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table |
3311 | #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table |
3861 | #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table |
3312 | #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record |
3862 | #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record |
3313 | #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 |
3863 | #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 |
- | 3864 | #define ATOM_ENCODER_CAP_RECORD_TYPE 20 |
|
Line 3314... | Line 3865... | ||
3314 | 3865 | ||
3315 | 3866 | ||
Line 3316... | Line 3867... | ||
3316 | //Must be updated when new record type is added,equal to that record definition! |
3867 | //Must be updated when new record type is added,equal to that record definition! |
3317 | #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE |
3868 | #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE |
3318 | 3869 | ||
3319 | typedef struct _ATOM_I2C_RECORD |
3870 | typedef struct _ATOM_I2C_RECORD |
Line 3439... | Line 3990... | ||
3439 | ATOM_COMMON_RECORD_HEADER sheader; |
3990 | ATOM_COMMON_RECORD_HEADER sheader; |
3440 | ULONG ulStrengthControl; // DVOA strength control for CF |
3991 | ULONG ulStrengthControl; // DVOA strength control for CF |
3441 | UCHAR ucPadding[2]; |
3992 | UCHAR ucPadding[2]; |
3442 | }ATOM_ENCODER_DVO_CF_RECORD; |
3993 | }ATOM_ENCODER_DVO_CF_RECORD; |
Line -... | Line 3994... | ||
- | 3994 | ||
- | 3995 | // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap |
|
- | 3996 | #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by this path |
|
- | 3997 | ||
- | 3998 | typedef struct _ATOM_ENCODER_CAP_RECORD |
|
- | 3999 | { |
|
- | 4000 | ATOM_COMMON_RECORD_HEADER sheader; |
|
- | 4001 | union { |
|
- | 4002 | USHORT usEncoderCap; |
|
- | 4003 | struct { |
|
- | 4004 | #if ATOM_BIG_ENDIAN |
|
- | 4005 | USHORT usReserved:15; // Bit1-15 may be defined for other capability in future |
|
- | 4006 | USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. |
|
- | 4007 | #else |
|
- | 4008 | USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. |
|
- | 4009 | USHORT usReserved:15; // Bit1-15 may be defined for other capability in future |
|
- | 4010 | #endif |
|
- | 4011 | }; |
|
- | 4012 | }; |
|
- | 4013 | }ATOM_ENCODER_CAP_RECORD; |
|
3443 | 4014 | ||
3444 | // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle |
4015 | // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle |
3445 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 |
4016 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 |
Line 3446... | Line 4017... | ||
3446 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 |
4017 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 |
Line 3578... | Line 4149... | ||
3578 | #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 |
4149 | #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 |
3579 | #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage |
4150 | #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage |
3580 | #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI |
4151 | #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI |
3581 | #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage |
4152 | #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage |
3582 | #define VOLTAGE_CONTROL_ID_DS4402 0x04 |
4153 | #define VOLTAGE_CONTROL_ID_DS4402 0x04 |
- | 4154 | #define VOLTAGE_CONTROL_ID_UP6266 0x05 |
|
- | 4155 | #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 |
|
- | 4156 | #define VOLTAGE_CONTROL_ID_VT1556M 0x07 |
|
- | 4157 | #define VOLTAGE_CONTROL_ID_CHL822x 0x08 |
|
- | 4158 | #define VOLTAGE_CONTROL_ID_VT1586M 0x09 |
|
Line 3583... | Line 4159... | ||
3583 | 4159 | ||
3584 | typedef struct _ATOM_VOLTAGE_OBJECT |
4160 | typedef struct _ATOM_VOLTAGE_OBJECT |
3585 | { |
4161 | { |
3586 | UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI |
4162 | UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI |
Line 3668... | Line 4244... | ||
3668 | //define ucPwrSensorId |
4244 | //define ucPwrSensorId |
3669 | #define POWER_SENSOR_ALWAYS 0x00 |
4245 | #define POWER_SENSOR_ALWAYS 0x00 |
3670 | #define POWER_SENSOR_GPIO 0x01 |
4246 | #define POWER_SENSOR_GPIO 0x01 |
3671 | #define POWER_SENSOR_I2C 0x02 |
4247 | #define POWER_SENSOR_I2C 0x02 |
Line -... | Line 4248... | ||
- | 4248 | ||
- | 4249 | typedef struct _ATOM_CLK_VOLT_CAPABILITY |
|
- | 4250 | { |
|
- | 4251 | ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table |
|
- | 4252 | ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz |
|
- | 4253 | }ATOM_CLK_VOLT_CAPABILITY; |
|
- | 4254 | ||
- | 4255 | typedef struct _ATOM_AVAILABLE_SCLK_LIST |
|
- | 4256 | { |
|
- | 4257 | ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz |
|
- | 4258 | USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK |
|
- | 4259 | USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK |
|
- | 4260 | }ATOM_AVAILABLE_SCLK_LIST; |
|
- | 4261 | ||
- | 4262 | // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition |
|
- | 4263 | #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] |
|
- | 4264 | ||
3672 | 4265 | // this IntegrateSystemInfoTable is used for Liano/Ontario APU |
|
3673 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 |
4266 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 |
3674 | { |
4267 | { |
3675 | ATOM_COMMON_TABLE_HEADER sHeader; |
4268 | ATOM_COMMON_TABLE_HEADER sHeader; |
3676 | ULONG ulBootUpEngineClock; |
4269 | ULONG ulBootUpEngineClock; |
3677 | ULONG ulDentistVCOFreq; |
4270 | ULONG ulDentistVCOFreq; |
3678 | ULONG ulBootUpUMAClock; |
4271 | ULONG ulBootUpUMAClock; |
3679 | ULONG ulReserved1[8]; |
4272 | ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; |
3680 | ULONG ulBootUpReqDisplayVector; |
4273 | ULONG ulBootUpReqDisplayVector; |
3681 | ULONG ulOtherDisplayMisc; |
4274 | ULONG ulOtherDisplayMisc; |
- | 4275 | ULONG ulGPUCapInfo; |
|
- | 4276 | ULONG ulSB_MMIO_Base_Addr; |
|
- | 4277 | USHORT usRequestedPWMFreqInHz; |
|
- | 4278 | UCHAR ucHtcTmpLmt; |
|
3682 | ULONG ulGPUCapInfo; |
4279 | UCHAR ucHtcHystLmt; |
3683 | ULONG ulReserved2[3]; |
4280 | ULONG ulMinEngineClock; |
3684 | ULONG ulSystemConfig; |
4281 | ULONG ulSystemConfig; |
3685 | ULONG ulCPUCapInfo; |
4282 | ULONG ulCPUCapInfo; |
3686 | USHORT usMaxNBVoltage; |
4283 | USHORT usNBP0Voltage; |
3687 | USHORT usMinNBVoltage; |
4284 | USHORT usNBP1Voltage; |
3688 | USHORT usBootUpNBVoltage; |
4285 | USHORT usBootUpNBVoltage; |
3689 | USHORT usExtDispConnInfoOffset; |
- | |
3690 | UCHAR ucHtcTmpLmt; |
4286 | USHORT usExtDispConnInfoOffset; |
3691 | UCHAR ucTjOffset; |
4287 | USHORT usPanelRefreshRateRange; |
3692 | UCHAR ucMemoryType; |
4288 | UCHAR ucMemoryType; |
3693 | UCHAR ucUMAChannelNumber; |
4289 | UCHAR ucUMAChannelNumber; |
3694 | ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; |
4290 | ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; |
3695 | ULONG ulCSR_M3_ARB_CNTL_UVD[10]; |
4291 | ULONG ulCSR_M3_ARB_CNTL_UVD[10]; |
- | 4292 | ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; |
|
- | 4293 | ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; |
|
- | 4294 | ULONG ulGMCRestoreResetTime; |
|
- | 4295 | ULONG ulMinimumNClk; |
|
- | 4296 | ULONG ulIdleNClk; |
|
- | 4297 | ULONG ulDDR_DLL_PowerUpTime; |
|
- | 4298 | ULONG ulDDR_PLL_PowerUpTime; |
|
- | 4299 | USHORT usPCIEClkSSPercentage; |
|
- | 4300 | USHORT usPCIEClkSSType; |
|
- | 4301 | USHORT usLvdsSSPercentage; |
|
- | 4302 | USHORT usLvdsSSpreadRateIn10Hz; |
|
- | 4303 | USHORT usHDMISSPercentage; |
|
- | 4304 | USHORT usHDMISSpreadRateIn10Hz; |
|
- | 4305 | USHORT usDVISSPercentage; |
|
3696 | ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; |
4306 | USHORT usDVISSpreadRateIn10Hz; |
3697 | ULONG ulReserved3[42]; |
4307 | ULONG ulReserved3[21]; |
3698 | ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; |
4308 | ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; |
Line -... | Line 4309... | ||
- | 4309 | }ATOM_INTEGRATED_SYSTEM_INFO_V6; |
|
- | 4310 | ||
- | 4311 | // ulGPUCapInfo |
|
- | 4312 | #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 |
|
- | 4313 | #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 |
|
- | 4314 | ||
- | 4315 | // ulOtherDisplayMisc |
|
- | 4316 | #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 |
|
3699 | }ATOM_INTEGRATED_SYSTEM_INFO_V6; |
4317 | |
3700 | 4318 | ||
3701 | /********************************************************************************************************************** |
4319 | /********************************************************************************************************************** |
3702 | // ATOM_INTEGRATED_SYSTEM_INFO_V6 Description |
4320 | ATOM_INTEGRATED_SYSTEM_INFO_V6 Description |
3703 | //ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. |
4321 | ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock |
3704 | //ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. |
4322 | ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. |
- | 4323 | ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. |
|
3705 | //ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. |
4324 | sDISPCLK_Voltage: Report Display clock voltage requirement. |
3706 | //ulReserved1[8] Reserved by now, must be 0x0. |
4325 | |
3707 | //ulBootUpReqDisplayVector VBIOS boot up display IDs |
4326 | ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: |
3708 | // ATOM_DEVICE_CRT1_SUPPORT 0x0001 |
4327 | ATOM_DEVICE_CRT1_SUPPORT 0x0001 |
3709 | // ATOM_DEVICE_CRT2_SUPPORT 0x0010 |
4328 | ATOM_DEVICE_CRT2_SUPPORT 0x0010 |
3710 | // ATOM_DEVICE_DFP1_SUPPORT 0x0008 |
4329 | ATOM_DEVICE_DFP1_SUPPORT 0x0008 |
3711 | // ATOM_DEVICE_DFP6_SUPPORT 0x0040 |
4330 | ATOM_DEVICE_DFP6_SUPPORT 0x0040 |
3712 | // ATOM_DEVICE_DFP2_SUPPORT 0x0080 |
4331 | ATOM_DEVICE_DFP2_SUPPORT 0x0080 |
3713 | // ATOM_DEVICE_DFP3_SUPPORT 0x0200 |
4332 | ATOM_DEVICE_DFP3_SUPPORT 0x0200 |
3714 | // ATOM_DEVICE_DFP4_SUPPORT 0x0400 |
4333 | ATOM_DEVICE_DFP4_SUPPORT 0x0400 |
3715 | // ATOM_DEVICE_DFP5_SUPPORT 0x0800 |
4334 | ATOM_DEVICE_DFP5_SUPPORT 0x0800 |
- | 4335 | ATOM_DEVICE_LCD1_SUPPORT 0x0002 |
|
- | 4336 | ulOtherDisplayMisc: Other display related flags, not defined yet. |
|
- | 4337 | ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. |
|
- | 4338 | =1: TMDS/HDMI Coherent Mode use signel PLL mode. |
|
- | 4339 | bit[3]=0: Enable HW AUX mode detection logic |
|
- | 4340 | =1: Disable HW AUX mode dettion logic |
|
- | 4341 | ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. |
|
- | 4342 | ||
- | 4343 | usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). |
|
- | 4344 | Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; |
|
- | 4345 | ||
- | 4346 | When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: |
|
- | 4347 | 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; |
|
- | 4348 | VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, |
|
- | 4349 | Changing BL using VBIOS function is functional in both driver and non-driver present environment; |
|
- | 4350 | and enabling VariBri under the driver environment from PP table is optional. |
|
- | 4351 | ||
- | 4352 | 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating |
|
- | 4353 | that BL control from GPU is expected. |
|
3716 | // ATOM_DEVICE_LCD1_SUPPORT 0x0002 |
4354 | VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 |
- | 4355 | Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but |
|
- | 4356 | it's per platform |
|
3717 | //ulOtherDisplayMisc Other display related flags, not defined yet. |
4357 | and enabling VariBri under the driver environment from PP table is optional. |
- | 4358 | ||
- | 4359 | ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. |
|
- | 4360 | Threshold on value to enter HTC_active state. |
|
- | 4361 | ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. |
|
3718 | //ulGPUCapInfo TBD |
4362 | To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. |
- | 4363 | ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. |
|
- | 4364 | ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled |
|
- | 4365 | =1: PCIE Power Gating Enabled |
|
- | 4366 | Bit[1]=0: DDR-DLL shut-down feature disabled. |
|
- | 4367 | 1: DDR-DLL shut-down feature enabled. |
|
3719 | //ulReserved2[3] must be 0x0 for the reserved. |
4368 | Bit[2]=0: DDR-PLL Power down feature disabled. |
- | 4369 | 1: DDR-PLL Power down feature enabled. |
|
- | 4370 | ulCPUCapInfo: TBD |
|
3720 | //ulSystemConfig TBD |
4371 | usNBP0Voltage: VID for voltage on NB P0 State |
- | 4372 | usNBP1Voltage: VID for voltage on NB P1 State |
|
3721 | //ulCPUCapInfo TBD |
4373 | usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. |
3722 | //usMaxNBVoltage High NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. |
4374 | usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure |
- | 4375 | usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set |
|
- | 4376 | to indicate a range. |
|
3723 | //usMinNBVoltage Low NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. |
4377 | SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 |
3724 | //usBootUpNBVoltage Boot up NB voltage in unit of mv. |
4378 | SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 |
3725 | //ucHtcTmpLmt Bit [22:16] of D24F3x64 Thermal Control (HTC) Register. |
4379 | SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 |
3726 | //ucTjOffset Bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed. |
4380 | SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 |
3727 | //ucMemoryType [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. |
- | |
3728 | //ucUMAChannelNumber System memory channel numbers. |
4381 | ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. |
3729 | //usExtDispConnectionInfoOffset ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO offset relative to beginning of this table. |
4382 | ucUMAChannelNumber: System memory channel numbers. |
3730 | //ulCSR_M3_ARB_CNTL_DEFAULT[10] Arrays with values for CSR M3 arbiter for default |
4383 | ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default |
- | 4384 | ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. |
|
- | 4385 | ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. |
|
- | 4386 | sAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high |
|
- | 4387 | ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. |
|
- | 4388 | ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. |
|
- | 4389 | ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. |
|
- | 4390 | ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. |
|
- | 4391 | ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. |
|
- | 4392 | usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. |
|
- | 4393 | usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. |
|
- | 4394 | usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. |
|
- | 4395 | usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
|
- | 4396 | usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. |
|
- | 4397 | usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
|
3731 | //ulCSR_M3_ARB_CNTL_UVD[10] Arrays with values for CSR M3 arbiter for UVD playback. |
4398 | usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. |
Line 3732... | Line 4399... | ||
3732 | //ulCSR_M3_ARB_CNTL_FS3D[10] Arrays with values for CSR M3 arbiter for Full Screen 3D applications. |
4399 | usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
3733 | **********************************************************************************************************************/ |
4400 | **********************************************************************************************************************/ |
3734 | 4401 | ||
Line 3778... | Line 4445... | ||
3778 | UCHAR ucClockIndication; //Indicate which clock source needs SS |
4445 | UCHAR ucClockIndication; //Indicate which clock source needs SS |
3779 | UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. |
4446 | UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. |
3780 | UCHAR ucReserved[2]; |
4447 | UCHAR ucReserved[2]; |
3781 | }ATOM_ASIC_SS_ASSIGNMENT; |
4448 | }ATOM_ASIC_SS_ASSIGNMENT; |
Line 3782... | Line 4449... | ||
3782 | 4449 | ||
3783 | //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. |
4450 | //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. |
3784 | //SS is not required or enabled if a match is not found. |
4451 | //SS is not required or enabled if a match is not found. |
3785 | #define ASIC_INTERNAL_MEMORY_SS 1 |
4452 | #define ASIC_INTERNAL_MEMORY_SS 1 |
3786 | #define ASIC_INTERNAL_ENGINE_SS 2 |
4453 | #define ASIC_INTERNAL_ENGINE_SS 2 |
3787 | #define ASIC_INTERNAL_UVD_SS 3 |
4454 | #define ASIC_INTERNAL_UVD_SS 3 |
3788 | #define ASIC_INTERNAL_SS_ON_TMDS 4 |
4455 | #define ASIC_INTERNAL_SS_ON_TMDS 4 |
3789 | #define ASIC_INTERNAL_SS_ON_HDMI 5 |
4456 | #define ASIC_INTERNAL_SS_ON_HDMI 5 |
3790 | #define ASIC_INTERNAL_SS_ON_LVDS 6 |
4457 | #define ASIC_INTERNAL_SS_ON_LVDS 6 |
3791 | #define ASIC_INTERNAL_SS_ON_DP 7 |
4458 | #define ASIC_INTERNAL_SS_ON_DP 7 |
- | 4459 | #define ASIC_INTERNAL_SS_ON_DCPLL 8 |
|
Line 3792... | Line 4460... | ||
3792 | #define ASIC_INTERNAL_SS_ON_DCPLL 8 |
4460 | #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 |
3793 | 4461 | ||
3794 | typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 |
4462 | typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 |
3795 | { |
4463 | { |
Line 3901... | Line 4569... | ||
3901 | #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 |
4569 | #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 |
Line 3902... | Line 4570... | ||
3902 | 4570 | ||
3903 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 |
4571 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 |
3904 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 |
4572 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 |
- | 4573 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 |
|
Line 3905... | Line 4574... | ||
3905 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 |
4574 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 |
3906 | 4575 | ||
3907 | //Byte aligned defintion for BIOS usage |
4576 | //Byte aligned definition for BIOS usage |
3908 | #define ATOM_S0_CRT1_MONOb0 0x01 |
4577 | #define ATOM_S0_CRT1_MONOb0 0x01 |
Line 3909... | Line 4578... | ||
3909 | #define ATOM_S0_CRT1_COLORb0 0x02 |
4578 | #define ATOM_S0_CRT1_COLORb0 0x02 |
Line 3968... | Line 4637... | ||
3968 | #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 |
4637 | #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 |
3969 | #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 |
4638 | #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 |
3970 | #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L |
4639 | #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L |
Line 3971... | Line 4640... | ||
3971 | 4640 | ||
3972 | 4641 | ||
3973 | //Byte aligned defintion for BIOS usage |
4642 | //Byte aligned definition for BIOS usage |
3974 | #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F |
4643 | #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F |
Line 3975... | Line 4644... | ||
3975 | #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF |
4644 | #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF |
Line 4018... | Line 4687... | ||
4018 | #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L |
4687 | #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L |
4019 | //Below two definitions are not supported in pplib, but in the old powerplay in DAL |
4688 | //Below two definitions are not supported in pplib, but in the old powerplay in DAL |
4020 | #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L |
4689 | #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L |
4021 | #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L |
4690 | #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L |
Line 4022... | Line 4691... | ||
4022 | 4691 | ||
4023 | //Byte aligned defintion for BIOS usage |
4692 | //Byte aligned definition for BIOS usage |
4024 | #define ATOM_S3_CRT1_ACTIVEb0 0x01 |
4693 | #define ATOM_S3_CRT1_ACTIVEb0 0x01 |
4025 | #define ATOM_S3_LCD1_ACTIVEb0 0x02 |
4694 | #define ATOM_S3_LCD1_ACTIVEb0 0x02 |
4026 | #define ATOM_S3_TV1_ACTIVEb0 0x04 |
4695 | #define ATOM_S3_TV1_ACTIVEb0 0x04 |
4027 | #define ATOM_S3_DFP1_ACTIVEb0 0x08 |
4696 | #define ATOM_S3_DFP1_ACTIVEb0 0x08 |
Line 4054... | Line 4723... | ||
4054 | // BIOS_4_SCRATCH Definition |
4723 | // BIOS_4_SCRATCH Definition |
4055 | #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL |
4724 | #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL |
4056 | #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L |
4725 | #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L |
4057 | #define ATOM_S4_LCD1_REFRESH_SHIFT 8 |
4726 | #define ATOM_S4_LCD1_REFRESH_SHIFT 8 |
Line 4058... | Line 4727... | ||
4058 | 4727 | ||
4059 | //Byte aligned defintion for BIOS usage |
4728 | //Byte aligned definition for BIOS usage |
4060 | #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF |
4729 | #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF |
4061 | #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
4730 | #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
Line 4062... | Line 4731... | ||
4062 | #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
4731 | #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
Line 4133... | Line 4802... | ||
4133 | #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L |
4802 | #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L |
4134 | #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L |
4803 | #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L |
4135 | #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L |
4804 | #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L |
4136 | #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L |
4805 | #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L |
Line 4137... | Line 4806... | ||
4137 | 4806 | ||
4138 | //Byte aligned defintion for BIOS usage |
4807 | //Byte aligned definition for BIOS usage |
4139 | #define ATOM_S6_DEVICE_CHANGEb0 0x01 |
4808 | #define ATOM_S6_DEVICE_CHANGEb0 0x01 |
4140 | #define ATOM_S6_SCALER_CHANGEb0 0x02 |
4809 | #define ATOM_S6_SCALER_CHANGEb0 0x02 |
4141 | #define ATOM_S6_LID_CHANGEb0 0x04 |
4810 | #define ATOM_S6_LID_CHANGEb0 0x04 |
4142 | #define ATOM_S6_DOCKING_CHANGEb0 0x08 |
4811 | #define ATOM_S6_DOCKING_CHANGEb0 0x08 |
Line 4374... | Line 5043... | ||
4374 | ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one |
5043 | ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one |
4375 | }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; |
5044 | }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; |
Line 4376... | Line 5045... | ||
4376 | 5045 | ||
4377 | typedef struct _MEMORY_CLEAN_UP_PARAMETERS |
5046 | typedef struct _MEMORY_CLEAN_UP_PARAMETERS |
4378 | { |
5047 | { |
4379 | USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address |
5048 | USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address |
4380 | USHORT usMemorySize; //8Kb blocks aligned |
5049 | USHORT usMemorySize; //8Kb blocks aligned |
4381 | }MEMORY_CLEAN_UP_PARAMETERS; |
5050 | }MEMORY_CLEAN_UP_PARAMETERS; |
Line 4382... | Line 5051... | ||
4382 | #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS |
5051 | #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS |
Line 4527... | Line 5196... | ||
4527 | #define VALUE_MASK_DWORD 0x84 |
5196 | #define VALUE_MASK_DWORD 0x84 |
Line 4528... | Line 5197... | ||
4528 | 5197 | ||
4529 | #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) |
5198 | #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) |
4530 | #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) |
5199 | #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) |
4531 | #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) |
- | |
- | 5200 | #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) |
|
- | 5201 | //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code |
|
Line 4532... | Line 5202... | ||
4532 | 5202 | #define ACCESS_PLACEHOLDER 0x80 |
|
4533 | 5203 | ||
4534 | typedef struct _ATOM_MC_INIT_PARAM_TABLE |
5204 | typedef struct _ATOM_MC_INIT_PARAM_TABLE |
4535 | { |
5205 | { |
Line 4552... | Line 5222... | ||
4552 | #define _16Mx32 0x23 |
5222 | #define _16Mx32 0x23 |
4553 | #define _32Mx16 0x32 |
5223 | #define _32Mx16 0x32 |
4554 | #define _32Mx32 0x33 |
5224 | #define _32Mx32 0x33 |
4555 | #define _64Mx8 0x41 |
5225 | #define _64Mx8 0x41 |
4556 | #define _64Mx16 0x42 |
5226 | #define _64Mx16 0x42 |
- | 5227 | #define _64Mx32 0x43 |
|
- | 5228 | #define _128Mx8 0x51 |
|
- | 5229 | #define _128Mx16 0x52 |
|
- | 5230 | #define _256Mx8 0x61 |
|
Line 4557... | Line 5231... | ||
4557 | 5231 | ||
4558 | #define SAMSUNG 0x1 |
5232 | #define SAMSUNG 0x1 |
4559 | #define INFINEON 0x2 |
5233 | #define INFINEON 0x2 |
4560 | #define ELPIDA 0x3 |
5234 | #define ELPIDA 0x3 |
Line 4567... | Line 5241... | ||
4567 | #define MICRON 0xF |
5241 | #define MICRON 0xF |
Line 4568... | Line 5242... | ||
4568 | 5242 | ||
4569 | #define QIMONDA INFINEON |
5243 | #define QIMONDA INFINEON |
4570 | #define PROMOS MOSEL |
5244 | #define PROMOS MOSEL |
- | 5245 | #define KRETON INFINEON |
|
Line 4571... | Line 5246... | ||
4571 | #define KRETON INFINEON |
5246 | #define ELIXIR NANYA |
Line 4572... | Line 5247... | ||
4572 | 5247 | ||
4573 | /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// |
5248 | /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// |
Line 4574... | Line 5249... | ||
4574 | 5249 | ||
Line 4575... | Line 5250... | ||
4575 | #define UCODE_ROM_START_ADDRESS 0x1c000 |
5250 | #define UCODE_ROM_START_ADDRESS 0x1b800 |
Line 4901... | Line 5576... | ||
4901 | UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth |
5576 | UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth |
4902 | UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth |
5577 | UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth |
4903 | ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock |
5578 | ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock |
4904 | }ATOM_VRAM_MODULE_V6; |
5579 | }ATOM_VRAM_MODULE_V6; |
Line -... | Line 5580... | ||
- | 5580 | ||
4905 | 5581 | typedef struct _ATOM_VRAM_MODULE_V7 |
|
- | 5582 | { |
|
- | 5583 | // Design Specific Values |
|
- | 5584 | ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP |
|
- | 5585 | USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 |
|
- | 5586 | USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) |
|
- | 5587 | USHORT usReserved; |
|
- | 5588 | UCHAR ucExtMemoryID; // Current memory module ID |
|
- | 5589 | UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 |
|
- | 5590 | UCHAR ucChannelNum; // Number of mem. channels supported in this module |
|
- | 5591 | UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT |
|
- | 5592 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
|
- | 5593 | UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. |
|
- | 5594 | UCHAR ucMisc; // RANK_OF_THISMEMORY etc. |
|
- | 5595 | UCHAR ucVREFI; // Not used. |
|
- | 5596 | UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. |
|
- | 5597 | UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble |
|
- | 5598 | UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros |
|
- | 5599 | UCHAR ucReserved[3]; |
|
- | 5600 | // Memory Module specific values |
|
- | 5601 | USHORT usEMRS2Value; // EMRS2/MR2 Value. |
|
- | 5602 | USHORT usEMRS3Value; // EMRS3/MR3 Value. |
|
- | 5603 | UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code |
|
- | 5604 | UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) |
|
- | 5605 | UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory |
|
- | 5606 | UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth |
|
- | 5607 | char strMemPNString[20]; // part number end with '0'. |
|
Line 4906... | Line 5608... | ||
4906 | 5608 | }ATOM_VRAM_MODULE_V7; |
|
4907 | 5609 | ||
4908 | typedef struct _ATOM_VRAM_INFO_V2 |
5610 | typedef struct _ATOM_VRAM_INFO_V2 |
4909 | { |
5611 | { |
Line 4940... | Line 5642... | ||
4940 | ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
5642 | ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
4941 | ATOM_INIT_REG_BLOCK asMemPatch; // for allocation |
5643 | ATOM_INIT_REG_BLOCK asMemPatch; // for allocation |
4942 | // ATOM_INIT_REG_BLOCK aMemAdjust; |
5644 | // ATOM_INIT_REG_BLOCK aMemAdjust; |
4943 | }ATOM_VRAM_INFO_V4; |
5645 | }ATOM_VRAM_INFO_V4; |
Line -... | Line 5646... | ||
- | 5646 | ||
- | 5647 | typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 |
|
- | 5648 | { |
|
- | 5649 | ATOM_COMMON_TABLE_HEADER sHeader; |
|
- | 5650 | USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting |
|
- | 5651 | USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting |
|
- | 5652 | USHORT usReserved[4]; |
|
- | 5653 | UCHAR ucNumOfVRAMModule; // indicate number of VRAM module |
|
- | 5654 | UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list |
|
- | 5655 | UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version |
|
- | 5656 | UCHAR ucReserved; |
|
- | 5657 | ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
|
- | 5658 | }ATOM_VRAM_INFO_HEADER_V2_1; |
|
- | 5659 | ||
4944 | 5660 | ||
4945 | typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO |
5661 | typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO |
4946 | { |
5662 | { |
4947 | ATOM_COMMON_TABLE_HEADER sHeader; |
5663 | ATOM_COMMON_TABLE_HEADER sHeader; |
4948 | UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator |
5664 | UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator |
Line 4997... | Line 5713... | ||
4997 | #define SW_I2C_CNTL_OPEN 4 |
5713 | #define SW_I2C_CNTL_OPEN 4 |
4998 | #define SW_I2C_CNTL_CLOSE 5 |
5714 | #define SW_I2C_CNTL_CLOSE 5 |
4999 | #define SW_I2C_CNTL_WRITE1BIT 6 |
5715 | #define SW_I2C_CNTL_WRITE1BIT 6 |
Line 5000... | Line 5716... | ||
5000 | 5716 | ||
5001 | //==============================VESA definition Portion=============================== |
5717 | //==============================VESA definition Portion=============================== |
5002 | #define VESA_OEM_PRODUCT_REV '01.00' |
5718 | #define VESA_OEM_PRODUCT_REV "01.00" |
5003 | #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support |
5719 | #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support |
5004 | #define VESA_MODE_WIN_ATTRIBUTE 7 |
5720 | #define VESA_MODE_WIN_ATTRIBUTE 7 |
Line 5005... | Line 5721... | ||
5005 | #define VESA_WIN_SIZE 64 |
5721 | #define VESA_WIN_SIZE 64 |
Line 5180... | Line 5896... | ||
5180 | UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) |
5896 | UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) |
5181 | UCHAR uc2ndEncoderID; |
5897 | UCHAR uc2ndEncoderID; |
5182 | UCHAR ucReserved; |
5898 | UCHAR ucReserved; |
5183 | }ASIC_TRANSMITTER_INFO; |
5899 | }ASIC_TRANSMITTER_INFO; |
Line -... | Line 5900... | ||
- | 5900 | ||
- | 5901 | #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 |
|
- | 5902 | #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 |
|
- | 5903 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 |
|
- | 5904 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 |
|
- | 5905 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 |
|
- | 5906 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 |
|
- | 5907 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 |
|
- | 5908 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 |
|
- | 5909 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 |
|
5184 | 5910 | ||
5185 | typedef struct _ASIC_ENCODER_INFO |
5911 | typedef struct _ASIC_ENCODER_INFO |
5186 | { |
5912 | { |
5187 | UCHAR ucEncoderID; |
5913 | UCHAR ucEncoderID; |
5188 | UCHAR ucEncoderConfig; |
5914 | UCHAR ucEncoderConfig; |
Line 5282... | Line 6008... | ||
5282 | #define ATOM_DP_CONFIG_LINK_A 0x00 |
6008 | #define ATOM_DP_CONFIG_LINK_A 0x00 |
5283 | #define ATOM_DP_CONFIG_LINK_B 0x04 |
6009 | #define ATOM_DP_CONFIG_LINK_B 0x04 |
5284 | /* /obselete */ |
6010 | /* /obselete */ |
5285 | #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
6011 | #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
Line -... | Line 6012... | ||
- | 6012 | ||
- | 6013 | ||
- | 6014 | typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 |
|
- | 6015 | { |
|
- | 6016 | USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION |
|
- | 6017 | UCHAR ucAuxId; |
|
- | 6018 | UCHAR ucAction; |
|
- | 6019 | UCHAR ucSinkType; // Iput and Output parameters. |
|
- | 6020 | UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION |
|
- | 6021 | UCHAR ucReserved[2]; |
|
- | 6022 | }DP_ENCODER_SERVICE_PARAMETERS_V2; |
|
- | 6023 | ||
- | 6024 | typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 |
|
- | 6025 | { |
|
- | 6026 | DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; |
|
- | 6027 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; |
|
- | 6028 | }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; |
|
- | 6029 | ||
- | 6030 | // ucAction |
|
- | 6031 | #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 |
|
- | 6032 | #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 |
|
- | 6033 | ||
5286 | 6034 | ||
5287 | // DP_TRAINING_TABLE |
6035 | // DP_TRAINING_TABLE |
5288 | #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR |
6036 | #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR |
5289 | #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) |
6037 | #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) |
5290 | #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) |
6038 | #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) |
Line 5337... | Line 6085... | ||
5337 | #define SELECT_DCIO_UNIPHY_LINK0 2 |
6085 | #define SELECT_DCIO_UNIPHY_LINK0 2 |
5338 | #define SELECT_DCIO_UNIPHY_LINK1 3 |
6086 | #define SELECT_DCIO_UNIPHY_LINK1 3 |
5339 | #define SELECT_DCIO_IMPCAL 4 |
6087 | #define SELECT_DCIO_IMPCAL 4 |
5340 | #define SELECT_DCIO_DIG 6 |
6088 | #define SELECT_DCIO_DIG 6 |
5341 | #define SELECT_CRTC_PIXEL_RATE 7 |
6089 | #define SELECT_CRTC_PIXEL_RATE 7 |
- | 6090 | #define SELECT_VGA_BLK 8 |
|
Line 5342... | Line 6091... | ||
5342 | 6091 | ||
5343 | /****************************************************************************/ |
6092 | /****************************************************************************/ |
5344 | //Portion VI: Definitinos for vbios MC scratch registers that driver used |
6093 | //Portion VI: Definitinos for vbios MC scratch registers that driver used |
Line 5740... | Line 6489... | ||
5740 | #define ATOM_PP_THERMALCONTROLLER_LM64 5 |
6489 | #define ATOM_PP_THERMALCONTROLLER_LM64 5 |
5741 | #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib |
6490 | #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib |
5742 | #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 |
6491 | #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 |
5743 | #define ATOM_PP_THERMALCONTROLLER_RV770 8 |
6492 | #define ATOM_PP_THERMALCONTROLLER_RV770 8 |
5744 | #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 |
6493 | #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 |
- | 6494 | #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 |
|
- | 6495 | #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 |
|
- | 6496 | #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. |
|
- | 6497 | #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally |
|
- | 6498 | #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 |
|
- | 6499 | ||
- | 6500 | // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. |
|
- | 6501 | // We probably should reserve the bit 0x80 for this use. |
|
- | 6502 | // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). |
|
- | 6503 | // The driver can pick the correct internal controller based on the ASIC. |
|
- | 6504 | ||
- | 6505 | #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller |
|
- | 6506 | #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller |
|
Line 5745... | Line 6507... | ||
5745 | 6507 | ||
5746 | typedef struct _ATOM_PPLIB_STATE |
6508 | typedef struct _ATOM_PPLIB_STATE |
5747 | { |
6509 | { |
5748 | UCHAR ucNonClockStateIndex; |
6510 | UCHAR ucNonClockStateIndex; |
5749 | UCHAR ucClockStateIndices[1]; // variable-sized |
6511 | UCHAR ucClockStateIndices[1]; // variable-sized |
Line -... | Line 6512... | ||
- | 6512 | } ATOM_PPLIB_STATE; |
|
- | 6513 | ||
- | 6514 | typedef struct _ATOM_PPLIB_FANTABLE |
|
- | 6515 | { |
|
- | 6516 | UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. |
|
- | 6517 | UCHAR ucTHyst; // Temperature hysteresis. Integer. |
|
- | 6518 | USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. |
|
- | 6519 | USHORT usTMed; // The middle temperature where we change slopes. |
|
- | 6520 | USHORT usTHigh; // The high point above TMed for adjusting the second slope. |
|
- | 6521 | USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). |
|
- | 6522 | USHORT usPWMMed; // The PWM value (in percent) at TMed. |
|
- | 6523 | USHORT usPWMHigh; // The PWM value at THigh. |
|
- | 6524 | } ATOM_PPLIB_FANTABLE; |
|
- | 6525 | ||
- | 6526 | typedef struct _ATOM_PPLIB_EXTENDEDHEADER |
|
- | 6527 | { |
|
- | 6528 | USHORT usSize; |
|
- | 6529 | ULONG ulMaxEngineClock; // For Overdrive. |
|
- | 6530 | ULONG ulMaxMemoryClock; // For Overdrive. |
|
- | 6531 | // Add extra system parameters here, always adjust size to include all fields. |
|
5750 | } ATOM_PPLIB_STATE; |
6532 | } ATOM_PPLIB_EXTENDEDHEADER; |
5751 | 6533 | ||
5752 | //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps |
6534 | //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps |
5753 | #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 |
6535 | #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 |
5754 | #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 |
6536 | #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 |
Line 5760... | Line 6542... | ||
5760 | #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 |
6542 | #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 |
5761 | #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 |
6543 | #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 |
5762 | #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 |
6544 | #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 |
5763 | #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 |
6545 | #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 |
5764 | #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 |
6546 | #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 |
- | 6547 | #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 |
|
- | 6548 | #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. |
|
- | 6549 | #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). |
|
- | 6550 | #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. |
|
- | 6551 | #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. |
|
- | 6552 | #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. |
|
Line 5765... | Line 6553... | ||
5765 | 6553 | ||
5766 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE |
6554 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE |
5767 | { |
6555 | { |
Line 5795... | Line 6583... | ||
5795 | USHORT usBootClockInfoOffset; |
6583 | USHORT usBootClockInfoOffset; |
5796 | USHORT usBootNonClockInfoOffset; |
6584 | USHORT usBootNonClockInfoOffset; |
Line 5797... | Line 6585... | ||
5797 | 6585 | ||
Line -... | Line 6586... | ||
- | 6586 | } ATOM_PPLIB_POWERPLAYTABLE; |
|
- | 6587 | ||
- | 6588 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 |
|
- | 6589 | { |
|
- | 6590 | ATOM_PPLIB_POWERPLAYTABLE basicTable; |
|
- | 6591 | UCHAR ucNumCustomThermalPolicy; |
|
- | 6592 | USHORT usCustomThermalPolicyArrayOffset; |
|
- | 6593 | }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; |
|
- | 6594 | ||
- | 6595 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 |
|
- | 6596 | { |
|
- | 6597 | ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; |
|
- | 6598 | USHORT usFormatID; // To be used ONLY by PPGen. |
|
- | 6599 | USHORT usFanTableOffset; |
|
- | 6600 | USHORT usExtendendedHeaderOffset; |
|
- | 6601 | } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; |
|
- | 6602 | ||
- | 6603 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 |
|
- | 6604 | { |
|
- | 6605 | ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; |
|
- | 6606 | ULONG ulGoldenPPID; // PPGen use only |
|
- | 6607 | ULONG ulGoldenRevision; // PPGen use only |
|
- | 6608 | USHORT usVddcDependencyOnSCLKOffset; |
|
- | 6609 | USHORT usVddciDependencyOnMCLKOffset; |
|
- | 6610 | USHORT usVddcDependencyOnMCLKOffset; |
|
- | 6611 | USHORT usMaxClockVoltageOnDCOffset; |
|
- | 6612 | USHORT usReserved[2]; |
|
- | 6613 | } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; |
|
- | 6614 | ||
- | 6615 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 |
|
- | 6616 | { |
|
- | 6617 | ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; |
|
- | 6618 | ULONG ulTDPLimit; |
|
- | 6619 | ULONG ulNearTDPLimit; |
|
- | 6620 | ULONG ulSQRampingThreshold; |
|
- | 6621 | USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table |
|
- | 6622 | ULONG ulCACLeakage; // TBD, this parameter is still under discussion. Change to ulReserved if not needed. |
|
- | 6623 | ULONG ulReserved; |
|
5798 | } ATOM_PPLIB_POWERPLAYTABLE; |
6624 | } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; |
5799 | 6625 | ||
5800 | //// ATOM_PPLIB_NONCLOCK_INFO::usClassification |
6626 | //// ATOM_PPLIB_NONCLOCK_INFO::usClassification |
5801 | #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 |
6627 | #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 |
5802 | #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 |
6628 | #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 |
Line 5814... | Line 6640... | ||
5814 | #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 |
6640 | #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 |
5815 | #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 |
6641 | #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 |
5816 | #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 |
6642 | #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 |
5817 | #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 |
6643 | #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 |
5818 | #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 |
6644 | #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 |
- | 6645 | #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 |
|
- | 6646 | #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 |
|
- | 6647 | #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 |
|
- | 6648 | ||
5819 | // remaining 3 bits are reserved |
6649 | //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 |
- | 6650 | #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 |
|
- | 6651 | #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 |
|
Line 5820... | Line 6652... | ||
5820 | 6652 | ||
5821 | //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings |
6653 | //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings |
5822 | #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 |
6654 | #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 |
Line 5838... | Line 6670... | ||
5838 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 |
6670 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 |
5839 | // 2-15 TBD as needed. |
6671 | // 2-15 TBD as needed. |
Line 5840... | Line 6672... | ||
5840 | 6672 | ||
5841 | #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 |
6673 | #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 |
- | 6674 | #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 |
|
5842 | #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 |
6675 | #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 |
Line -... | Line 6676... | ||
- | 6676 | #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 |
|
- | 6677 | ||
- | 6678 | //memory related flags |
|
- | 6679 | #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 |
|
- | 6680 | ||
- | 6681 | //M3 Arb //2bits, current 3 sets of parameters in total |
|
- | 6682 | #define ATOM_PPLIB_M3ARB_MASK 0x00060000 |
|
5843 | #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 |
6683 | #define ATOM_PPLIB_M3ARB_SHIFT 17 |
- | 6684 | ||
- | 6685 | #define ATOM_PPLIB_ENABLE_DRR 0x00080000 |
|
- | 6686 | ||
- | 6687 | // remaining 16 bits are reserved |
|
- | 6688 | typedef struct _ATOM_PPLIB_THERMAL_STATE |
|
- | 6689 | { |
|
- | 6690 | UCHAR ucMinTemperature; |
|
- | 6691 | UCHAR ucMaxTemperature; |
|
Line 5844... | Line 6692... | ||
5844 | 6692 | UCHAR ucThermalAction; |
|
5845 | #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 |
6693 | }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; |
5846 | 6694 | ||
- | 6695 | // Contained in an array starting at the offset |
|
- | 6696 | // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. |
|
5847 | // Contained in an array starting at the offset |
6697 | // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex |
5848 | // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. |
6698 | #define ATOM_PPLIB_NONCLOCKINFO_VER1 12 |
5849 | // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex |
6699 | #define ATOM_PPLIB_NONCLOCKINFO_VER2 24 |
5850 | typedef struct _ATOM_PPLIB_NONCLOCK_INFO |
6700 | typedef struct _ATOM_PPLIB_NONCLOCK_INFO |
5851 | { |
6701 | { |
5852 | USHORT usClassification; |
6702 | USHORT usClassification; |
5853 | UCHAR ucMinTemperature; |
6703 | UCHAR ucMinTemperature; |
- | 6704 | UCHAR ucMaxTemperature; |
|
- | 6705 | ULONG ulCapsAndSettings; |
|
- | 6706 | UCHAR ucRequiredPower; |
|
5854 | UCHAR ucMaxTemperature; |
6707 | USHORT usClassification2; |
5855 | ULONG ulCapsAndSettings; |
6708 | ULONG ulVCLK; |
Line 5856... | Line 6709... | ||
5856 | UCHAR ucRequiredPower; |
6709 | ULONG ulDCLK; |
5857 | UCHAR ucUnused1[3]; |
6710 | UCHAR ucUnused[5]; |
5858 | } ATOM_PPLIB_NONCLOCK_INFO; |
6711 | } ATOM_PPLIB_NONCLOCK_INFO; |
Line 5880... | Line 6733... | ||
5880 | #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 |
6733 | #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 |
5881 | #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 |
6734 | #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 |
5882 | #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 |
6735 | #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 |
5883 | #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 |
6736 | #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 |
5884 | #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 |
6737 | #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 |
- | 6738 | #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). |
|
- | 6739 | ||
- | 6740 | typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO |
|
- | 6741 | { |
|
- | 6742 | USHORT usEngineClockLow; |
|
- | 6743 | UCHAR ucEngineClockHigh; |
|
- | 6744 | ||
- | 6745 | USHORT usMemoryClockLow; |
|
- | 6746 | UCHAR ucMemoryClockHigh; |
|
- | 6747 | ||
- | 6748 | USHORT usVDDC; |
|
- | 6749 | USHORT usVDDCI; |
|
- | 6750 | USHORT usUnused; |
|
- | 6751 | ||
- | 6752 | ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* |
|
- | 6753 | ||
- | 6754 | } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; |
|
Line 5885... | Line 6755... | ||
5885 | 6755 | ||
Line 5886... | Line 6756... | ||
5886 | typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO |
6756 | typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO |
5887 | 6757 | ||
Line 5893... | Line 6763... | ||
5893 | USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. |
6763 | USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. |
5894 | UCHAR ucMemoryClockHigh; // Currentyl unused. |
6764 | UCHAR ucMemoryClockHigh; // Currentyl unused. |
5895 | UCHAR ucPadding; // For proper alignment and size. |
6765 | UCHAR ucPadding; // For proper alignment and size. |
5896 | USHORT usVDDC; // For the 780, use: None, Low, High, Variable |
6766 | USHORT usVDDC; // For the 780, use: None, Low, High, Variable |
5897 | UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} |
6767 | UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} |
5898 | UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement. |
6768 | UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requirement. |
5899 | USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). |
6769 | USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). |
5900 | ULONG ulFlags; |
6770 | ULONG ulFlags; |
5901 | } ATOM_PPLIB_RS780_CLOCK_INFO; |
6771 | } ATOM_PPLIB_RS780_CLOCK_INFO; |
Line 5902... | Line 6772... | ||
5902 | 6772 | ||
Line 5911... | Line 6781... | ||
5911 | 6781 | ||
5912 | #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 |
6782 | #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 |
5913 | #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 |
6783 | #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 |
Line -... | Line 6784... | ||
- | 6784 | #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 |
|
- | 6785 | ||
- | 6786 | typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ |
|
- | 6787 | USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz |
|
- | 6788 | UCHAR ucEngineClockHigh; //clockfrequency >> 16. |
|
- | 6789 | UCHAR vddcIndex; //2-bit vddc index; |
|
- | 6790 | UCHAR leakage; //please use 8-bit absolute value, not the 6-bit % value |
|
- | 6791 | //please initalize to 0 |
|
- | 6792 | UCHAR rsv; |
|
- | 6793 | //please initalize to 0 |
|
- | 6794 | USHORT rsv1; |
|
- | 6795 | //please initialize to 0s |
|
- | 6796 | ULONG rsv2[2]; |
|
- | 6797 | }ATOM_PPLIB_SUMO_CLOCK_INFO; |
|
- | 6798 | ||
- | 6799 | ||
- | 6800 | ||
- | 6801 | typedef struct _ATOM_PPLIB_STATE_V2 |
|
- | 6802 | { |
|
- | 6803 | //number of valid dpm levels in this state; Driver uses it to calculate the whole |
|
- | 6804 | //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) |
|
- | 6805 | UCHAR ucNumDPMLevels; |
|
- | 6806 | ||
- | 6807 | //a index to the array of nonClockInfos |
|
- | 6808 | UCHAR nonClockInfoIndex; |
|
- | 6809 | /** |
|
- | 6810 | * Driver will read the first ucNumDPMLevels in this array |
|
- | 6811 | */ |
|
- | 6812 | UCHAR clockInfoIndex[1]; |
|
- | 6813 | } ATOM_PPLIB_STATE_V2; |
|
- | 6814 | ||
- | 6815 | typedef struct StateArray{ |
|
- | 6816 | //how many states we have |
|
- | 6817 | UCHAR ucNumEntries; |
|
- | 6818 | ||
- | 6819 | ATOM_PPLIB_STATE_V2 states[1]; |
|
- | 6820 | }StateArray; |
|
- | 6821 | ||
- | 6822 | ||
- | 6823 | typedef struct ClockInfoArray{ |
|
- | 6824 | //how many clock levels we have |
|
- | 6825 | UCHAR ucNumEntries; |
|
- | 6826 | ||
- | 6827 | //sizeof(ATOM_PPLIB_SUMO_CLOCK_INFO) |
|
- | 6828 | UCHAR ucEntrySize; |
|
- | 6829 | ||
- | 6830 | //this is for Sumo |
|
- | 6831 | ATOM_PPLIB_SUMO_CLOCK_INFO clockInfo[1]; |
|
- | 6832 | }ClockInfoArray; |
|
- | 6833 | ||
- | 6834 | typedef struct NonClockInfoArray{ |
|
- | 6835 | ||
- | 6836 | //how many non-clock levels we have. normally should be same as number of states |
|
- | 6837 | UCHAR ucNumEntries; |
|
- | 6838 | //sizeof(ATOM_PPLIB_NONCLOCK_INFO) |
|
- | 6839 | UCHAR ucEntrySize; |
|
- | 6840 | ||
- | 6841 | ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; |
|
- | 6842 | }NonClockInfoArray; |
|
- | 6843 | ||
- | 6844 | typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record |
|
- | 6845 | { |
|
- | 6846 | USHORT usClockLow; |
|
- | 6847 | UCHAR ucClockHigh; |
|
- | 6848 | USHORT usVoltage; |
|
- | 6849 | }ATOM_PPLIB_Clock_Voltage_Dependency_Record; |
|
- | 6850 | ||
- | 6851 | typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table |
|
- | 6852 | { |
|
- | 6853 | UCHAR ucNumEntries; // Number of entries. |
|
- | 6854 | ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. |
|
- | 6855 | }ATOM_PPLIB_Clock_Voltage_Dependency_Table; |
|
- | 6856 | ||
- | 6857 | typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record |
|
- | 6858 | { |
|
- | 6859 | USHORT usSclkLow; |
|
- | 6860 | UCHAR ucSclkHigh; |
|
- | 6861 | USHORT usMclkLow; |
|
- | 6862 | UCHAR ucMclkHigh; |
|
- | 6863 | USHORT usVddc; |
|
- | 6864 | USHORT usVddci; |
|
- | 6865 | }ATOM_PPLIB_Clock_Voltage_Limit_Record; |
|
- | 6866 | ||
- | 6867 | typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table |
|
- | 6868 | { |
|
- | 6869 | UCHAR ucNumEntries; // Number of entries. |
|
- | 6870 | ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. |
|
5914 | #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 |
6871 | }ATOM_PPLIB_Clock_Voltage_Limit_Table; |
Line 5915... | Line 6872... | ||
5915 | 6872 | ||
5916 | /**************************************************************************/ |
6873 | /**************************************************************************/ |
5917 | 6874 | ||
5918 | 6875 | ||
5919 | // Following definitions are for compatiblity issue in different SW components. |
6876 | // Following definitions are for compatibility issue in different SW components. |
5920 | #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 |
6877 | #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 |