Subversion Repositories Kolibri OS

Rev

Rev 4280 | Rev 6084 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 4280 Rev 5354
Line 1... Line 1...
1
#include 
1
#include 
2
#include 
2
#include 
3
#include 
3
#include 
4
#include 
4
#include 
5
#include 
5
#include 
6
#include 
6
#include 
Line 7... Line 7...
7
 
7
 
Line 8... Line 8...
8
extern int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn);
8
extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);
Line 9... Line 9...
9
 
9
 
10
static LIST_HEAD(devices);
10
static LIST_HEAD(devices);
Line 29... Line 29...
29
    return IORESOURCE_MEM;
29
    return IORESOURCE_MEM;
30
}
30
}
Line 31... Line 31...
31
 
31
 
32
 
32
 
33
static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask)
33
static u32 pci_size(u32 base, u32 maxbase, u32 mask)
Line 34... Line 34...
34
{
34
{
35
    u32_t size = mask & maxbase;      /* Find the significant bits */
35
    u32 size = mask & maxbase;      /* Find the significant bits */
Line 36... Line 36...
36
 
36
 
Line 48... Line 48...
48
 
48
 
Line 49... Line 49...
49
    return size;
49
    return size;
50
}
50
}
Line 51... Line 51...
51
 
51
 
52
static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask)
52
static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
53
{
53
{
Line 54... Line 54...
54
    u64_t size = mask & maxbase;      /* Find the significant bits */
54
    u64 size = mask & maxbase;      /* Find the significant bits */
55
 
55
 
Line 56... Line 56...
56
    if (!size)
56
    if (!size)
Line 67... Line 67...
67
 
67
 
Line 68... Line 68...
68
    return size;
68
    return size;
69
}
69
}
Line 70... Line 70...
70
 
70
 
71
static inline int is_64bit_memory(u32_t mask)
71
static inline int is_64bit_memory(u32 mask)
72
{
72
{
73
    if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
73
    if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
74
        (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
74
        (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
75
        return 1;
75
        return 1;
76
    return 0;
76
    return 0;
Line 77... Line 77...
77
}
77
}
78
 
78
 
79
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
79
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
80
{
80
{
81
    u32_t  pos, reg, next;
81
    u32  pos, reg, next;
Line 82... Line 82...
82
    u32_t  l, sz;
82
    u32  l, sz;
83
    struct resource *res;
83
    struct resource *res;
84
 
84
 
85
    for(pos=0; pos < howmany; pos = next)
85
    for(pos=0; pos < howmany; pos = next)
86
    {
86
    {
Line 87... Line 87...
87
        u64_t  l64;
87
        u64  l64;
Line 88... Line 88...
88
        u64_t  sz64;
88
        u64  sz64;
Line 107... Line 107...
107
        raw_sz = sz;
107
        raw_sz = sz;
108
        if ((l & PCI_BASE_ADDRESS_SPACE) ==
108
        if ((l & PCI_BASE_ADDRESS_SPACE) ==
109
                        PCI_BASE_ADDRESS_SPACE_MEMORY)
109
                        PCI_BASE_ADDRESS_SPACE_MEMORY)
110
        {
110
        {
111
            sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK);
111
            sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
112
            /*
112
            /*
113
             * For 64bit prefetchable memory sz could be 0, if the
113
             * For 64bit prefetchable memory sz could be 0, if the
114
             * real size is bigger than 4G, so we need to check
114
             * real size is bigger than 4G, so we need to check
115
             * szhi for that.
115
             * szhi for that.
116
             */
116
             */
Line 129... Line 129...
129
        res->end = res->start + (unsigned long) sz;
129
        res->end = res->start + (unsigned long) sz;
130
        res->flags |= pci_calc_resource_flags(l);
130
        res->flags |= pci_calc_resource_flags(l);
131
        if (is_64bit_memory(l))
131
        if (is_64bit_memory(l))
132
        {
132
        {
133
            u32_t szhi, lhi;
133
            u32 szhi, lhi;
134
 
134
 
Line 135... Line 135...
135
            lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
135
            lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
136
            PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
136
            PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
137
            szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
137
            szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
138
            PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
138
            PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
139
            sz64 = ((u64_t)szhi << 32) | raw_sz;
139
            sz64 = ((u64)szhi << 32) | raw_sz;
140
            l64 = ((u64_t)lhi << 32) | l;
140
            l64 = ((u64)lhi << 32) | l;
141
            sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
141
            sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
142
            next++;
142
            next++;
Line 143... Line 143...
143
 
143
 
144
#if BITS_PER_LONG == 64
144
#if BITS_PER_LONG == 64
Line 160... Line 160...
160
            else if (lhi)
160
            else if (lhi)
161
            {
161
            {
162
                /* 64-bit wide address, treat as disabled */
162
                /* 64-bit wide address, treat as disabled */
163
                PciWrite32(dev->busnr, dev->devfn, reg,
163
                PciWrite32(dev->busnr, dev->devfn, reg,
164
                        l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK);
164
                        l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
165
                PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
165
                PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
166
                res->start = 0;
166
                res->start = 0;
167
                res->end = sz;
167
                res->end = sz;
168
            }
168
            }
169
#endif
169
#endif
170
        }
170
        }
Line 184... Line 184...
184
            l = 0;
184
            l = 0;
185
 
185
 
Line 186... Line 186...
186
        if (sz && sz != 0xffffffff)
186
        if (sz && sz != 0xffffffff)
187
        {
187
        {
188
            sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK);
188
            sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
Line 189... Line 189...
189
 
189
 
190
            if (sz)
190
            if (sz)
191
            {
191
            {
192
                res->flags = (l & IORESOURCE_ROM_ENABLE) |
192
                res->flags = (l & IORESOURCE_ROM_ENABLE) |
Line 200... Line 200...
200
}
200
}
201
 
201
 
Line 202... Line 202...
202
static void pci_read_irq(struct pci_dev *dev)
202
static void pci_read_irq(struct pci_dev *dev)
203
{
203
{
204
    u8_t irq;
204
    u8 irq;
Line 205... Line 205...
205
 
205
 
206
    irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
206
    irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
207
    dev->pin = irq;
207
    dev->pin = irq;
208
    if (irq)
208
    if (irq)
Line 212... Line 212...
212
 
212
 
Line 213... Line 213...
213
 
213
 
214
int pci_setup_device(struct pci_dev *dev)
214
int pci_setup_device(struct pci_dev *dev)
215
{
215
{
Line 216... Line 216...
216
    u32_t  class;
216
    u32  class;
217
 
217
 
218
    class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
218
    class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
219
    dev->revision = class & 0xff;
219
    dev->revision = class & 0xff;
Line 244... Line 244...
244
             *      BAR0-3 in a few cases contain junk!
244
             *      BAR0-3 in a few cases contain junk!
245
             */
245
             */
246
            if (class == PCI_CLASS_STORAGE_IDE)
246
            if (class == PCI_CLASS_STORAGE_IDE)
247
            {
247
            {
248
                u8_t progif;
248
                u8 progif;
249
 
249
 
Line 250... Line 250...
250
                progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
250
                progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
251
                if ((progif & 1) == 0)
251
                if ((progif & 1) == 0)
252
                {
252
                {
253
                    dev->resource[0].start = 0x1F0;
253
                    dev->resource[0].start = 0x1F0;
Line 309... Line 309...
309
 
309
 
Line 310... Line 310...
310
    return 0;
310
    return 0;
311
};
311
};
Line 312... Line 312...
312
 
312
 
313
static pci_dev_t* pci_scan_device(u32_t busnr, int devfn)
313
static pci_dev_t* pci_scan_device(u32 busnr, int devfn)
314
{
314
{
Line 315... Line 315...
315
    pci_dev_t  *dev;
315
    pci_dev_t  *dev;
316
 
316
 
Line 317... Line 317...
317
    u32_t   id;
317
    u32   id;
Line 318... Line 318...
318
    u8_t    hdr;
318
    u8    hdr;
Line 370... Line 370...
370
 
370
 
Line 371... Line 371...
371
 
371
 
372
 
372
 
373
 
373
 
Line 374... Line 374...
374
int pci_scan_slot(u32_t bus, int devfn)
374
int pci_scan_slot(u32 bus, int devfn)
375
{
375
{
Line 478... Line 478...
478
 
478
 
479
int enum_pci_devices()
479
int enum_pci_devices()
480
{
480
{
481
    pci_dev_t  *dev;
481
    pci_dev_t  *dev;
482
    u32_t       last_bus;
482
    u32       last_bus;
Line 483... Line 483...
483
    u32_t       bus = 0 , devfn = 0;
483
    u32       bus = 0 , devfn = 0;
Line 662... Line 662...
662
    IO_COND(addr, /* nothing */, iounmap(addr));
662
    IO_COND(addr, /* nothing */, iounmap(addr));
663
}
663
}
664
 
664
 
Line 665... Line -...
665
 
-
 
666
struct pci_bus_region {
-
 
667
    resource_size_t start;
-
 
668
    resource_size_t end;
-
 
669
};
-
 
670
 
665
 
671
static inline void
666
static inline void
672
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
667
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
673
                         struct resource *res)
668
                         struct resource *res)
674
{
669
{