WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/main.c


#include 
#include 
#include 
#include "i915_drv.h"
//#include "intel_drv.h"
 
#include 
#include 
#include 
#include 
#include 
#include 
 
#include "bitmap.h"
 
struct pci_device {
    uint16_t    domain;
    uint8_t     bus;
    uint8_t     dev;
    uint8_t     func;
    uint16_t    vendor_id;
    uint16_t    device_id;
    uint16_t    subvendor_id;
    uint16_t    subdevice_id;
    uint32_t    device_class;
    uint8_t     revision;
};
 
struct drm_device *main_device;
struct drm_file   *drm_file_handlers[256];
 
void cpu_detect();
 
void parse_cmdline(char *cmdline, char *log);
int _stdcall display_handler(ioctl_t *io);
int init_agp(void);
 
int srv_blit_bitmap(u32 hbitmap, int  dst_x, int dst_y,
               int src_x, int src_y, u32 w, u32 h);
 
int blit_textured(u32 hbitmap, int  dst_x, int dst_y,
               int src_x, int src_y, u32 w, u32 h);
 
int blit_tex(u32 hbitmap, int  dst_x, int dst_y,
             int src_x, int src_y, u32 w, u32 h);
 
void get_pci_info(struct pci_device *dev);
int gem_getparam(struct drm_device *dev, void *data);
 
int i915_mask_update(struct drm_device *dev, void *data,
            struct drm_file *file);
 
 
static char  log[256];
 
struct workqueue_struct *system_wq;
int driver_wq_state;
 
int x86_clflush_size;
unsigned int tsc_khz;
 
int i915_modeset = 1;
 
typedef union __attribute__((packed))
{
    uint32_t val;
    struct
    {
        uint8_t   state;
        uint8_t   code;
        uint16_t  ctrl_key;
    };
}oskey_t;
 
static inline oskey_t get_key(void)
{
    oskey_t val;
    asm volatile("int $0x40":"=a"(val):"a"(2));
    return val;
};
 
void i915_dpms(struct drm_device *dev, int mode);
 
void i915_driver_thread()
{
    struct drm_i915_private *dev_priv = main_device->dev_private;
    struct workqueue_struct *cwq = dev_priv->wq;
    static int dpms = 1;
    static int dpms_lock = 0;
    oskey_t   key;
    unsigned long irqflags;
    int tmp;
 
    printf("%s\n",__FUNCTION__);
 
    asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1));
    asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330));
    asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330));
 
    while(driver_wq_state != 0)
    {
        key = get_key();
 
        if( (key.val != 1) && (key.state == 0x02))
        {
            if(key.code == 0x46 && dpms_lock == 0)
            {
                dpms_lock = 1;
                if(dpms == 1)
                {
                    i915_dpms(main_device, DRM_MODE_DPMS_OFF);
                    printf("dpms off\n");
                }
                else
                {
                    i915_dpms(main_device, DRM_MODE_DPMS_ON);
                    printf("dpms on\n");
                };
                dpms ^= 1;
                }
            else if(key.code == 0xC6)
                dpms_lock = 0;
        };
 
        spin_lock_irqsave(&cwq->lock, irqflags);
 
        while (!list_empty(&cwq->worklist))
        {
            struct work_struct *work = list_entry(cwq->worklist.next,
                                        struct work_struct, entry);
            work_func_t f = work->func;
            list_del_init(cwq->worklist.next);
 
            spin_unlock_irqrestore(&cwq->lock, irqflags);
            f(work);
            spin_lock_irqsave(&cwq->lock, irqflags);
        }
 
        spin_unlock_irqrestore(&cwq->lock, irqflags);
 
        delay(1);
    };
 
    asm volatile ("int $0x40"::"a"(-1));
}
 
u32_t  __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
{
    int err = 0;
 
    if(action != 1)
    {
        driver_wq_state = 0;
        return 0;
    };
 
    if( GetService("DISPLAY") != 0 )
        return 0;
 
    if( cmdline && *cmdline )
        parse_cmdline(cmdline, log);
 
    if(!dbg_open(log))
    {
        strcpy(log, "/tmp1/1/i915.log");
 
 
 
        if(!dbg_open(log))
        {
            printf("Can't open %s\nExit\n", log);
            return 0;
        };
    }
    dbgprintf(" i915 v3.12-6\n cmdline: %s\n", cmdline);
 
    cpu_detect();
//    dbgprintf("\ncache line size %d\n", x86_clflush_size);
 
    enum_pci_devices();
 
    err = i915_init();
    if(err)
    {
        dbgprintf("Epic Fail :(\n");
        return 0;
    };
    init_display_kms(main_device);
 
    err = RegService("DISPLAY", display_handler);
 
    if( err != 0)
        dbgprintf("Set DISPLAY handler\n");
 
 
 
    driver_wq_state = 1;
 
    CreateKernelThread(i915_driver_thread);
 
    return err;
};
 
 
#define CURRENT_API     0x0200      /*      2.00     */
#define COMPATIBLE_API  0x0100      /*      1.00     */
 
#define API_VERSION     (COMPATIBLE_API << 16) | CURRENT_API
#define DISPLAY_VERSION  API_VERSION
 
 
#define SRV_GETVERSION          0
#define SRV_ENUM_MODES          1
#define SRV_SET_MODE            2
#define SRV_GET_CAPS            3
 
#define SRV_CREATE_SURFACE      10
#define SRV_DESTROY_SURFACE     11
#define SRV_LOCK_SURFACE        12
#define SRV_UNLOCK_SURFACE      13
#define SRV_RESIZE_SURFACE      14
#define SRV_BLIT_BITMAP         15
#define SRV_BLIT_TEXTURE        16
#define SRV_BLIT_VIDEO          17
 
 
#define SRV_GET_PCI_INFO            20
#define SRV_GET_PARAM               21
#define SRV_I915_GEM_CREATE         22
#define SRV_DRM_GEM_CLOSE           23
#define SRV_I915_GEM_PIN            24
#define SRV_I915_GEM_SET_CACHEING   25
#define SRV_I915_GEM_GET_APERTURE   26
#define SRV_I915_GEM_PWRITE         27
#define SRV_I915_GEM_BUSY           28
#define SRV_I915_GEM_SET_DOMAIN     29
#define SRV_I915_GEM_MMAP           30
#define SRV_I915_GEM_MMAP_GTT       31
#define SRV_I915_GEM_THROTTLE       32
#define SRV_FBINFO                  33
#define SRV_I915_GEM_EXECBUFFER2    34
#define SRV_MASK_UPDATE             35
 
 
 
#define check_input(size) \
    if( unlikely((inp==NULL)||(io->inp_size != (size))) )   \
        break;
 
#define check_output(size) \
    if( unlikely((outp==NULL)||(io->out_size != (size))) )   \
        break;
 
int _stdcall display_handler(ioctl_t *io)
{
    struct drm_file *file;
 
    int    retval = -1;
    u32_t *inp;
    u32_t *outp;
 
    inp = io->input;
    outp = io->output;
 
    file = drm_file_handlers[0];
 
    switch(io->io_code)
    {
        case SRV_GETVERSION:
            check_output(4);
            *outp  = DISPLAY_VERSION;
            retval = 0;
            break;
 
        case SRV_ENUM_MODES:
//            dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
//                       inp, io->inp_size, io->out_size );
            check_output(4);
//            check_input(*outp * sizeof(videomode_t));
            if( i915_modeset)
                retval = get_videomodes((videomode_t*)inp, outp);
            break;
 
        case SRV_SET_MODE:
//            dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
//                       inp, io->inp_size);
            check_input(sizeof(videomode_t));
            if( i915_modeset )
                retval = set_user_mode((videomode_t*)inp);
            break;
 
        case SRV_GET_CAPS:
            retval = get_driver_caps((hwcaps_t*)inp);
            break;
 
        case SRV_CREATE_SURFACE:
//            check_input(8);
//            retval = create_surface(main_device, (struct io_call_10*)inp);
            break;
 
        case SRV_LOCK_SURFACE:
//            retval = lock_surface((struct io_call_12*)inp);
            break;
 
        case SRV_RESIZE_SURFACE:
//            retval = resize_surface((struct io_call_14*)inp);
            break;
 
        case SRV_BLIT_BITMAP:
//            srv_blit_bitmap( inp[0], inp[1], inp[2],
//                        inp[3], inp[4], inp[5], inp[6]);
 
//            blit_tex( inp[0], inp[1], inp[2],
//                    inp[3], inp[4], inp[5], inp[6]);
 
            break;
 
        case SRV_GET_PCI_INFO:
            get_pci_info((struct pci_device *)inp);
            retval = 0;
            break;
 
        case SRV_GET_PARAM:
            retval = gem_getparam(main_device, inp);
            break;
 
        case SRV_I915_GEM_CREATE:
            retval = i915_gem_create_ioctl(main_device, inp, file);
            break;
 
        case SRV_DRM_GEM_CLOSE:
            retval = drm_gem_close_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_PIN:
            retval = i915_gem_pin_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_SET_CACHEING:
            retval = i915_gem_set_caching_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_GET_APERTURE:
            retval = i915_gem_get_aperture_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_PWRITE:
            retval = i915_gem_pwrite_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_BUSY:
            retval = i915_gem_busy_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_SET_DOMAIN:
            retval = i915_gem_set_domain_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_THROTTLE:
            retval = i915_gem_throttle_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_MMAP:
            retval = i915_gem_mmap_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_MMAP_GTT:
            retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);
            break;
 
 
        case SRV_FBINFO:
            retval = i915_fbinfo(inp);
            break;
 
        case SRV_I915_GEM_EXECBUFFER2:
            retval = i915_gem_execbuffer2(main_device, inp, file);
            break;
 
        case SRV_MASK_UPDATE:
            retval = i915_mask_update(main_device, inp, file);
            break;
 
    };
 
    return retval;
}
 
 
#define PCI_CLASS_REVISION      0x08
#define PCI_CLASS_DISPLAY_VGA   0x0300
#define PCI_CLASS_BRIDGE_HOST   0x0600
#define PCI_CLASS_BRIDGE_ISA    0x0601
 
int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)
{
    u16_t vendor, device;
    u32_t class;
    int   ret = 0;
 
    vendor   = id & 0xffff;
    device   = (id >> 16) & 0xffff;
 
    if(vendor == 0x8086)
    {
        class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
        class >>= 16;
 
        if( (class == PCI_CLASS_DISPLAY_VGA) ||
            (class == PCI_CLASS_BRIDGE_HOST) ||
            (class == PCI_CLASS_BRIDGE_ISA))
            ret = 1;
    }
    return ret;
};
 
 
static char* parse_path(char *p, char *log)
{
    char  c;
 
    while( (c = *p++) == ' ');
        p--;
    while( (c = *log++ = *p++) && (c != ' '));
    *log = 0;
 
    return p;
};
 
void parse_cmdline(char *cmdline, char *log)
{
    char *p = cmdline;
 
    char c = *p++;
 
    while( c )
    {
        if( c == '-')
        {
            switch(*p++)
            {
                case 'l':
                    p = parse_path(p, log);
                    break;
            };
        };
        c = *p++;
    };
};
 
 
static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
                unsigned int *ecx, unsigned int *edx)
{
    /* ecx is often an input as well as an output. */
    asm volatile("cpuid"
        : "=a" (*eax),
          "=b" (*ebx),
          "=c" (*ecx),
          "=d" (*edx)
        : "0" (*eax), "2" (*ecx)
        : "memory");
}
 
 
 
static inline void cpuid(unsigned int op,
                         unsigned int *eax, unsigned int *ebx,
                         unsigned int *ecx, unsigned int *edx)
{
        *eax = op;
        *ecx = 0;
        __cpuid(eax, ebx, ecx, edx);
}
 
void cpu_detect()
{
    u32 junk, tfms, cap0, misc;
 
    cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
 
    if (cap0 & (1<<19))
    {
        x86_clflush_size = ((misc >> 8) & 0xff) * 8;
    }
 
    tsc_khz = (unsigned int)(GetCpuFreq()/1000);
}
 
 
int get_driver_caps(hwcaps_t *caps)
{
    int ret = 0;
 
    switch(caps->idx)
    {
        case 0:
            caps->opt[0] = 0;
            caps->opt[1] = 0;
            break;
 
        case 1:
            caps->cap1.max_tex_width  = 4096;
            caps->cap1.max_tex_height = 4096;
            break;
        default:
            ret = 1;
    };
    caps->idx = 1;
    return ret;
}
 
 
void get_pci_info(struct pci_device *dev)
{
    struct pci_dev *pdev = main_device->pdev;
 
    memset(dev, sizeof(*dev), 0);
 
    dev->domain     = 0;
    dev->bus        = pdev->busnr;
    dev->dev        = pdev->devfn >> 3;
    dev->func       = pdev->devfn & 7;
    dev->vendor_id  = pdev->vendor;
    dev->device_id  = pdev->device;
    dev->revision   = pdev->revision;
};
>
>

Rev 4104	Rev 4126
1	#include	1	#include
2	#include	2	#include
3	#include	3	#include
4	#include "i915_drv.h"	4	#include "i915_drv.h"
5	//#include "intel_drv.h"	5	//#include "intel_drv.h"
6		6
7	#include	7	#include
8	#include	8	#include
9	#include	9	#include
10	#include	10	#include
11	#include	11	#include
12	#include	12	#include
13		13
14	#include "bitmap.h"	14	#include "bitmap.h"
15		15
16	struct pci_device {	16	struct pci_device {
17	uint16_t domain;	17	uint16_t domain;
18	uint8_t bus;	18	uint8_t bus;
19	uint8_t dev;	19	uint8_t dev;
20	uint8_t func;	20	uint8_t func;
21	uint16_t vendor_id;	21	uint16_t vendor_id;
22	uint16_t device_id;	22	uint16_t device_id;
23	uint16_t subvendor_id;	23	uint16_t subvendor_id;
24	uint16_t subdevice_id;	24	uint16_t subdevice_id;
25	uint32_t device_class;	25	uint32_t device_class;
26	uint8_t revision;	26	uint8_t revision;
27	};	27	};
28		28
29	struct drm_device *main_device;	29	struct drm_device *main_device;
30	struct drm_file *drm_file_handlers[256];	30	struct drm_file *drm_file_handlers[256];
31		31
32	void cpu_detect();	32	void cpu_detect();
33		33
34	void parse_cmdline(char cmdline, char log);	34	void parse_cmdline(char cmdline, char log);
35	int _stdcall display_handler(ioctl_t *io);	35	int _stdcall display_handler(ioctl_t *io);
36	int init_agp(void);	36	int init_agp(void);
37		37
38	int srv_blit_bitmap(u32 hbitmap, int dst_x, int dst_y,	38	int srv_blit_bitmap(u32 hbitmap, int dst_x, int dst_y,
39	int src_x, int src_y, u32 w, u32 h);	39	int src_x, int src_y, u32 w, u32 h);
40		40
41	int blit_textured(u32 hbitmap, int dst_x, int dst_y,	41	int blit_textured(u32 hbitmap, int dst_x, int dst_y,
42	int src_x, int src_y, u32 w, u32 h);	42	int src_x, int src_y, u32 w, u32 h);
43		43
44	int blit_tex(u32 hbitmap, int dst_x, int dst_y,	44	int blit_tex(u32 hbitmap, int dst_x, int dst_y,
45	int src_x, int src_y, u32 w, u32 h);	45	int src_x, int src_y, u32 w, u32 h);
46		46
47	void get_pci_info(struct pci_device *dev);	47	void get_pci_info(struct pci_device *dev);
48	int gem_getparam(struct drm_device dev, void data);	48	int gem_getparam(struct drm_device dev, void data);
49		49
50	int i915_mask_update(struct drm_device dev, void data,	50	int i915_mask_update(struct drm_device dev, void data,
51	struct drm_file *file);	51	struct drm_file *file);
52		52
53		53
54	static char log[256];	54	static char log[256];
55		55
56	struct workqueue_struct *system_wq;	56	struct workqueue_struct *system_wq;
57	int driver_wq_state;	57	int driver_wq_state;
58		58
59	int x86_clflush_size;	59	int x86_clflush_size;
60	unsigned int tsc_khz;	60	unsigned int tsc_khz;
61		61
62	int i915_modeset = 1;	62	int i915_modeset = 1;
-		63
-		64	typedef union __attribute__((packed))
-		65	{
-		66	uint32_t val;
-		67	struct
-		68	{
-		69	uint8_t state;
-		70	uint8_t code;
-		71	uint16_t ctrl_key;
-		72	};
-		73	}oskey_t;
-		74
-		75	static inline oskey_t get_key(void)
-		76	{
-		77	oskey_t val;
-		78	asm volatile("int $0x40":"=a"(val):"a"(2));
-		79	return val;
-		80	};
-		81
-		82	void i915_dpms(struct drm_device *dev, int mode);
-		83
-		84	void i915_driver_thread()
-		85	{
-		86	struct drm_i915_private *dev_priv = main_device->dev_private;
-		87	struct workqueue_struct *cwq = dev_priv->wq;
-		88	static int dpms = 1;
-		89	static int dpms_lock = 0;
-		90	oskey_t key;
-		91	unsigned long irqflags;
-		92	int tmp;
-		93
-		94	printf("%s\n",__FUNCTION__);
-		95
-		96	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1));
-		97	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330));
-		98	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330));
-		99
-		100	while(driver_wq_state != 0)
-		101	{
-		102	key = get_key();
-		103
-		104	if( (key.val != 1) && (key.state == 0x02))
-		105	{
-		106	if(key.code == 0x46 && dpms_lock == 0)
-		107	{
-		108	dpms_lock = 1;
-		109	if(dpms == 1)
-		110	{
-		111	i915_dpms(main_device, DRM_MODE_DPMS_OFF);
-		112	printf("dpms off\n");
-		113	}
-		114	else
-		115	{
-		116	i915_dpms(main_device, DRM_MODE_DPMS_ON);
-		117	printf("dpms on\n");
-		118	};
-		119	dpms ^= 1;
-		120	}
-		121	else if(key.code == 0xC6)
-		122	dpms_lock = 0;
-		123	};
-		124
-		125	spin_lock_irqsave(&cwq->lock, irqflags);
-		126
-		127	while (!list_empty(&cwq->worklist))
-		128	{
-		129	struct work_struct *work = list_entry(cwq->worklist.next,
-		130	struct work_struct, entry);
-		131	work_func_t f = work->func;
-		132	list_del_init(cwq->worklist.next);
-		133
-		134	spin_unlock_irqrestore(&cwq->lock, irqflags);
-		135	f(work);
-		136	spin_lock_irqsave(&cwq->lock, irqflags);
-		137	}
-		138
-		139	spin_unlock_irqrestore(&cwq->lock, irqflags);
-		140
-		141	delay(1);
-		142	};
-		143
-		144	asm volatile ("int $0x40"::"a"(-1));
-		145	}
63		146
64	u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline)	147	u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
65	{	148	{
66	int err = 0;	149	int err = 0;
67		150
68	if(action != 1)	151	if(action != 1)
69	{	152	{
70	driver_wq_state = 0;	153	driver_wq_state = 0;
71	return 0;	154	return 0;
72	};	155	};
73		156
74	if( GetService("DISPLAY") != 0 )	157	if( GetService("DISPLAY") != 0 )
75	return 0;	158	return 0;
76		159
77	if( cmdline && *cmdline )	160	if( cmdline && *cmdline )
78	parse_cmdline(cmdline, log);	161	parse_cmdline(cmdline, log);
79		162
80	if(!dbg_open(log))	163	if(!dbg_open(log))
81	{	164	{
82	// strcpy(log, "/tmp1/1/i915.log");	165	strcpy(log, "/tmp1/1/i915.log");
83	// strcpy(log, "/RD/1/DRIVERS/i915.log");	-
84	strcpy(log, "/BD1/4/i915.log");	-
85		166
86	if(!dbg_open(log))	167	if(!dbg_open(log))
87	{	168	{
88	printf("Can't open %s\nExit\n", log);	169	printf("Can't open %s\nExit\n", log);
89	return 0;	170	return 0;
90	};	171	};
91	}	172	}
92	dbgprintf(" i915 v3.12-6\n cmdline: %s\n", cmdline);	173	dbgprintf(" i915 v3.12-6\n cmdline: %s\n", cmdline);
93		174
94	cpu_detect();	175	cpu_detect();
95	// dbgprintf("\ncache line size %d\n", x86_clflush_size);	176	// dbgprintf("\ncache line size %d\n", x86_clflush_size);
96		177
97	enum_pci_devices();	178	enum_pci_devices();
98		179
99	err = i915_init();	180	err = i915_init();
100	if(err)	181	if(err)
101	{	182	{
102	dbgprintf("Epic Fail :(\n");	183	dbgprintf("Epic Fail :(\n");
103	return 0;	184	return 0;
104	};	185	};
105	init_display_kms(main_device);	186	init_display_kms(main_device);
106		187
107	err = RegService("DISPLAY", display_handler);	188	err = RegService("DISPLAY", display_handler);
108		189
109	if( err != 0)	190	if( err != 0)
110	dbgprintf("Set DISPLAY handler\n");	191	dbgprintf("Set DISPLAY handler\n");
111		-
112	struct drm_i915_private *dev_priv = main_device->dev_private;	-
113		192
114	driver_wq_state = 1;	193	driver_wq_state = 1;
115		194
116	run_workqueue(dev_priv->wq);	195	CreateKernelThread(i915_driver_thread);
117		196
118	return err;	197	return err;
119	};	198	};
120		199
121		200
122	#define CURRENT_API 0x0200 /* 2.00 */	201	#define CURRENT_API 0x0200 /* 2.00 */
123	#define COMPATIBLE_API 0x0100 /* 1.00 */	202	#define COMPATIBLE_API 0x0100 /* 1.00 */
124		203
125	#define API_VERSION (COMPATIBLE_API << 16) \| CURRENT_API	204	#define API_VERSION (COMPATIBLE_API << 16) \| CURRENT_API
126	#define DISPLAY_VERSION API_VERSION	205	#define DISPLAY_VERSION API_VERSION
127		206
128		207
129	#define SRV_GETVERSION 0	208	#define SRV_GETVERSION 0
130	#define SRV_ENUM_MODES 1	209	#define SRV_ENUM_MODES 1
131	#define SRV_SET_MODE 2	210	#define SRV_SET_MODE 2
132	#define SRV_GET_CAPS 3	211	#define SRV_GET_CAPS 3
133		212
134	#define SRV_CREATE_SURFACE 10	213	#define SRV_CREATE_SURFACE 10
135	#define SRV_DESTROY_SURFACE 11	214	#define SRV_DESTROY_SURFACE 11
136	#define SRV_LOCK_SURFACE 12	215	#define SRV_LOCK_SURFACE 12
137	#define SRV_UNLOCK_SURFACE 13	216	#define SRV_UNLOCK_SURFACE 13
138	#define SRV_RESIZE_SURFACE 14	217	#define SRV_RESIZE_SURFACE 14
139	#define SRV_BLIT_BITMAP 15	218	#define SRV_BLIT_BITMAP 15
140	#define SRV_BLIT_TEXTURE 16	219	#define SRV_BLIT_TEXTURE 16
141	#define SRV_BLIT_VIDEO 17	220	#define SRV_BLIT_VIDEO 17
142		221
143		222
144	#define SRV_GET_PCI_INFO 20	223	#define SRV_GET_PCI_INFO 20
145	#define SRV_GET_PARAM 21	224	#define SRV_GET_PARAM 21
146	#define SRV_I915_GEM_CREATE 22	225	#define SRV_I915_GEM_CREATE 22
147	#define SRV_DRM_GEM_CLOSE 23	226	#define SRV_DRM_GEM_CLOSE 23
148	#define SRV_I915_GEM_PIN 24	227	#define SRV_I915_GEM_PIN 24
149	#define SRV_I915_GEM_SET_CACHEING 25	228	#define SRV_I915_GEM_SET_CACHEING 25
150	#define SRV_I915_GEM_GET_APERTURE 26	229	#define SRV_I915_GEM_GET_APERTURE 26
151	#define SRV_I915_GEM_PWRITE 27	230	#define SRV_I915_GEM_PWRITE 27
152	#define SRV_I915_GEM_BUSY 28	231	#define SRV_I915_GEM_BUSY 28
153	#define SRV_I915_GEM_SET_DOMAIN 29	232	#define SRV_I915_GEM_SET_DOMAIN 29
154	#define SRV_I915_GEM_MMAP 30	233	#define SRV_I915_GEM_MMAP 30
155	#define SRV_I915_GEM_MMAP_GTT 31	234	#define SRV_I915_GEM_MMAP_GTT 31
156	#define SRV_I915_GEM_THROTTLE 32	235	#define SRV_I915_GEM_THROTTLE 32
157	#define SRV_FBINFO 33	236	#define SRV_FBINFO 33
158	#define SRV_I915_GEM_EXECBUFFER2 34	237	#define SRV_I915_GEM_EXECBUFFER2 34
159	#define SRV_MASK_UPDATE 35	238	#define SRV_MASK_UPDATE 35
160		239
161		240
162		241
163	#define check_input(size) \	242	#define check_input(size) \
164	if( unlikely((inp==NULL)\|\|(io->inp_size != (size))) ) \	243	if( unlikely((inp==NULL)\|\|(io->inp_size != (size))) ) \
165	break;	244	break;
166		245
167	#define check_output(size) \	246	#define check_output(size) \
168	if( unlikely((outp==NULL)\|\|(io->out_size != (size))) ) \	247	if( unlikely((outp==NULL)\|\|(io->out_size != (size))) ) \
169	break;	248	break;
170		249
171	int _stdcall display_handler(ioctl_t *io)	250	int _stdcall display_handler(ioctl_t *io)
172	{	251	{
173	struct drm_file *file;	252	struct drm_file *file;
174		253
175	int retval = -1;	254	int retval = -1;
176	u32_t *inp;	255	u32_t *inp;
177	u32_t *outp;	256	u32_t *outp;
178		257
179	inp = io->input;	258	inp = io->input;
180	outp = io->output;	259	outp = io->output;
181		260
182	file = drm_file_handlers[0];	261	file = drm_file_handlers[0];
183		262
184	switch(io->io_code)	263	switch(io->io_code)
185	{	264	{
186	case SRV_GETVERSION:	265	case SRV_GETVERSION:
187	check_output(4);	266	check_output(4);
188	*outp = DISPLAY_VERSION;	267	*outp = DISPLAY_VERSION;
189	retval = 0;	268	retval = 0;
190	break;	269	break;
191		270
192	case SRV_ENUM_MODES:	271	case SRV_ENUM_MODES:
193	// dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",	272	// dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
194	// inp, io->inp_size, io->out_size );	273	// inp, io->inp_size, io->out_size );
195	check_output(4);	274	check_output(4);
196	// check_input(outp sizeof(videomode_t));	275	// check_input(outp sizeof(videomode_t));
197	if( i915_modeset)	276	if( i915_modeset)
198	retval = get_videomodes((videomode_t*)inp, outp);	277	retval = get_videomodes((videomode_t*)inp, outp);
199	break;	278	break;
200		279
201	case SRV_SET_MODE:	280	case SRV_SET_MODE:
202	// dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",	281	// dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
203	// inp, io->inp_size);	282	// inp, io->inp_size);
204	check_input(sizeof(videomode_t));	283	check_input(sizeof(videomode_t));
205	if( i915_modeset )	284	if( i915_modeset )
206	retval = set_user_mode((videomode_t*)inp);	285	retval = set_user_mode((videomode_t*)inp);
207	break;	286	break;
208		287
209	case SRV_GET_CAPS:	288	case SRV_GET_CAPS:
210	retval = get_driver_caps((hwcaps_t*)inp);	289	retval = get_driver_caps((hwcaps_t*)inp);
211	break;	290	break;
212		291
213	case SRV_CREATE_SURFACE:	292	case SRV_CREATE_SURFACE:
214	// check_input(8);	293	// check_input(8);
215	// retval = create_surface(main_device, (struct io_call_10*)inp);	294	// retval = create_surface(main_device, (struct io_call_10*)inp);
216	break;	295	break;
217		296
218	case SRV_LOCK_SURFACE:	297	case SRV_LOCK_SURFACE:
219	// retval = lock_surface((struct io_call_12*)inp);	298	// retval = lock_surface((struct io_call_12*)inp);
220	break;	299	break;
221		300
222	case SRV_RESIZE_SURFACE:	301	case SRV_RESIZE_SURFACE:
223	// retval = resize_surface((struct io_call_14*)inp);	302	// retval = resize_surface((struct io_call_14*)inp);
224	break;	303	break;
225		304
226	case SRV_BLIT_BITMAP:	305	case SRV_BLIT_BITMAP:
227	// srv_blit_bitmap( inp[0], inp[1], inp[2],	306	// srv_blit_bitmap( inp[0], inp[1], inp[2],
228	// inp[3], inp[4], inp[5], inp[6]);	307	// inp[3], inp[4], inp[5], inp[6]);
229		308
230	// blit_tex( inp[0], inp[1], inp[2],	309	// blit_tex( inp[0], inp[1], inp[2],
231	// inp[3], inp[4], inp[5], inp[6]);	310	// inp[3], inp[4], inp[5], inp[6]);
232		311
233	break;	312	break;
234		313
235	case SRV_GET_PCI_INFO:	314	case SRV_GET_PCI_INFO:
236	get_pci_info((struct pci_device *)inp);	315	get_pci_info((struct pci_device *)inp);
237	retval = 0;	316	retval = 0;
238	break;	317	break;
239		318
240	case SRV_GET_PARAM:	319	case SRV_GET_PARAM:
241	retval = gem_getparam(main_device, inp);	320	retval = gem_getparam(main_device, inp);
242	break;	321	break;
243		322
244	case SRV_I915_GEM_CREATE:	323	case SRV_I915_GEM_CREATE:
245	retval = i915_gem_create_ioctl(main_device, inp, file);	324	retval = i915_gem_create_ioctl(main_device, inp, file);
246	break;	325	break;
247		326
248	case SRV_DRM_GEM_CLOSE:	327	case SRV_DRM_GEM_CLOSE:
249	retval = drm_gem_close_ioctl(main_device, inp, file);	328	retval = drm_gem_close_ioctl(main_device, inp, file);
250	break;	329	break;
251		330
252	case SRV_I915_GEM_PIN:	331	case SRV_I915_GEM_PIN:
253	retval = i915_gem_pin_ioctl(main_device, inp, file);	332	retval = i915_gem_pin_ioctl(main_device, inp, file);
254	break;	333	break;
255		334
256	case SRV_I915_GEM_SET_CACHEING:	335	case SRV_I915_GEM_SET_CACHEING:
257	retval = i915_gem_set_caching_ioctl(main_device, inp, file);	336	retval = i915_gem_set_caching_ioctl(main_device, inp, file);
258	break;	337	break;
259		338
260	case SRV_I915_GEM_GET_APERTURE:	339	case SRV_I915_GEM_GET_APERTURE:
261	retval = i915_gem_get_aperture_ioctl(main_device, inp, file);	340	retval = i915_gem_get_aperture_ioctl(main_device, inp, file);
262	break;	341	break;
263		342
264	case SRV_I915_GEM_PWRITE:	343	case SRV_I915_GEM_PWRITE:
265	retval = i915_gem_pwrite_ioctl(main_device, inp, file);	344	retval = i915_gem_pwrite_ioctl(main_device, inp, file);
266	break;	345	break;
267		346
268	case SRV_I915_GEM_BUSY:	347	case SRV_I915_GEM_BUSY:
269	retval = i915_gem_busy_ioctl(main_device, inp, file);	348	retval = i915_gem_busy_ioctl(main_device, inp, file);
270	break;	349	break;
271		350
272	case SRV_I915_GEM_SET_DOMAIN:	351	case SRV_I915_GEM_SET_DOMAIN:
273	retval = i915_gem_set_domain_ioctl(main_device, inp, file);	352	retval = i915_gem_set_domain_ioctl(main_device, inp, file);
274	break;	353	break;
275		354
276	case SRV_I915_GEM_THROTTLE:	355	case SRV_I915_GEM_THROTTLE:
277	retval = i915_gem_throttle_ioctl(main_device, inp, file);	356	retval = i915_gem_throttle_ioctl(main_device, inp, file);
278	break;	357	break;
279		358
280	case SRV_I915_GEM_MMAP:	359	case SRV_I915_GEM_MMAP:
281	retval = i915_gem_mmap_ioctl(main_device, inp, file);	360	retval = i915_gem_mmap_ioctl(main_device, inp, file);
282	break;	361	break;
283		362
284	case SRV_I915_GEM_MMAP_GTT:	363	case SRV_I915_GEM_MMAP_GTT:
285	retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);	364	retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);
286	break;	365	break;
287		366
288		367
289	case SRV_FBINFO:	368	case SRV_FBINFO:
290	retval = i915_fbinfo(inp);	369	retval = i915_fbinfo(inp);
291	break;	370	break;
292		371
293	case SRV_I915_GEM_EXECBUFFER2:	372	case SRV_I915_GEM_EXECBUFFER2:
294	retval = i915_gem_execbuffer2(main_device, inp, file);	373	retval = i915_gem_execbuffer2(main_device, inp, file);
295	break;	374	break;
296		375
297	case SRV_MASK_UPDATE:	376	case SRV_MASK_UPDATE:
298	retval = i915_mask_update(main_device, inp, file);	377	retval = i915_mask_update(main_device, inp, file);
299	break;	378	break;
300		379
301	};	380	};
302		381
303	return retval;	382	return retval;
304	}	383	}
305		384
306		385
307	#define PCI_CLASS_REVISION 0x08	386	#define PCI_CLASS_REVISION 0x08
308	#define PCI_CLASS_DISPLAY_VGA 0x0300	387	#define PCI_CLASS_DISPLAY_VGA 0x0300
309	#define PCI_CLASS_BRIDGE_HOST 0x0600	388	#define PCI_CLASS_BRIDGE_HOST 0x0600
310	#define PCI_CLASS_BRIDGE_ISA 0x0601	389	#define PCI_CLASS_BRIDGE_ISA 0x0601
311		390
312	int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)	391	int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)
313	{	392	{
314	u16_t vendor, device;	393	u16_t vendor, device;
315	u32_t class;	394	u32_t class;
316	int ret = 0;	395	int ret = 0;
317		396
318	vendor = id & 0xffff;	397	vendor = id & 0xffff;
319	device = (id >> 16) & 0xffff;	398	device = (id >> 16) & 0xffff;
320		399
321	if(vendor == 0x8086)	400	if(vendor == 0x8086)
322	{	401	{
323	class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);	402	class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
324	class >>= 16;	403	class >>= 16;
325		404
326	if( (class == PCI_CLASS_DISPLAY_VGA) \|\|	405	if( (class == PCI_CLASS_DISPLAY_VGA) \|\|
327	(class == PCI_CLASS_BRIDGE_HOST) \|\|	406	(class == PCI_CLASS_BRIDGE_HOST) \|\|
328	(class == PCI_CLASS_BRIDGE_ISA))	407	(class == PCI_CLASS_BRIDGE_ISA))
329	ret = 1;	408	ret = 1;
330	}	409	}
331	return ret;	410	return ret;
332	};	411	};
333		412
334		413
335	static char* parse_path(char p, char log)	414	static char* parse_path(char p, char log)
336	{	415	{
337	char c;	416	char c;
338		417
339	while( (c = *p++) == ' ');	418	while( (c = *p++) == ' ');
340	p--;	419	p--;
341	while( (c = log++ = p++) && (c != ' '));	420	while( (c = log++ = p++) && (c != ' '));
342	*log = 0;	421	*log = 0;
343		422
344	return p;	423	return p;
345	};	424	};
346		425
347	void parse_cmdline(char cmdline, char log)	426	void parse_cmdline(char cmdline, char log)
348	{	427	{
349	char *p = cmdline;	428	char *p = cmdline;
350		429
351	char c = *p++;	430	char c = *p++;
352		431
353	while( c )	432	while( c )
354	{	433	{
355	if( c == '-')	434	if( c == '-')
356	{	435	{
357	switch(*p++)	436	switch(*p++)
358	{	437	{
359	case 'l':	438	case 'l':
360	p = parse_path(p, log);	439	p = parse_path(p, log);
361	break;	440	break;
362	};	441	};
363	};	442	};
364	c = *p++;	443	c = *p++;
365	};	444	};
366	};	445	};
367		446
368		447
369	static inline void __cpuid(unsigned int eax, unsigned int ebx,	448	static inline void __cpuid(unsigned int eax, unsigned int ebx,
370	unsigned int ecx, unsigned int edx)	449	unsigned int ecx, unsigned int edx)
371	{	450	{
372	/* ecx is often an input as well as an output. */	451	/* ecx is often an input as well as an output. */
373	asm volatile("cpuid"	452	asm volatile("cpuid"
374	: "=a" (*eax),	453	: "=a" (*eax),
375	"=b" (*ebx),	454	"=b" (*ebx),
376	"=c" (*ecx),	455	"=c" (*ecx),
377	"=d" (*edx)	456	"=d" (*edx)
378	: "0" (eax), "2" (ecx)	457	: "0" (eax), "2" (ecx)
379	: "memory");	458	: "memory");
380	}	459	}
381		460
382		461
383		462
384	static inline void cpuid(unsigned int op,	463	static inline void cpuid(unsigned int op,
385	unsigned int eax, unsigned int ebx,	464	unsigned int eax, unsigned int ebx,
386	unsigned int ecx, unsigned int edx)	465	unsigned int ecx, unsigned int edx)
387	{	466	{
388	*eax = op;	467	*eax = op;
389	*ecx = 0;	468	*ecx = 0;
390	__cpuid(eax, ebx, ecx, edx);	469	__cpuid(eax, ebx, ecx, edx);
391	}	470	}
392		471
393	void cpu_detect()	472	void cpu_detect()
394	{	473	{
395	u32 junk, tfms, cap0, misc;	474	u32 junk, tfms, cap0, misc;
396		475
397	cpuid(0x00000001, &tfms, &misc, &junk, &cap0);	476	cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
398		477
399	if (cap0 & (1<<19))	478	if (cap0 & (1<<19))
400	{	479	{
401	x86_clflush_size = ((misc >> 8) & 0xff) * 8;	480	x86_clflush_size = ((misc >> 8) & 0xff) * 8;
402	}	481	}
403		482
404	tsc_khz = (unsigned int)(GetCpuFreq()/1000);	483	tsc_khz = (unsigned int)(GetCpuFreq()/1000);
405	}	484	}
406		485
407		486
408	int get_driver_caps(hwcaps_t *caps)	487	int get_driver_caps(hwcaps_t *caps)
409	{	488	{
410	int ret = 0;	489	int ret = 0;
411		490
412	switch(caps->idx)	491	switch(caps->idx)
413	{	492	{
414	case 0:	493	case 0:
415	caps->opt[0] = 0;	494	caps->opt[0] = 0;
416	caps->opt[1] = 0;	495	caps->opt[1] = 0;
417	break;	496	break;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/main.c – Rev 4104 → 4126