WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/main.c


#include 
#include 
#include 
#include "i915_drv.h"
//#include "intel_drv.h"
 
#include 
#include 
#include 
#include 
#include 
#include 
 
#include "bitmap.h"
 
struct pci_device {
    uint16_t    domain;
    uint8_t     bus;
    uint8_t     dev;
    uint8_t     func;
    uint16_t    vendor_id;
    uint16_t    device_id;
    uint16_t    subvendor_id;
    uint16_t    subdevice_id;
    uint32_t    device_class;
    uint8_t     revision;
};
 
extern struct drm_device *main_device;
extern struct drm_file   *drm_file_handlers[256];
 
void cpu_detect();
 
void parse_cmdline(char *cmdline, char *log);
int _stdcall display_handler(ioctl_t *io);
int init_agp(void);
 
int srv_blit_bitmap(u32 hbitmap, int  dst_x, int dst_y,
               int src_x, int src_y, u32 w, u32 h);
 
int blit_textured(u32 hbitmap, int  dst_x, int dst_y,
               int src_x, int src_y, u32 w, u32 h);
 
int blit_tex(u32 hbitmap, int  dst_x, int dst_y,
             int src_x, int src_y, u32 w, u32 h);
 
void get_pci_info(struct pci_device *dev);
int gem_getparam(struct drm_device *dev, void *data);
 
int i915_mask_update(struct drm_device *dev, void *data,
            struct drm_file *file);
 
 
static char  log[256];
 
struct workqueue_struct *system_wq;
int driver_wq_state;
 
int x86_clflush_size;
unsigned int tsc_khz;
 
int i915_modeset = 1;
 
u32_t  __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
{
 
    int     err = 0;
 
    if(action != 1)
    {
        driver_wq_state = 0;
        return 0;
    };
 
    if( GetService("DISPLAY") != 0 )
        return 0;
 
    if( cmdline && *cmdline )
        parse_cmdline(cmdline, log);
 
    if(!dbg_open(log))
    {
        strcpy(log, "/tmp1/1/i915.log");
//        strcpy(log, "/RD/1/DRIVERS/i915.log");
 
        if(!dbg_open(log))
        {
            printf("Can't open %s\nExit\n", log);
            return 0;
        };
    }
    dbgprintf(" i915 v3.10\n cmdline: %s\n", cmdline);
 
    cpu_detect();
//    dbgprintf("\ncache line size %d\n", x86_clflush_size);
 
    enum_pci_devices();
 
    err = i915_init();
 
    if(err)
    {
        dbgprintf("Epic Fail :(\n");
        return 0;
    };
 
    err = RegService("DISPLAY", display_handler);
 
    if( err != 0)
        dbgprintf("Set DISPLAY handler\n");
 
    struct drm_i915_private *dev_priv = main_device->dev_private;
 
    driver_wq_state = 1;
    run_workqueue(dev_priv->wq);
 
    return err;
};
 
 
#define CURRENT_API     0x0200      /*      2.00     */
#define COMPATIBLE_API  0x0100      /*      1.00     */
 
#define API_VERSION     (COMPATIBLE_API << 16) | CURRENT_API
#define DISPLAY_VERSION  API_VERSION
 
 
#define SRV_GETVERSION          0
#define SRV_ENUM_MODES          1
#define SRV_SET_MODE            2
#define SRV_GET_CAPS            3
 
#define SRV_CREATE_SURFACE      10
#define SRV_DESTROY_SURFACE     11
#define SRV_LOCK_SURFACE        12
#define SRV_UNLOCK_SURFACE      13
#define SRV_RESIZE_SURFACE      14
#define SRV_BLIT_BITMAP         15
#define SRV_BLIT_TEXTURE        16
#define SRV_BLIT_VIDEO          17
 
 
#define SRV_GET_PCI_INFO            20
#define SRV_GET_PARAM           21
#define SRV_I915_GEM_CREATE     22
#define SRV_DRM_GEM_CLOSE       23
#define SRV_I915_GEM_PIN        24
#define SRV_I915_GEM_SET_CACHEING   25
#define SRV_I915_GEM_GET_APERTURE   26
#define SRV_I915_GEM_PWRITE         27
#define SRV_I915_GEM_BUSY           28
#define SRV_I915_GEM_SET_DOMAIN     29
#define SRV_I915_GEM_MMAP           30
#define SRV_I915_GEM_MMAP_GTT       31
#define SRV_I915_GEM_THROTTLE       32
#define SRV_FBINFO                  33
#define SRV_I915_GEM_EXECBUFFER2    34
#define SRV_MASK_UPDATE             35
 
 
 
#define check_input(size) \
    if( unlikely((inp==NULL)||(io->inp_size != (size))) )   \
        break;
 
#define check_output(size) \
    if( unlikely((outp==NULL)||(io->out_size != (size))) )   \
        break;
 
int _stdcall display_handler(ioctl_t *io)
{
    struct drm_file *file;
 
    int    retval = -1;
    u32_t *inp;
    u32_t *outp;
 
    inp = io->input;
    outp = io->output;
 
    file = drm_file_handlers[0];
 
    switch(io->io_code)
    {
        case SRV_GETVERSION:
            check_output(4);
            *outp  = DISPLAY_VERSION;
            retval = 0;
            break;
 
        case SRV_ENUM_MODES:
//            dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
//                       inp, io->inp_size, io->out_size );
            check_output(4);
//            check_input(*outp * sizeof(videomode_t));
            if( i915_modeset)
                retval = get_videomodes((videomode_t*)inp, outp);
            break;
 
        case SRV_SET_MODE:
//            dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
//                       inp, io->inp_size);
            check_input(sizeof(videomode_t));
            if( i915_modeset )
                retval = set_user_mode((videomode_t*)inp);
            break;
 
        case SRV_GET_CAPS:
            retval = get_driver_caps((hwcaps_t*)inp);
            break;
 
        case SRV_CREATE_SURFACE:
//            check_input(8);
//            retval = create_surface(main_device, (struct io_call_10*)inp);
            break;
 
        case SRV_LOCK_SURFACE:
//            retval = lock_surface((struct io_call_12*)inp);
            break;
 
        case SRV_RESIZE_SURFACE:
//            retval = resize_surface((struct io_call_14*)inp);
            break;
 
        case SRV_BLIT_BITMAP:
//            srv_blit_bitmap( inp[0], inp[1], inp[2],
//                        inp[3], inp[4], inp[5], inp[6]);
 
//            blit_tex( inp[0], inp[1], inp[2],
//                    inp[3], inp[4], inp[5], inp[6]);
 
            break;
 
        case SRV_GET_PCI_INFO:
            get_pci_info((struct pci_device *)inp);
            retval = 0;
            break;
 
        case SRV_GET_PARAM:
            retval = gem_getparam(main_device, inp);
            break;
 
        case SRV_I915_GEM_CREATE:
            retval = i915_gem_create_ioctl(main_device, inp, file);
            break;
 
        case SRV_DRM_GEM_CLOSE:
            retval = drm_gem_close_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_PIN:
            retval = i915_gem_pin_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_SET_CACHEING:
            retval = i915_gem_set_caching_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_GET_APERTURE:
            retval = i915_gem_get_aperture_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_PWRITE:
            retval = i915_gem_pwrite_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_BUSY:
            retval = i915_gem_busy_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_SET_DOMAIN:
            retval = i915_gem_set_domain_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_THROTTLE:
            retval = i915_gem_throttle_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_MMAP:
            retval = i915_gem_mmap_ioctl(main_device, inp, file);
            break;
 
        case SRV_I915_GEM_MMAP_GTT:
            retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);
            break;
 
 
        case SRV_FBINFO:
            retval = i915_fbinfo(inp);
            break;
 
        case SRV_I915_GEM_EXECBUFFER2:
            retval = i915_gem_execbuffer2(main_device, inp, file);
            break;
 
        case SRV_MASK_UPDATE:
            retval = i915_mask_update(main_device, inp, file);
            break;
 
    };
 
    return retval;
}
 
 
#define PCI_CLASS_REVISION      0x08
#define PCI_CLASS_DISPLAY_VGA   0x0300
#define PCI_CLASS_BRIDGE_HOST   0x0600
#define PCI_CLASS_BRIDGE_ISA    0x0601
 
int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)
{
    u16_t vendor, device;
    u32_t class;
    int   ret = 0;
 
    vendor   = id & 0xffff;
    device   = (id >> 16) & 0xffff;
 
    if(vendor == 0x8086)
    {
        class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
        class >>= 16;
 
        if( (class == PCI_CLASS_DISPLAY_VGA) ||
            (class == PCI_CLASS_BRIDGE_HOST) ||
            (class == PCI_CLASS_BRIDGE_ISA))
            ret = 1;
    }
    return ret;
};
 
 
static char* parse_path(char *p, char *log)
{
    char  c;
 
    while( (c = *p++) == ' ');
        p--;
    while( (c = *log++ = *p++) && (c != ' '));
    *log = 0;
 
    return p;
};
 
void parse_cmdline(char *cmdline, char *log)
{
    char *p = cmdline;
 
    char c = *p++;
 
    while( c )
    {
        if( c == '-')
        {
            switch(*p++)
            {
                case 'l':
                    p = parse_path(p, log);
                    break;
            };
        };
        c = *p++;
    };
};
 
 
static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
                unsigned int *ecx, unsigned int *edx)
{
    /* ecx is often an input as well as an output. */
    asm volatile("cpuid"
        : "=a" (*eax),
          "=b" (*ebx),
          "=c" (*ecx),
          "=d" (*edx)
        : "0" (*eax), "2" (*ecx)
        : "memory");
}
 
 
 
static inline void cpuid(unsigned int op,
                         unsigned int *eax, unsigned int *ebx,
                         unsigned int *ecx, unsigned int *edx)
{
        *eax = op;
        *ecx = 0;
        __cpuid(eax, ebx, ecx, edx);
}
 
void cpu_detect()
{
    u32 junk, tfms, cap0, misc;
 
    cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
 
    if (cap0 & (1<<19))
    {
        x86_clflush_size = ((misc >> 8) & 0xff) * 8;
    }
 
    tsc_khz = (unsigned int)(GetCpuFreq()/1000);
}
 
 
int get_driver_caps(hwcaps_t *caps)
{
    int ret = 0;
 
    switch(caps->idx)
    {
        case 0:
            caps->opt[0] = 0;
            caps->opt[1] = 0;
            break;
 
        case 1:
            caps->cap1.max_tex_width  = 4096;
            caps->cap1.max_tex_height = 4096;
            break;
        default:
            ret = 1;
    };
    caps->idx = 1;
    return ret;
}
 
 
void get_pci_info(struct pci_device *dev)
{
    struct pci_dev *pdev = main_device->pdev;
 
    memset(dev, sizeof(*dev), 0);
 
    dev->domain     = 0;
    dev->bus        = pdev->busnr;
    dev->dev        = pdev->devfn >> 3;
    dev->func       = pdev->devfn & 7;
    dev->vendor_id  = pdev->vendor;
    dev->device_id  = pdev->device;
    dev->revision   = pdev->revision;
};
>
>

Rev 3482	Rev 3764
1	#include	1	#include
2	#include	2	#include
3	#include	3	#include
4	#include "i915_drv.h"	4	#include "i915_drv.h"
5	//#include "intel_drv.h"	5	//#include "intel_drv.h"
6		6
7	#include	7	#include
8	#include	8	#include
9	#include	9	#include
10	#include	10	#include
11	#include	11	#include
12	#include	12	#include
13		13
14	#include "bitmap.h"	14	#include "bitmap.h"
15		15
16	struct pci_device {	16	struct pci_device {
17	uint16_t domain;	17	uint16_t domain;
18	uint8_t bus;	18	uint8_t bus;
19	uint8_t dev;	19	uint8_t dev;
20	uint8_t func;	20	uint8_t func;
21	uint16_t vendor_id;	21	uint16_t vendor_id;
22	uint16_t device_id;	22	uint16_t device_id;
23	uint16_t subvendor_id;	23	uint16_t subvendor_id;
24	uint16_t subdevice_id;	24	uint16_t subdevice_id;
25	uint32_t device_class;	25	uint32_t device_class;
26	uint8_t revision;	26	uint8_t revision;
27	};	27	};
28		28
29	extern struct drm_device *main_device;	29	extern struct drm_device *main_device;
30	extern struct drm_file *drm_file_handlers[256];	30	extern struct drm_file *drm_file_handlers[256];
31		31
32	void cpu_detect();	32	void cpu_detect();
33		33
34	void parse_cmdline(char cmdline, char log);	34	void parse_cmdline(char cmdline, char log);
35	int _stdcall display_handler(ioctl_t *io);	35	int _stdcall display_handler(ioctl_t *io);
36	int init_agp(void);	36	int init_agp(void);
37		37
38	int srv_blit_bitmap(u32 hbitmap, int dst_x, int dst_y,	38	int srv_blit_bitmap(u32 hbitmap, int dst_x, int dst_y,
39	int src_x, int src_y, u32 w, u32 h);	39	int src_x, int src_y, u32 w, u32 h);
40		40
41	int blit_textured(u32 hbitmap, int dst_x, int dst_y,	41	int blit_textured(u32 hbitmap, int dst_x, int dst_y,
42	int src_x, int src_y, u32 w, u32 h);	42	int src_x, int src_y, u32 w, u32 h);
43		43
44	int blit_tex(u32 hbitmap, int dst_x, int dst_y,	44	int blit_tex(u32 hbitmap, int dst_x, int dst_y,
45	int src_x, int src_y, u32 w, u32 h);	45	int src_x, int src_y, u32 w, u32 h);
46		46
47	void get_pci_info(struct pci_device *dev);	47	void get_pci_info(struct pci_device *dev);
48	int gem_getparam(struct drm_device dev, void data);	48	int gem_getparam(struct drm_device dev, void data);
49		49
50	int i915_mask_update(struct drm_device dev, void data,	50	int i915_mask_update(struct drm_device dev, void data,
51	struct drm_file *file);	51	struct drm_file *file);
52		52
53		53
54	static char log[256];	54	static char log[256];
55		55
56	struct workqueue_struct *system_wq;	56	struct workqueue_struct *system_wq;
-		57	int driver_wq_state;
57		58
58	int x86_clflush_size;	59	int x86_clflush_size;
59	unsigned int tsc_khz;	60	unsigned int tsc_khz;
60		61
61	int i915_modeset = 1;	62	int i915_modeset = 1;
62		63
63	u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline)	64	u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
64	{	65	{
65		66
66	int err = 0;	67	int err = 0;
67		68
68	if(action != 1)	69	if(action != 1)
-		70	{
-		71	driver_wq_state = 0;
69	return 0;	72	return 0;
-		73	};
70		74
71	if( GetService("DISPLAY") != 0 )	75	if( GetService("DISPLAY") != 0 )
72	return 0;	76	return 0;
73		77
74	if( cmdline && *cmdline )	78	if( cmdline && *cmdline )
75	parse_cmdline(cmdline, log);	79	parse_cmdline(cmdline, log);
76		80
77	if(!dbg_open(log))	81	if(!dbg_open(log))
78	{	82	{
79	strcpy(log, "/tmp1/1/i915.log");	83	strcpy(log, "/tmp1/1/i915.log");
80	// strcpy(log, "/RD/1/DRIVERS/i915.log");	84	// strcpy(log, "/RD/1/DRIVERS/i915.log");
81		85
82	if(!dbg_open(log))	86	if(!dbg_open(log))
83	{	87	{
84	printf("Can't open %s\nExit\n", log);	88	printf("Can't open %s\nExit\n", log);
85	return 0;	89	return 0;
86	};	90	};
87	}	91	}
88	dbgprintf(" i915 v3.9-rc8\n cmdline: %s\n", cmdline);	92	dbgprintf(" i915 v3.10\n cmdline: %s\n", cmdline);
89		93
90	cpu_detect();	94	cpu_detect();
91	// dbgprintf("\ncache line size %d\n", x86_clflush_size);	95	// dbgprintf("\ncache line size %d\n", x86_clflush_size);
92		96
93	enum_pci_devices();	97	enum_pci_devices();
94		98
95	err = i915_init();	99	err = i915_init();
96		100
97	if(err)	101	if(err)
98	{	102	{
99	dbgprintf("Epic Fail :(\n");	103	dbgprintf("Epic Fail :(\n");
100	return 0;	104	return 0;
101	};	105	};
102		106
103	err = RegService("DISPLAY", display_handler);	107	err = RegService("DISPLAY", display_handler);
104		108
105	if( err != 0)	109	if( err != 0)
106	dbgprintf("Set DISPLAY handler\n");	110	dbgprintf("Set DISPLAY handler\n");
107		111
108	struct drm_i915_private *dev_priv = main_device->dev_private;	112	struct drm_i915_private *dev_priv = main_device->dev_private;
109		-
-		113	driver_wq_state = 1;
110	run_workqueue(dev_priv->wq);	114	run_workqueue(dev_priv->wq);
111		115
112	return err;	116	return err;
113	};	117	};
114		118
115		119
116	#define CURRENT_API 0x0200 /* 2.00 */	120	#define CURRENT_API 0x0200 /* 2.00 */
117	#define COMPATIBLE_API 0x0100 /* 1.00 */	121	#define COMPATIBLE_API 0x0100 /* 1.00 */
118		122
119	#define API_VERSION (COMPATIBLE_API << 16) \| CURRENT_API	123	#define API_VERSION (COMPATIBLE_API << 16) \| CURRENT_API
120	#define DISPLAY_VERSION API_VERSION	124	#define DISPLAY_VERSION API_VERSION
121		125
122		126
123	#define SRV_GETVERSION 0	127	#define SRV_GETVERSION 0
124	#define SRV_ENUM_MODES 1	128	#define SRV_ENUM_MODES 1
125	#define SRV_SET_MODE 2	129	#define SRV_SET_MODE 2
126	#define SRV_GET_CAPS 3	130	#define SRV_GET_CAPS 3
127		131
128	#define SRV_CREATE_SURFACE 10	132	#define SRV_CREATE_SURFACE 10
129	#define SRV_DESTROY_SURFACE 11	133	#define SRV_DESTROY_SURFACE 11
130	#define SRV_LOCK_SURFACE 12	134	#define SRV_LOCK_SURFACE 12
131	#define SRV_UNLOCK_SURFACE 13	135	#define SRV_UNLOCK_SURFACE 13
132	#define SRV_RESIZE_SURFACE 14	136	#define SRV_RESIZE_SURFACE 14
133	#define SRV_BLIT_BITMAP 15	137	#define SRV_BLIT_BITMAP 15
134	#define SRV_BLIT_TEXTURE 16	138	#define SRV_BLIT_TEXTURE 16
135	#define SRV_BLIT_VIDEO 17	139	#define SRV_BLIT_VIDEO 17
136		140
137		141
138	#define SRV_GET_PCI_INFO 20	142	#define SRV_GET_PCI_INFO 20
139	#define SRV_GET_PARAM 21	143	#define SRV_GET_PARAM 21
140	#define SRV_I915_GEM_CREATE 22	144	#define SRV_I915_GEM_CREATE 22
141	#define SRV_DRM_GEM_CLOSE 23	145	#define SRV_DRM_GEM_CLOSE 23
142	#define SRV_I915_GEM_PIN 24	146	#define SRV_I915_GEM_PIN 24
143	#define SRV_I915_GEM_SET_CACHEING 25	147	#define SRV_I915_GEM_SET_CACHEING 25
144	#define SRV_I915_GEM_GET_APERTURE 26	148	#define SRV_I915_GEM_GET_APERTURE 26
145	#define SRV_I915_GEM_PWRITE 27	149	#define SRV_I915_GEM_PWRITE 27
146	#define SRV_I915_GEM_BUSY 28	150	#define SRV_I915_GEM_BUSY 28
147	#define SRV_I915_GEM_SET_DOMAIN 29	151	#define SRV_I915_GEM_SET_DOMAIN 29
148	#define SRV_I915_GEM_MMAP 30	152	#define SRV_I915_GEM_MMAP 30
149	#define SRV_I915_GEM_MMAP_GTT 31	153	#define SRV_I915_GEM_MMAP_GTT 31
150	#define SRV_I915_GEM_THROTTLE 32	154	#define SRV_I915_GEM_THROTTLE 32
151	#define SRV_FBINFO 33	155	#define SRV_FBINFO 33
152	#define SRV_I915_GEM_EXECBUFFER2 34	156	#define SRV_I915_GEM_EXECBUFFER2 34
153	#define SRV_MASK_UPDATE 35	157	#define SRV_MASK_UPDATE 35
154		158
155		159
156		160
157	#define check_input(size) \	161	#define check_input(size) \
158	if( unlikely((inp==NULL)\|\|(io->inp_size != (size))) ) \	162	if( unlikely((inp==NULL)\|\|(io->inp_size != (size))) ) \
159	break;	163	break;
160		164
161	#define check_output(size) \	165	#define check_output(size) \
162	if( unlikely((outp==NULL)\|\|(io->out_size != (size))) ) \	166	if( unlikely((outp==NULL)\|\|(io->out_size != (size))) ) \
163	break;	167	break;
164		168
165	int _stdcall display_handler(ioctl_t *io)	169	int _stdcall display_handler(ioctl_t *io)
166	{	170	{
167	struct drm_file *file;	171	struct drm_file *file;
168		172
169	int retval = -1;	173	int retval = -1;
170	u32_t *inp;	174	u32_t *inp;
171	u32_t *outp;	175	u32_t *outp;
172		176
173	inp = io->input;	177	inp = io->input;
174	outp = io->output;	178	outp = io->output;
175		179
176	file = drm_file_handlers[0];	180	file = drm_file_handlers[0];
177		181
178	switch(io->io_code)	182	switch(io->io_code)
179	{	183	{
180	case SRV_GETVERSION:	184	case SRV_GETVERSION:
181	check_output(4);	185	check_output(4);
182	*outp = DISPLAY_VERSION;	186	*outp = DISPLAY_VERSION;
183	retval = 0;	187	retval = 0;
184	break;	188	break;
185		189
186	case SRV_ENUM_MODES:	190	case SRV_ENUM_MODES:
187	// dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",	191	// dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
188	// inp, io->inp_size, io->out_size );	192	// inp, io->inp_size, io->out_size );
189	check_output(4);	193	check_output(4);
190	// check_input(outp sizeof(videomode_t));	194	// check_input(outp sizeof(videomode_t));
191	if( i915_modeset)	195	if( i915_modeset)
192	retval = get_videomodes((videomode_t*)inp, outp);	196	retval = get_videomodes((videomode_t*)inp, outp);
193	break;	197	break;
194		198
195	case SRV_SET_MODE:	199	case SRV_SET_MODE:
196	// dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",	200	// dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
197	// inp, io->inp_size);	201	// inp, io->inp_size);
198	check_input(sizeof(videomode_t));	202	check_input(sizeof(videomode_t));
199	if( i915_modeset )	203	if( i915_modeset )
200	retval = set_user_mode((videomode_t*)inp);	204	retval = set_user_mode((videomode_t*)inp);
201	break;	205	break;
202		206
203	case SRV_GET_CAPS:	207	case SRV_GET_CAPS:
204	retval = get_driver_caps((hwcaps_t*)inp);	208	retval = get_driver_caps((hwcaps_t*)inp);
205	break;	209	break;
206		210
207	case SRV_CREATE_SURFACE:	211	case SRV_CREATE_SURFACE:
208	// check_input(8);	212	// check_input(8);
209	// retval = create_surface(main_device, (struct io_call_10*)inp);	213	// retval = create_surface(main_device, (struct io_call_10*)inp);
210	break;	214	break;
211		215
212	case SRV_LOCK_SURFACE:	216	case SRV_LOCK_SURFACE:
213	// retval = lock_surface((struct io_call_12*)inp);	217	// retval = lock_surface((struct io_call_12*)inp);
214	break;	218	break;
215		219
216	case SRV_RESIZE_SURFACE:	220	case SRV_RESIZE_SURFACE:
217	// retval = resize_surface((struct io_call_14*)inp);	221	// retval = resize_surface((struct io_call_14*)inp);
218	break;	222	break;
219		223
220	case SRV_BLIT_BITMAP:	224	case SRV_BLIT_BITMAP:
221	// srv_blit_bitmap( inp[0], inp[1], inp[2],	225	// srv_blit_bitmap( inp[0], inp[1], inp[2],
222	// inp[3], inp[4], inp[5], inp[6]);	226	// inp[3], inp[4], inp[5], inp[6]);
223		227
224	// blit_tex( inp[0], inp[1], inp[2],	228	// blit_tex( inp[0], inp[1], inp[2],
225	// inp[3], inp[4], inp[5], inp[6]);	229	// inp[3], inp[4], inp[5], inp[6]);
226		230
227	break;	231	break;
228		232
229	case SRV_GET_PCI_INFO:	233	case SRV_GET_PCI_INFO:
230	get_pci_info((struct pci_device *)inp);	234	get_pci_info((struct pci_device *)inp);
231	retval = 0;	235	retval = 0;
232	break;	236	break;
233		237
234	case SRV_GET_PARAM:	238	case SRV_GET_PARAM:
235	retval = gem_getparam(main_device, inp);	239	retval = gem_getparam(main_device, inp);
236	break;	240	break;
237		241
238	case SRV_I915_GEM_CREATE:	242	case SRV_I915_GEM_CREATE:
239	retval = i915_gem_create_ioctl(main_device, inp, file);	243	retval = i915_gem_create_ioctl(main_device, inp, file);
240	break;	244	break;
241		245
242	case SRV_DRM_GEM_CLOSE:	246	case SRV_DRM_GEM_CLOSE:
243	retval = drm_gem_close_ioctl(main_device, inp, file);	247	retval = drm_gem_close_ioctl(main_device, inp, file);
244	break;	248	break;
245		249
246	case SRV_I915_GEM_PIN:	250	case SRV_I915_GEM_PIN:
247	retval = i915_gem_pin_ioctl(main_device, inp, file);	251	retval = i915_gem_pin_ioctl(main_device, inp, file);
248	break;	252	break;
249		253
250	case SRV_I915_GEM_SET_CACHEING:	254	case SRV_I915_GEM_SET_CACHEING:
251	retval = i915_gem_set_caching_ioctl(main_device, inp, file);	255	retval = i915_gem_set_caching_ioctl(main_device, inp, file);
252	break;	256	break;
253		257
254	case SRV_I915_GEM_GET_APERTURE:	258	case SRV_I915_GEM_GET_APERTURE:
255	retval = i915_gem_get_aperture_ioctl(main_device, inp, file);	259	retval = i915_gem_get_aperture_ioctl(main_device, inp, file);
256	break;	260	break;
257		261
258	case SRV_I915_GEM_PWRITE:	262	case SRV_I915_GEM_PWRITE:
259	retval = i915_gem_pwrite_ioctl(main_device, inp, file);	263	retval = i915_gem_pwrite_ioctl(main_device, inp, file);
260	break;	264	break;
261		265
262	case SRV_I915_GEM_BUSY:	266	case SRV_I915_GEM_BUSY:
263	retval = i915_gem_busy_ioctl(main_device, inp, file);	267	retval = i915_gem_busy_ioctl(main_device, inp, file);
264	break;	268	break;
265		269
266	case SRV_I915_GEM_SET_DOMAIN:	270	case SRV_I915_GEM_SET_DOMAIN:
267	retval = i915_gem_set_domain_ioctl(main_device, inp, file);	271	retval = i915_gem_set_domain_ioctl(main_device, inp, file);
268	break;	272	break;
269		273
270	case SRV_I915_GEM_THROTTLE:	274	case SRV_I915_GEM_THROTTLE:
271	retval = i915_gem_throttle_ioctl(main_device, inp, file);	275	retval = i915_gem_throttle_ioctl(main_device, inp, file);
272	break;	276	break;
273		277
274	case SRV_I915_GEM_MMAP:	278	case SRV_I915_GEM_MMAP:
275	retval = i915_gem_mmap_ioctl(main_device, inp, file);	279	retval = i915_gem_mmap_ioctl(main_device, inp, file);
276	break;	280	break;
277		281
278	case SRV_I915_GEM_MMAP_GTT:	282	case SRV_I915_GEM_MMAP_GTT:
279	retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);	283	retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);
280	break;	284	break;
281		285
282		286
283	case SRV_FBINFO:	287	case SRV_FBINFO:
284	retval = i915_fbinfo(inp);	288	retval = i915_fbinfo(inp);
285	break;	289	break;
286		290
287	case SRV_I915_GEM_EXECBUFFER2:	291	case SRV_I915_GEM_EXECBUFFER2:
288	retval = i915_gem_execbuffer2(main_device, inp, file);	292	retval = i915_gem_execbuffer2(main_device, inp, file);
289	break;	293	break;
290		294
291	case SRV_MASK_UPDATE:	295	case SRV_MASK_UPDATE:
292	retval = i915_mask_update(main_device, inp, file);	296	retval = i915_mask_update(main_device, inp, file);
293	break;	297	break;
294		298
295	};	299	};
296		300
297	return retval;	301	return retval;
298	}	302	}
299		303
300		304
301	#define PCI_CLASS_REVISION 0x08	305	#define PCI_CLASS_REVISION 0x08
302	#define PCI_CLASS_DISPLAY_VGA 0x0300	306	#define PCI_CLASS_DISPLAY_VGA 0x0300
303	#define PCI_CLASS_BRIDGE_HOST 0x0600	307	#define PCI_CLASS_BRIDGE_HOST 0x0600
304	#define PCI_CLASS_BRIDGE_ISA 0x0601	308	#define PCI_CLASS_BRIDGE_ISA 0x0601
305		309
306	int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)	310	int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)
307	{	311	{
308	u16_t vendor, device;	312	u16_t vendor, device;
309	u32_t class;	313	u32_t class;
310	int ret = 0;	314	int ret = 0;
311		315
312	vendor = id & 0xffff;	316	vendor = id & 0xffff;
313	device = (id >> 16) & 0xffff;	317	device = (id >> 16) & 0xffff;
314		318
315	if(vendor == 0x8086)	319	if(vendor == 0x8086)
316	{	320	{
317	class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);	321	class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
318	class >>= 16;	322	class >>= 16;
319		323
320	if( (class == PCI_CLASS_DISPLAY_VGA) \|\|	324	if( (class == PCI_CLASS_DISPLAY_VGA) \|\|
321	(class == PCI_CLASS_BRIDGE_HOST) \|\|	325	(class == PCI_CLASS_BRIDGE_HOST) \|\|
322	(class == PCI_CLASS_BRIDGE_ISA))	326	(class == PCI_CLASS_BRIDGE_ISA))
323	ret = 1;	327	ret = 1;
324	}	328	}
325	return ret;	329	return ret;
326	};	330	};
327		331
328		332
329	static char* parse_path(char p, char log)	333	static char* parse_path(char p, char log)
330	{	334	{
331	char c;	335	char c;
332		336
333	while( (c = *p++) == ' ');	337	while( (c = *p++) == ' ');
334	p--;	338	p--;
335	while( (c = log++ = p++) && (c != ' '));	339	while( (c = log++ = p++) && (c != ' '));
336	*log = 0;	340	*log = 0;
337		341
338	return p;	342	return p;
339	};	343	};
340		344
341	void parse_cmdline(char cmdline, char log)	345	void parse_cmdline(char cmdline, char log)
342	{	346	{
343	char *p = cmdline;	347	char *p = cmdline;
344		348
345	char c = *p++;	349	char c = *p++;
346		350
347	while( c )	351	while( c )
348	{	352	{
349	if( c == '-')	353	if( c == '-')
350	{	354	{
351	switch(*p++)	355	switch(*p++)
352	{	356	{
353	case 'l':	357	case 'l':
354	p = parse_path(p, log);	358	p = parse_path(p, log);
355	break;	359	break;
356	};	360	};
357	};	361	};
358	c = *p++;	362	c = *p++;
359	};	363	};
360	};	364	};
361		365
362		366
363	static inline void __cpuid(unsigned int eax, unsigned int ebx,	367	static inline void __cpuid(unsigned int eax, unsigned int ebx,
364	unsigned int ecx, unsigned int edx)	368	unsigned int ecx, unsigned int edx)
365	{	369	{
366	/* ecx is often an input as well as an output. */	370	/* ecx is often an input as well as an output. */
367	asm volatile("cpuid"	371	asm volatile("cpuid"
368	: "=a" (*eax),	372	: "=a" (*eax),
369	"=b" (*ebx),	373	"=b" (*ebx),
370	"=c" (*ecx),	374	"=c" (*ecx),
371	"=d" (*edx)	375	"=d" (*edx)
372	: "0" (eax), "2" (ecx)	376	: "0" (eax), "2" (ecx)
373	: "memory");	377	: "memory");
374	}	378	}
375		379
376		380
377		381
378	static inline void cpuid(unsigned int op,	382	static inline void cpuid(unsigned int op,
379	unsigned int eax, unsigned int ebx,	383	unsigned int eax, unsigned int ebx,
380	unsigned int ecx, unsigned int edx)	384	unsigned int ecx, unsigned int edx)
381	{	385	{
382	*eax = op;	386	*eax = op;
383	*ecx = 0;	387	*ecx = 0;
384	__cpuid(eax, ebx, ecx, edx);	388	__cpuid(eax, ebx, ecx, edx);
385	}	389	}
386		390
387	void cpu_detect()	391	void cpu_detect()
388	{	392	{
389	u32 junk, tfms, cap0, misc;	393	u32 junk, tfms, cap0, misc;
390		394
391	cpuid(0x00000001, &tfms, &misc, &junk, &cap0);	395	cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
392		396
393	if (cap0 & (1<<19))	397	if (cap0 & (1<<19))
394	{	398	{
395	x86_clflush_size = ((misc >> 8) & 0xff) * 8;	399	x86_clflush_size = ((misc >> 8) & 0xff) * 8;
396	}	400	}
397		401
398	tsc_khz = (unsigned int)(GetCpuFreq()/1000);	402	tsc_khz = (unsigned int)(GetCpuFreq()/1000);
399	}	403	}
400		404
401		405
402	int get_driver_caps(hwcaps_t *caps)	406	int get_driver_caps(hwcaps_t *caps)
403	{	407	{
404	int ret = 0;	408	int ret = 0;
405		409
406	switch(caps->idx)	410	switch(caps->idx)
407	{	411	{
408	case 0:	412	case 0:
409	caps->opt[0] = 0;	413	caps->opt[0] = 0;
410	caps->opt[1] = 0;	414	caps->opt[1] = 0;
411	break;	415	break;
412		416
413	case 1:	417	case 1:
414	caps->cap1.max_tex_width = 4096;	418	caps->cap1.max_tex_width = 4096;
415	caps->cap1.max_tex_height = 4096;	419	caps->cap1.max_tex_height = 4096;
416	break;	420	break;
417	default:	421	default:
418	ret = 1;	422	ret = 1;
419	};	423	};
420	caps->idx = 1;	424	caps->idx = 1;
421	return ret;	425	return ret;
422	}	426	}
423		427
424		428
425	void get_pci_info(struct pci_device *dev)	429	void get_pci_info(struct pci_device *dev)
426	{	430	{
427	struct pci_dev *pdev = main_device->pdev;	431	struct pci_dev *pdev = main_device->pdev;
428		432
429	memset(dev, sizeof(*dev), 0);	433	memset(dev, sizeof(*dev), 0);
430		434
431	dev->domain = 0;	435	dev->domain = 0;
432	dev->bus = pdev->busnr;	436	dev->bus = pdev->busnr;
433	dev->dev = pdev->devfn >> 3;	437	dev->dev = pdev->devfn >> 3;
434	dev->func = pdev->devfn & 7;	438	dev->func = pdev->devfn & 7;
435	dev->vendor_id = pdev->vendor;	439	dev->vendor_id = pdev->vendor;
436	dev->device_id = pdev->device;	440	dev->device_id = pdev->device;
437	dev->revision = pdev->revision;	441	dev->revision = pdev->revision;
438	};	442	};
439	>	443	>
440	>	444	>

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(root)/drivers/video/drm/i915/main.c – Rev 3482 → 3764