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Line 51... | Line 51... | ||
51 | }; |
51 | }; |
Line 52... | Line 52... | ||
52 | 52 | ||
53 | #define PCI_CLASS_REVISION 0x08 |
53 | #define PCI_CLASS_REVISION 0x08 |
54 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
54 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
- | 55 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
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Line 55... | Line 56... | ||
55 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
56 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
56 | 57 | ||
57 | int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn) |
58 | int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn) |
58 | { |
59 | { |
Line 67... | Line 68... | ||
67 | { |
68 | { |
68 | class = PciRead32(busnr, devfn, PCI_CLASS_REVISION); |
69 | class = PciRead32(busnr, devfn, PCI_CLASS_REVISION); |
69 | class >>= 16; |
70 | class >>= 16; |
Line 70... | Line 71... | ||
70 | 71 | ||
71 | if( (class == PCI_CLASS_DISPLAY_VGA) || |
72 | if( (class == PCI_CLASS_DISPLAY_VGA) || |
- | 73 | (class == PCI_CLASS_BRIDGE_HOST) || |
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72 | (class == PCI_CLASS_BRIDGE_HOST) ) |
74 | (class == PCI_CLASS_BRIDGE_ISA)) |
73 | ret = 1; |
75 | ret = 1; |
74 | } |
76 | } |
75 | return ret; |
77 | return ret; |