WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_uncore.c

  * IN THE SOFTWARE.
  */
 #include "i915_drv.h"
+#include "intel_drv.h"
+#include "i915_vgpu.h"
-#include "intel_drv.h"
+#include
-#define FORCEWAKE_ACK_TIMEOUT_MS 2
+#define FORCEWAKE_ACK_TIMEOUT_MS 50
 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
+#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
+static const char * const forcewake_domain_names[] = {
+	"render",
+	"blitter",
+	"media",
+};
+const char *
+intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
+{
+	BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
+	if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
+		return forcewake_domain_names[id];
+	WARN_ON(id);
+	return "unknown";
 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
 static void
 assert_device_not_suspended(struct drm_i915_private *dev_priv)
+{
 	WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
+		  "Device suspended\n");
-	     "Device suspended\n");
+}
-static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
+static inline void
-{
-	/* w/a for a sporadic read returning 0 by waiting for the GT
+fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
-	 * thread to wake up.
-	 */
 	if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
+	WARN_ON(d->reg_set == 0);
-				GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
+	__raw_i915_write32(d->i915, d->reg_set, d->val_reset);
 		DRM_ERROR("GT thread status wait timed out\n");
-}
+static inline void
-static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
+fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
+{
+//	__raw_i915_write32(dev_priv, FORCEWAKE, 0);
-	__raw_i915_write32(dev_priv, FORCEWAKE, 0);
+//	/* something from same cacheline, but !FORCEWAKE */
-	/* something from same cacheline, but !FORCEWAKE */
-	__raw_posting_read(dev_priv, ECOBUS);
+//	__raw_posting_read(dev_priv, ECOBUS);
 }
 static inline void
-static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
+fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
+{
+	if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
-							int fw_engine)
+			     FORCEWAKE_KERNEL) == 0,
-{
+			    FORCEWAKE_ACK_TIMEOUT_MS))
+		DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
-	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
+			  intel_uncore_forcewake_domain_to_str(d->id));
+}
+static inline void
+fw_domain_get(const struct intel_uncore_forcewake_domain *d)
-			    FORCEWAKE_ACK_TIMEOUT_MS))
+{
+	__raw_i915_write32(d->i915, d->reg_set, d->val_set);
 		DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
+static inline void
+fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
-	__raw_i915_write32(dev_priv, FORCEWAKE, 1);
+{
+	if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
+			     FORCEWAKE_KERNEL),
-	/* something from same cacheline, but !FORCEWAKE */
+			    FORCEWAKE_ACK_TIMEOUT_MS))
-	__raw_posting_read(dev_priv, ECOBUS);
+		DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
+			  intel_uncore_forcewake_domain_to_str(d->id));
+}
 	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
-			    FORCEWAKE_ACK_TIMEOUT_MS))
-		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
+static inline void
+fw_domain_put(const struct intel_uncore_forcewake_domain *d)
+{
-	/* WaRsForcewakeWaitTC0:snb */
+	__raw_i915_write32(d->i915, d->reg_set, d->val_clear);
+}
-	__gen6_gt_wait_for_thread_c0(dev_priv);
-}
 static inline void
+fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
-static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
+{
-{
+	/* something from same cacheline, but not from the set register */
-	__raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
+	if (d->reg_post)
-	/* something from same cacheline, but !FORCEWAKE_MT */
+		__raw_posting_read(d->i915, d->reg_post);
-	__raw_posting_read(dev_priv, ECOBUS);
+}
+static void
+fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
-}
+{
+	struct intel_uncore_forcewake_domain *d;
+	enum forcewake_domain_id id;
-static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
-							int fw_engine)
+	for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
-{
+		fw_domain_wait_ack_clear(d);
-	u32 forcewake_ack;
+		fw_domain_get(d);
+		fw_domain_wait_ack(d);
+	}
+}
+static void
+fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
+{
+	struct intel_uncore_forcewake_domain *d;
+	enum forcewake_domain_id id;
+	for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
+		fw_domain_put(d);
+		fw_domain_posting_read(d);
+	}
+}
-	if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev))
+static void
+fw_domains_posting_read(struct drm_i915_private *dev_priv)
+{
+	struct intel_uncore_forcewake_domain *d;
+	enum forcewake_domain_id id;
-		forcewake_ack = FORCEWAKE_ACK_HSW;
+	/* No need to do for all, just do for first found */
+	for_each_fw_domain(d, dev_priv, id) {
-	else
+		fw_domain_posting_read(d);
+		break;
+	}
+}
+static void
+fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
+{
+	struct intel_uncore_forcewake_domain *d;
+	enum forcewake_domain_id id;
+	if (dev_priv->uncore.fw_domains == 0)
+		return;
+	for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
+		fw_domain_reset(d);
+	fw_domains_posting_read(dev_priv);
+}
-		forcewake_ack = FORCEWAKE_MT_ACK;
+static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
+{
-	if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
+	/* w/a for a sporadic read returning 0 by waiting for the GT
-			    FORCEWAKE_ACK_TIMEOUT_MS))
+	 * thread to wake up.
-		DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
+	 */
 	gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 	if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 		__raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
+}
-static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
+static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
-							int fw_engine)
+				     enum forcewake_domains fw_domains)
-{
-	__raw_i915_write32(dev_priv, FORCEWAKE, 0);
-	/* something from same cacheline, but !FORCEWAKE */
+{
-	__raw_posting_read(dev_priv, ECOBUS);
+	fw_domains_put(dev_priv, fw_domains);
 	gen6_gt_check_fifodbg(dev_priv);
 }
 static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
-							int fw_engine)
+static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
-{
-	__raw_i915_write32(dev_priv, FORCEWAKE_MT,
-			   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
-	/* something from same cacheline, but !FORCEWAKE_MT */
-	__raw_posting_read(dev_priv, ECOBUS);
+{
 	u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 	if (IS_GEN7(dev_priv->dev))
-	gen6_gt_check_fifodbg(dev_priv);
+	return count & GT_FIFO_FREE_ENTRIES_MASK;
+}
 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
+{
 	int ret = 0;
-	/* On VLV, FIFO will be shared by both SW and HW.
 	 * So, we need to read the FREE_ENTRIES everytime */
-	if (IS_VALLEYVIEW(dev_priv->dev))
+	/* On VLV, FIFO will be shared by both SW and HW.
-		dev_priv->uncore.fifo_count =
+	 * So, we need to read the FREE_ENTRIES everytime */
+	if (IS_VALLEYVIEW(dev_priv->dev))
-			__raw_i915_read32(dev_priv, GTFIFOCTL) &
+		dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 						GT_FIFO_FREE_ENTRIES_MASK;
+	if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
-	if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
+		int loop = 500;
-		int loop = 500;
+		u32 fifo = fifo_free_entries(dev_priv);
 		u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 		while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 			udelay(10);
-			fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
+			fifo = fifo_free_entries(dev_priv);
+		}
 		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 			++ret;
-		dev_priv->uncore.fifo_count = fifo;
-	}
-	dev_priv->uncore.fifo_count--;
-	return ret;
-}
-static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
-{
-	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
-			   _MASKED_BIT_DISABLE(0xffff));
-	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
-			   _MASKED_BIT_DISABLE(0xffff));
-	/* something from same cacheline, but !FORCEWAKE_VLV */
-	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
-}
-static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
-						int fw_engine)
-{
-	/* Check for Render Engine */
-	if (FORCEWAKE_RENDER & fw_engine) {
-		if (wait_for_atomic((__raw_i915_read32(dev_priv,
-						FORCEWAKE_ACK_VLV) &
-						FORCEWAKE_KERNEL) == 0,
-			    FORCEWAKE_ACK_TIMEOUT_MS))
-			DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
-	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
-			   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
-		if (wait_for_atomic((__raw_i915_read32(dev_priv,
-						FORCEWAKE_ACK_VLV) &
-						FORCEWAKE_KERNEL),
-					FORCEWAKE_ACK_TIMEOUT_MS))
-			DRM_ERROR("Timed out: waiting for Render to ack.\n");
-	}
-	/* Check for Media Engine */
-	if (FORCEWAKE_MEDIA & fw_engine) {
-		if (wait_for_atomic((__raw_i915_read32(dev_priv,
-						FORCEWAKE_ACK_MEDIA_VLV) &
-						FORCEWAKE_KERNEL) == 0,
-					FORCEWAKE_ACK_TIMEOUT_MS))
-			DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
-	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
-			   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
-		if (wait_for_atomic((__raw_i915_read32(dev_priv,
-						FORCEWAKE_ACK_MEDIA_VLV) &
-			     FORCEWAKE_KERNEL),
-			    FORCEWAKE_ACK_TIMEOUT_MS))
-			DRM_ERROR("Timed out: waiting for media to ack.\n");
-	}
-}
-static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
-					int fw_engine)
-{
-	/* Check for Render Engine */
-	if (FORCEWAKE_RENDER & fw_engine)
-	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
-			   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
-	/* Check for Media Engine */
-	if (FORCEWAKE_MEDIA & fw_engine)
-	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
-			   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 		dev_priv->uncore.fifo_count = fifo;
+	}
-	/* something from same cacheline, but !FORCEWAKE_VLV */
+	dev_priv->uncore.fifo_count--;
-	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
-	if (!IS_CHERRYVIEW(dev_priv->dev))
-	gen6_gt_check_fifodbg(dev_priv);
+	return ret;
-}
-static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
+}
-{
-	unsigned long irqflags;
+static void intel_uncore_fw_release_timer(unsigned long arg)
+{
+	struct intel_uncore_forcewake_domain *domain = (void *)arg;
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+	unsigned long irqflags;
-	if (fw_engine & FORCEWAKE_RENDER &&
+	assert_device_not_suspended(domain->i915);
 	    dev_priv->uncore.fw_rendercount++ != 0)
+	spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
-		fw_engine &= ~FORCEWAKE_RENDER;
+	if (WARN_ON(domain->wake_count == 0))
+		domain->wake_count++;
+	if (--domain->wake_count == 0)
+		domain->i915->uncore.funcs.force_wake_put(domain->i915,
-	if (fw_engine & FORCEWAKE_MEDIA &&
-	    dev_priv->uncore.fw_mediacount++ != 0)
-		fw_engine &= ~FORCEWAKE_MEDIA;
-	if (fw_engine)
-		dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-}
-static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
-{
-	unsigned long irqflags;
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-	if (fw_engine & FORCEWAKE_RENDER) {
-		WARN_ON(!dev_priv->uncore.fw_rendercount);
+<< domain->id);
-		if (--dev_priv->uncore.fw_rendercount != 0)
-			fw_engine &= ~FORCEWAKE_RENDER;
-	}
-	if (fw_engine & FORCEWAKE_MEDIA) {
-		WARN_ON(!dev_priv->uncore.fw_mediacount);
-		if (--dev_priv->uncore.fw_mediacount != 0)
-			fw_engine &= ~FORCEWAKE_MEDIA;
-	}
-	if (fw_engine)
-		dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-}
-static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
-{
+	spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
-	__raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
-			_MASKED_BIT_DISABLE(0xffff));
-	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
-			_MASKED_BIT_DISABLE(0xffff));
-	__raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
-			_MASKED_BIT_DISABLE(0xffff));
-}
-static void
-__gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
-{
-	/* Check for Render Engine */
-	if (FORCEWAKE_RENDER & fw_engine) {
-		if (wait_for_atomic((__raw_i915_read32(dev_priv,
+}
-						FORCEWAKE_ACK_RENDER_GEN9) &
-						FORCEWAKE_KERNEL) == 0,
-					FORCEWAKE_ACK_TIMEOUT_MS))
-			DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
-		__raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
-				   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
-		if (wait_for_atomic((__raw_i915_read32(dev_priv,
-						FORCEWAKE_ACK_RENDER_GEN9) &
-						FORCEWAKE_KERNEL),
-					FORCEWAKE_ACK_TIMEOUT_MS))
-			DRM_ERROR("Timed out: waiting for Render to ack.\n");
-	}
-	/* Check for Media Engine */
-	if (FORCEWAKE_MEDIA & fw_engine) {
-		if (wait_for_atomic((__raw_i915_read32(dev_priv,
-						FORCEWAKE_ACK_MEDIA_GEN9) &
-						FORCEWAKE_KERNEL) == 0,
-					FORCEWAKE_ACK_TIMEOUT_MS))
-			DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
-		__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
+void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
-				   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
-		if (wait_for_atomic((__raw_i915_read32(dev_priv,
-						FORCEWAKE_ACK_MEDIA_GEN9) &
-						FORCEWAKE_KERNEL),
-					FORCEWAKE_ACK_TIMEOUT_MS))
+{
-			DRM_ERROR("Timed out: waiting for Media to ack.\n");
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	}
+	unsigned long irqflags;
-	/* Check for Blitter Engine */
-	if (FORCEWAKE_BLITTER & fw_engine) {
-		if (wait_for_atomic((__raw_i915_read32(dev_priv,
-						FORCEWAKE_ACK_BLITTER_GEN9) &
-						FORCEWAKE_KERNEL) == 0,
-					FORCEWAKE_ACK_TIMEOUT_MS))
-			DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n");
-		__raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
-				   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
-		if (wait_for_atomic((__raw_i915_read32(dev_priv,
-						FORCEWAKE_ACK_BLITTER_GEN9) &
-						FORCEWAKE_KERNEL),
+	struct intel_uncore_forcewake_domain *domain;
-					FORCEWAKE_ACK_TIMEOUT_MS))
-			DRM_ERROR("Timed out: waiting for Blitter to ack.\n");
-	}
-}
-static void
-__gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
+	int retry_count = 100;
-{
-	/* Check for Render Engine */
-	if (FORCEWAKE_RENDER & fw_engine)
-		__raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
-				_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 	enum forcewake_domain_id id;
-	/* Check for Media Engine */
-	if (FORCEWAKE_MEDIA & fw_engine)
-		__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
+	enum forcewake_domains fw = 0, active_domains;
-				_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
-	/* Check for Blitter Engine */
-	if (FORCEWAKE_BLITTER & fw_engine)
-		__raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
-				_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
-}
-static void
-gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
-{
-	unsigned long irqflags;
+	/* Hold uncore.lock across reset to prevent any register access
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+	 * with forcewake not set correctly. Wait until all pending
-	if (FORCEWAKE_RENDER & fw_engine) {
-		if (dev_priv->uncore.fw_rendercount++ == 0)
-			dev_priv->uncore.funcs.force_wake_get(dev_priv,
-							FORCEWAKE_RENDER);
-	}
-	if (FORCEWAKE_MEDIA & fw_engine) {
-		if (dev_priv->uncore.fw_mediacount++ == 0)
-			dev_priv->uncore.funcs.force_wake_get(dev_priv,
-							FORCEWAKE_MEDIA);
-	}
-	if (FORCEWAKE_BLITTER & fw_engine) {
-		if (dev_priv->uncore.fw_blittercount++ == 0)
-			dev_priv->uncore.funcs.force_wake_get(dev_priv,
-							FORCEWAKE_BLITTER);
-	}
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+	 * timers are run before holding.
-}
-static void
-gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
-{
-	unsigned long irqflags;
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-	if (FORCEWAKE_RENDER & fw_engine) {
+	 */
+	while (1) {
-		WARN_ON(dev_priv->uncore.fw_rendercount == 0);
+		active_domains = 0;
-		if (--dev_priv->uncore.fw_rendercount == 0)
+		for_each_fw_domain(domain, dev_priv, id) {
-			dev_priv->uncore.funcs.force_wake_put(dev_priv,
-							FORCEWAKE_RENDER);
-	}
-	if (FORCEWAKE_MEDIA & fw_engine) {
-		WARN_ON(dev_priv->uncore.fw_mediacount == 0);
-		if (--dev_priv->uncore.fw_mediacount == 0)
-			dev_priv->uncore.funcs.force_wake_put(dev_priv,
-							FORCEWAKE_MEDIA);
-	}
-	if (FORCEWAKE_BLITTER & fw_engine) {
-		WARN_ON(dev_priv->uncore.fw_blittercount == 0);
+			if (del_timer_sync(&domain->timer) == 0)
-		if (--dev_priv->uncore.fw_blittercount == 0)
-			dev_priv->uncore.funcs.force_wake_put(dev_priv,
+				continue;
 							FORCEWAKE_BLITTER);
-	}
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-}
+			intel_uncore_fw_release_timer((unsigned long)domain);
+		}
-static void gen6_force_wake_timer(unsigned long arg)
+		spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-{
-	struct drm_i915_private *dev_priv = (void *)arg;
-	unsigned long irqflags;
-	assert_device_not_suspended(dev_priv);
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-	WARN_ON(!dev_priv->uncore.forcewake_count);
+		for_each_fw_domain(domain, dev_priv, id) {
-	if (--dev_priv->uncore.forcewake_count == 0)
-		dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-	intel_runtime_pm_put(dev_priv);
+//           if (timer_pending(&domain->timer))
 //				active_domains |= (1 << id);
-void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned long irqflags;
-	if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
-		gen6_force_wake_timer((unsigned long)dev_priv);
-	/* Hold uncore.lock across reset to prevent any register access
-	 * with forcewake not set correctly
-	 */
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-	if (IS_VALLEYVIEW(dev))
-		vlv_force_wake_reset(dev_priv);
-	else if (IS_GEN6(dev) || IS_GEN7(dev))
-		__gen6_gt_force_wake_reset(dev_priv);
-	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
-		__gen7_gt_force_wake_mt_reset(dev_priv);
 	if (IS_GEN9(dev))
 		__gen9_gt_force_wake_mt_reset(dev_priv);
 		if (active_domains == 0)
-	if (restore) { /* If reset with a user forcewake, try to restore */
+			break;
-		unsigned fw = 0;
-		if (IS_VALLEYVIEW(dev)) {
+		if (--retry_count == 0) {
+			DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
+			break;
+		}
 			if (dev_priv->uncore.fw_rendercount)
-				fw |= FORCEWAKE_RENDER;
+		spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+        change_task();
-			if (dev_priv->uncore.fw_mediacount)
 				fw |= FORCEWAKE_MEDIA;
 		} else if (IS_GEN9(dev)) {
-			if (dev_priv->uncore.fw_rendercount)
+	WARN_ON(active_domains);
-				fw |= FORCEWAKE_RENDER;
-			if (dev_priv->uncore.fw_mediacount)
-				fw |= FORCEWAKE_MEDIA;
+	for_each_fw_domain(domain, dev_priv, id)
 		if (domain->wake_count)
-			if (dev_priv->uncore.fw_blittercount)
+			fw |= 1 << id;
 				fw |= FORCEWAKE_BLITTER;
-		} else {
+	if (fw)
-			if (dev_priv->uncore.forcewake_count)
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 				fw = FORCEWAKE_ALL;
 	fw_domains_reset(dev_priv, FORCEWAKE_ALL);
+	if (restore) { /* If reset with a user forcewake, try to restore */
+		if (fw)
+			dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
+		if (IS_GEN6(dev) || IS_GEN7(dev))
+			dev_priv->uncore.fifo_count =
+				fifo_free_entries(dev_priv);
+	}
-		if (fw)
+	if (!restore)
-			dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
+		assert_forcewakes_inactive(dev_priv);
-		if (IS_GEN6(dev) || IS_GEN7(dev))
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+static void intel_uncore_ellc_detect(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
+	     INTEL_INFO(dev)->gen >= 9) &&
-			dev_priv->uncore.fifo_count =
+	    (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
-				__raw_i915_read32(dev_priv, GTFIFOCTL) &
+		/* The docs do not explain exactly how the calculation can be
-				GT_FIFO_FREE_ENTRIES_MASK;
+		 * made. It is somewhat guessable, but for now, it's always
 		 * 128MB.
+{
 	/* BIOS often leaves RC6 enabled, but disable it for hw init */
 	intel_disable_gt_powersave(dev);
+}
-/*
- * Generally this is called implicitly by the register read function. However,
- * if some sequence requires the GT to not power down then this function should
- * be called at the beginning of the sequence followed by a call to
+static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
- * gen6_gt_force_wake_put() at the end of the sequence.
- */
-void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
+					 enum forcewake_domains fw_domains)
+{
-{
+	struct intel_uncore_forcewake_domain *domain;
-	unsigned long irqflags;
+	enum forcewake_domain_id id;
 	if (!dev_priv->uncore.funcs.force_wake_get)
+		return;
-		return;
+	fw_domains &= dev_priv->uncore.fw_domains;
+	for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
+		if (domain->wake_count++)
-	intel_runtime_pm_get(dev_priv);
+			fw_domains &= ~(1 << id);
+	}
+	if (fw_domains)
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
+}
+/**
+ * intel_uncore_forcewake_get - grab forcewake domain references
+ * @dev_priv: i915 device instance
+ * @fw_domains: forcewake domains to get reference on
+ *
+ * This function can be used get GT's forcewake domain references.
+ * Normal register access will handle the forcewake domains automatically.
+ * However if some sequence requires the GT to not power down a particular
+ * forcewake domains this function should be called at the beginning of the
+ * sequence. And subsequently the reference should be dropped by symmetric
+ * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
+ * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
+ */
+void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
-	/* Redirect to Gen9 specific routine */
+				enum forcewake_domains fw_domains)
+{
-	if (IS_GEN9(dev_priv->dev))
+	unsigned long irqflags;
 		return gen9_force_wake_get(dev_priv, fw_engine);
-	/* Redirect to VLV specific routine */
+	if (!dev_priv->uncore.funcs.force_wake_get)
-	if (IS_VALLEYVIEW(dev_priv->dev))
+		return;
 		return vlv_force_wake_get(dev_priv, fw_engine);
+	WARN_ON(dev_priv->pm.suspended);
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+	__intel_uncore_forcewake_get(dev_priv, fw_domains);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
-	if (dev_priv->uncore.forcewake_count++ == 0)
+/**
-		dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
+ * intel_uncore_forcewake_get__locked - grab forcewake domain references
+ * @dev_priv: i915 device instance
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+ * @fw_domains: forcewake domains to get reference on
-}
+ *
-/*
+ * See intel_uncore_forcewake_get(). This variant places the onus
- * see gen6_gt_force_wake_get()
+ * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
- */
-void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
-{
+ */
-	unsigned long irqflags;
-	bool delayed = false;
+void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
+					enum forcewake_domains fw_domains)
-	if (!dev_priv->uncore.funcs.force_wake_put)
-		return;
+{
-	/* Redirect to Gen9 specific routine */
+	assert_spin_locked(&dev_priv->uncore.lock);
+	if (!dev_priv->uncore.funcs.force_wake_get)
+		return;
-	if (IS_GEN9(dev_priv->dev)) {
+	__intel_uncore_forcewake_get(dev_priv, fw_domains);
-		gen9_force_wake_put(dev_priv, fw_engine);
+}
-		goto out;
+static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
+					 enum forcewake_domains fw_domains)
-	}
+{
+	struct intel_uncore_forcewake_domain *domain;
+	enum forcewake_domain_id id;
-	/* Redirect to VLV specific routine */
-	if (IS_VALLEYVIEW(dev_priv->dev)) {
+	if (!dev_priv->uncore.funcs.force_wake_put)
-		vlv_force_wake_put(dev_priv, fw_engine);
+		return;
+	fw_domains &= dev_priv->uncore.fw_domains;
+	for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
+		if (WARN_ON(domain->wake_count == 0))
+			continue;
+		if (--domain->wake_count)
+			continue;
+		domain->wake_count++;
+		fw_domain_arm_timer(domain);
+	}
+}
+/**
+ * intel_uncore_forcewake_put - release a forcewake domain reference
+ * @dev_priv: i915 device instance
+ * @fw_domains: forcewake domains to put references
+ *
-		goto out;
+ * This function drops the device-level forcewakes for specified
+ * domains obtained by intel_uncore_forcewake_get().
-	}
+ */
+void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
+				enum forcewake_domains fw_domains)
+{
+	unsigned long irqflags;
+	if (!dev_priv->uncore.funcs.force_wake_put)
+		return;
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+	__intel_uncore_forcewake_put(dev_priv, fw_domains);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+/**
+ * intel_uncore_forcewake_put__locked - grab forcewake domain references
+ * @dev_priv: i915 device instance
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+ * @fw_domains: forcewake domains to get reference on
-	WARN_ON(!dev_priv->uncore.forcewake_count);
+ *
  * See intel_uncore_forcewake_put(). This variant places the onus
+ * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
+ */
+void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
-	if (--dev_priv->uncore.forcewake_count == 0) {
+					enum forcewake_domains fw_domains)
 		dev_priv->uncore.forcewake_count++;
+	assert_spin_locked(&dev_priv->uncore.lock);
-		delayed = true;
-//       mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
+	if (!dev_priv->uncore.funcs.force_wake_put)
-//                GetTimerTicks() + 1);
+		return;
-	}
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+	__intel_uncore_forcewake_put(dev_priv, fw_domains);
+}
 out:
 	 REG_RANGE((reg), 0x22000, 0x24000) || \
 	 REG_RANGE((reg), 0x30000, 0x40000))
 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 	(REG_RANGE((reg), 0x2000, 0x4000) || \
-	 REG_RANGE((reg), 0x5000, 0x8000) || \
+	 REG_RANGE((reg), 0x5200, 0x8000) || \
 	 REG_RANGE((reg), 0x8300, 0x8500) || \
-	 REG_RANGE((reg), 0xB000, 0xC000) || \
+	 REG_RANGE((reg), 0xB000, 0xB480) || \
 	 REG_RANGE((reg), 0xE000, 0xE800))
 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 	(REG_RANGE((reg), 0x8800, 0x8900) || \
 	 REG_RANGE((reg), 0xD000, 0xD800) || \
 	 REG_RANGE((reg), 0x12000, 0x14000) || \
 	 REG_RANGE((reg), 0x1A000, 0x1C000) || \
 	 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
-	 REG_RANGE((reg), 0x30000, 0x40000))
+	 REG_RANGE((reg), 0x30000, 0x38000))
 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 	(REG_RANGE((reg), 0x4000, 0x5000) || \
-	 REG_RANGE((reg), 0x8000, 0x8300) || \
-	 REG_RANGE((reg), 0x8500, 0x8600) || \
-	 REG_RANGE((reg), 0x9000, 0xB000) || \
-	 REG_RANGE((reg), 0xC000, 0xC800) || \
+	 REG_RANGE((reg), 0x8000, 0x8300) || \
-	 REG_RANGE((reg), 0xF000, 0x10000) || \
+	 REG_RANGE((reg), 0x8500, 0x8600) || \
-	 REG_RANGE((reg), 0x14000, 0x14400) || \
+	 REG_RANGE((reg), 0x9000, 0xB000) || \
-	 REG_RANGE((reg), 0x22000, 0x24000))
+	 REG_RANGE((reg), 0xF000, 0x10000))
 	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 		WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 		     when, op, reg);
+		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
-		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+		i915.mmio_debug--; /* Only report the first N failures */
+	}
+}
 static void
+hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
+{
-hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
+	static bool mmio_debug_once = true;
-	if (i915.mmio_debug)
+	if (i915.mmio_debug || !mmio_debug_once)
+		return;
-		return;
+	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 		DRM_DEBUG("Unclaimed register detected, "
+			  "enabling oneshot unclaimed register reporting. "
-	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
+			  "Please use i915.mmio_debug=N for more information.\n");
-		DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
+		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
-		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+		i915.mmio_debug = mmio_debug_once--;
-	}
+	}
+}
-#define REG_READ_HEADER(x) \
-	unsigned long irqflags; \
-	u##x val = 0; \
-	assert_device_not_suspended(dev_priv); \
+#define GEN2_READ_HEADER(x) \
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
+	u##x val = 0; \
+	assert_device_not_suspended(dev_priv);
 #define REG_READ_FOOTER \
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
+#define GEN2_READ_FOOTER \
 	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 	return val
-#define __gen4_read(x) \
+#define __gen2_read(x) \
 static u##x \
-gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-	REG_READ_HEADER(x); \
+	GEN2_READ_HEADER(x); \
 	val = __raw_i915_read##x(dev_priv, reg); \
-	REG_READ_FOOTER; \
+	GEN2_READ_FOOTER; \
+}
+#define __gen5_read(x) \
+static u##x \
+gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+	GEN2_READ_HEADER(x); \
+	ilk_dummy_write(dev_priv); \
+	val = __raw_i915_read##x(dev_priv, reg); \
+	GEN2_READ_FOOTER; \
+}
+__gen5_read(8)
+__gen5_read(16)
+__gen5_read(32)
+__gen5_read(64)
+__gen2_read(8)
+__gen2_read(16)
+__gen2_read(32)
+__gen2_read(64)
+#undef __gen5_read
+#undef __gen2_read
+#undef GEN2_READ_FOOTER
+#undef GEN2_READ_HEADER
+#define GEN6_READ_HEADER(x) \
+	unsigned long irqflags; \
+	u##x val = 0; \
+	assert_device_not_suspended(dev_priv); \
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
+#define GEN6_READ_FOOTER \
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
+	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
+	return val
+static inline void __force_wake_get(struct drm_i915_private *dev_priv,
+				    enum forcewake_domains fw_domains)
+{
+	struct intel_uncore_forcewake_domain *domain;
+	enum forcewake_domain_id id;
+	if (WARN_ON(!fw_domains))
+		return;
+	/* Ideally GCC would be constant-fold and eliminate this loop */
+	for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
+		if (domain->wake_count) {
+			fw_domains &= ~(1 << id);
+			continue;
+		}
+		domain->wake_count++;
+		fw_domain_arm_timer(domain);
+	}
+	if (fw_domains)
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
+}
 #define __gen5_read(x) \
-static u##x \
+#define __vgpu_read(x) \
-gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+static u##x \
-	REG_READ_HEADER(x); \
+vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-		ilk_dummy_write(dev_priv); \
+	GEN6_READ_HEADER(x); \
 	val = __raw_i915_read##x(dev_priv, reg); \
-	REG_READ_FOOTER; \
-}
+	GEN6_READ_FOOTER; \
-#define __gen6_read(x) \
-static u##x \
+}
-gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-	REG_READ_HEADER(x); \
-	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 	if (dev_priv->uncore.forcewake_count == 0 && \
-	    NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
-			dev_priv->uncore.funcs.force_wake_get(dev_priv, \
+#define __gen6_read(x) \
-							FORCEWAKE_ALL); \
+static u##x \
-		val = __raw_i915_read##x(dev_priv, reg); \
+gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-			dev_priv->uncore.funcs.force_wake_put(dev_priv, \
+	GEN6_READ_HEADER(x); \
-							FORCEWAKE_ALL); \
+	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
-	} else { \
+	if (NEEDS_FORCE_WAKE(reg)) \
-		val = __raw_i915_read##x(dev_priv, reg); \
-	} \
+		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
-	hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
+	val = __raw_i915_read##x(dev_priv, reg); \
-	REG_READ_FOOTER; \
-}
+	hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
+	GEN6_READ_FOOTER; \
-#define __vlv_read(x) \
-static u##x \
-vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-	unsigned fwengine = 0; \
-	REG_READ_HEADER(x); \
+}
 	if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) {   \
-		if (dev_priv->uncore.fw_rendercount == 0) \
-		fwengine = FORCEWAKE_RENDER;            \
-	} else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
+#define __vlv_read(x) \
-		if (dev_priv->uncore.fw_mediacount == 0) \
+static u##x \
-		fwengine = FORCEWAKE_MEDIA;             \
+vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-	}                                               \
+	GEN6_READ_HEADER(x); \
-	if (fwengine) \
+	if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
-		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
-		val = __raw_i915_read##x(dev_priv, reg); \
+		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
-	if (fwengine) \
+	else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
-		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
-	REG_READ_FOOTER; \
+		__force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
-}
+	val = __raw_i915_read##x(dev_priv, reg); \
-#define __chv_read(x) \
+	GEN6_READ_FOOTER; \
-static u##x \
+}
-chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-	unsigned fwengine = 0; \
-	REG_READ_HEADER(x); \
-	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+#define __chv_read(x) \
-		if (dev_priv->uncore.fw_rendercount == 0) \
-			fwengine = FORCEWAKE_RENDER; \
-	} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
-		if (dev_priv->uncore.fw_mediacount == 0) \
+static u##x \
-		fwengine = FORCEWAKE_MEDIA;             \
-	} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
-		if (dev_priv->uncore.fw_rendercount == 0) \
+chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-			fwengine |= FORCEWAKE_RENDER; \
+	GEN6_READ_HEADER(x); \
-		if (dev_priv->uncore.fw_mediacount == 0) \
+	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
-			fwengine |= FORCEWAKE_MEDIA; \
+		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
-	}  \
+	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
-	if (fwengine) \
+		__force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
-		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
+	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
+		__force_wake_get(dev_priv, \
-		val = __raw_i915_read##x(dev_priv, reg); \
+				 FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
-	if (fwengine) \
+	val = __raw_i915_read##x(dev_priv, reg); \
-		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
+	GEN6_READ_FOOTER; \
-	REG_READ_FOOTER; \
 }
-#define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)	\
-	 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
+#define SKL_NEEDS_FORCE_WAKE(reg) \
+	 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
-#define __gen9_read(x) \
-static u##x \
-gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+#define __gen9_read(x) \
-	REG_READ_HEADER(x); \
-	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
+static u##x \
-		val = __raw_i915_read##x(dev_priv, reg); \
-	} else { \
-		unsigned fwengine = 0; \
+gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-		if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
-			if (dev_priv->uncore.fw_rendercount == 0) \
+	enum forcewake_domains fw_engine; \
-				fwengine = FORCEWAKE_RENDER; \
-		} else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
+	GEN6_READ_HEADER(x); \
-			if (dev_priv->uncore.fw_mediacount == 0) \
+	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
-				fwengine = FORCEWAKE_MEDIA; \
+	if (!SKL_NEEDS_FORCE_WAKE(reg)) \
-		} else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
-			if (dev_priv->uncore.fw_rendercount == 0) \
+		fw_engine = 0; \
-				fwengine |= FORCEWAKE_RENDER; \
-			if (dev_priv->uncore.fw_mediacount == 0) \
+	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
-				fwengine |= FORCEWAKE_MEDIA; \
+		fw_engine = FORCEWAKE_RENDER; \
+	else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
+		fw_engine = FORCEWAKE_MEDIA; \
+	else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
+		fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
-		} else { \
+	else \
-			if (dev_priv->uncore.fw_blittercount == 0) \
+		fw_engine = FORCEWAKE_BLITTER; \
-				fwengine = FORCEWAKE_BLITTER; \
+	if (fw_engine) \
-		} \
+		__force_wake_get(dev_priv, fw_engine); \
-		if (fwengine) \
+	val = __raw_i915_read##x(dev_priv, reg); \
 __vlv_read(64)
 __gen6_read(8)
 __gen6_read(16)
 __gen6_read(32)
 __gen6_read(64)
-__gen5_read(8)
-__gen5_read(16)
-__gen5_read(32)
-__gen5_read(64)
-__gen4_read(8)
-__gen4_read(16)
-__gen4_read(32)
-__gen4_read(64)
 #undef __gen9_read
 #undef __chv_read
 #undef __vlv_read
-#undef __gen6_read
-#undef __gen5_read
+#undef __gen6_read
-#undef __gen4_read
+#undef __vgpu_read
-#undef REG_READ_FOOTER
+#undef GEN6_READ_FOOTER
-#undef REG_READ_HEADER
+#undef GEN6_READ_HEADER
 #define REG_WRITE_HEADER \
-	unsigned long irqflags; \
+#define GEN2_WRITE_HEADER \
-	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
-	assert_device_not_suspended(dev_priv); \
+	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
+	assert_device_not_suspended(dev_priv); \
 #define REG_WRITE_FOOTER \
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
+#define GEN2_WRITE_FOOTER
-#define __gen4_write(x) \
+#define __gen2_write(x) \
 static void \
-gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
-	REG_WRITE_HEADER; \
+	GEN2_WRITE_HEADER; \
 	__raw_i915_write##x(dev_priv, reg, val); \
-	REG_WRITE_FOOTER; \
+	GEN2_WRITE_FOOTER; \
 }
 #define __gen5_write(x) \
 static void \
 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+	GEN2_WRITE_HEADER; \
+	ilk_dummy_write(dev_priv); \
+	__raw_i915_write##x(dev_priv, reg, val); \
+	GEN2_WRITE_FOOTER; \
+}
+__gen5_write(8)
+__gen5_write(16)
+__gen5_write(32)
+__gen5_write(64)
+__gen2_write(8)
+__gen2_write(16)
+__gen2_write(32)
+__gen2_write(64)
+#undef __gen5_write
+#undef __gen2_write
+#undef GEN2_WRITE_FOOTER
+#undef GEN2_WRITE_HEADER
+#define GEN6_WRITE_HEADER \
+	unsigned long irqflags; \
+	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
-	REG_WRITE_HEADER; \
+	assert_device_not_suspended(dev_priv); \
-	ilk_dummy_write(dev_priv); \
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 	__raw_i915_write##x(dev_priv, reg, val); \
-	REG_WRITE_FOOTER; \
+#define GEN6_WRITE_FOOTER \
-}
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 #define __gen6_write(x) \
 static void \
 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 	u32 __fifo_ret = 0; \
-	REG_WRITE_HEADER; \
+	GEN6_WRITE_HEADER; \
-	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
+	if (NEEDS_FORCE_WAKE(reg)) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 	} \
 	__raw_i915_write##x(dev_priv, reg, val); \
 	if (unlikely(__fifo_ret)) { \
 		gen6_gt_check_fifodbg(dev_priv); \
 	} \
-	REG_WRITE_FOOTER; \
+	GEN6_WRITE_FOOTER; \
 }
 #define __hsw_write(x) \
 static void \
 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 	u32 __fifo_ret = 0; \
-	REG_WRITE_HEADER; \
+	GEN6_WRITE_HEADER; \
-	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
+	if (NEEDS_FORCE_WAKE(reg)) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 	} \
 	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
+	__raw_i915_write##x(dev_priv, reg, val); \
+	if (unlikely(__fifo_ret)) { \
+		gen6_gt_check_fifodbg(dev_priv); \
+	} \
+	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
+	hsw_unclaimed_reg_detect(dev_priv); \
+	GEN6_WRITE_FOOTER; \
+}
 	__raw_i915_write##x(dev_priv, reg, val); \
-	if (unlikely(__fifo_ret)) { \
+#define __vgpu_write(x) \
-		gen6_gt_check_fifodbg(dev_priv); \
+static void vgpu_write##x(struct drm_i915_private *dev_priv, \
-	} \
+			  off_t reg, u##x val, bool trace) { \
+}
 #define __gen8_write(x) \
 static void \
 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
-	REG_WRITE_HEADER; \
+	GEN6_WRITE_HEADER; \
 	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
-	if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
-		if (dev_priv->uncore.forcewake_count == 0) \
-		dev_priv->uncore.funcs.force_wake_get(dev_priv, \
-							FORCEWAKE_ALL); \
+	if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
-	__raw_i915_write##x(dev_priv, reg, val); \
-		if (dev_priv->uncore.forcewake_count == 0) \
-		dev_priv->uncore.funcs.force_wake_put(dev_priv, \
-							FORCEWAKE_ALL); \
-	} else { \
+		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
-		__raw_i915_write##x(dev_priv, reg, val); \
-	} \
+	__raw_i915_write##x(dev_priv, reg, val); \
 	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 	hsw_unclaimed_reg_detect(dev_priv); \
-	REG_WRITE_FOOTER; \
+	GEN6_WRITE_FOOTER; \
+}
 #define __chv_write(x) \
-static void \
-chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+static void \
-	unsigned fwengine = 0; \
+chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
-	REG_WRITE_HEADER; \
+	GEN6_WRITE_HEADER; \
-	if (!shadowed) { \
-		if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+	if (!shadowed) { \
-			if (dev_priv->uncore.fw_rendercount == 0) \
+		if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
-				fwengine = FORCEWAKE_RENDER; \
-		} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+			__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
-			if (dev_priv->uncore.fw_mediacount == 0) \
+		else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
-				fwengine = FORCEWAKE_MEDIA; \
-		} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+			__force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
-			if (dev_priv->uncore.fw_rendercount == 0) \
-				fwengine |= FORCEWAKE_RENDER; \
-			if (dev_priv->uncore.fw_mediacount == 0) \
+		else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
-				fwengine |= FORCEWAKE_MEDIA; \
-		} \
-	} \
-	if (fwengine) \
+			__force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
-		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
-	__raw_i915_write##x(dev_priv, reg, val); \
-	if (fwengine) \
+	} \
-		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
+	__raw_i915_write##x(dev_priv, reg, val); \
-	REG_WRITE_FOOTER; \
+	GEN6_WRITE_FOOTER; \
+}
 #define __gen9_write(x) \
 static void \
 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
+		bool trace) { \
-		bool trace) { \
+	enum forcewake_domains fw_engine; \
-	REG_WRITE_HEADER; \
+	GEN6_WRITE_HEADER; \
-	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
+	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
-			is_gen9_shadowed(dev_priv, reg)) { \
+	if (!SKL_NEEDS_FORCE_WAKE(reg) || \
-		__raw_i915_write##x(dev_priv, reg, val); \
-	} else { \
+	    is_gen9_shadowed(dev_priv, reg)) \
-		unsigned fwengine = 0; \
+		fw_engine = 0; \
-		if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
-			if (dev_priv->uncore.fw_rendercount == 0) \
+	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
-				fwengine = FORCEWAKE_RENDER; \
+		fw_engine = FORCEWAKE_RENDER; \
-		} else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
-			if (dev_priv->uncore.fw_mediacount == 0) \
+	else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
-				fwengine = FORCEWAKE_MEDIA; \
+		fw_engine = FORCEWAKE_MEDIA; \
-		} else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
-			if (dev_priv->uncore.fw_rendercount == 0) \
+	else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
-				fwengine |= FORCEWAKE_RENDER; \
-			if (dev_priv->uncore.fw_mediacount == 0) \
-				fwengine |= FORCEWAKE_MEDIA; \
+		fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
-		} else { \
-			if (dev_priv->uncore.fw_blittercount == 0) \
+	else \
-				fwengine = FORCEWAKE_BLITTER; \
-		} \
+		fw_engine = FORCEWAKE_BLITTER; \
-		if (fwengine) \
+	if (fw_engine) \
-			dev_priv->uncore.funcs.force_wake_get(dev_priv, \
-					fwengine); \
+		__force_wake_get(dev_priv, fw_engine); \
-		__raw_i915_write##x(dev_priv, reg, val); \
-		if (fwengine) \
+	__raw_i915_write##x(dev_priv, reg, val); \
-			dev_priv->uncore.funcs.force_wake_put(dev_priv, \
+	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
-					fwengine); \
-	} \
+	hsw_unclaimed_reg_detect(dev_priv); \
-	REG_WRITE_FOOTER; \
+	GEN6_WRITE_FOOTER; \
+}
 __gen9_write(8)
 __hsw_write(64)
 __gen6_write(8)
 __gen6_write(16)
 __gen6_write(32)
 __gen6_write(64)
-__gen5_write(8)
+__vgpu_write(8)
-__gen5_write(16)
-__gen5_write(32)
-__gen5_write(64)
-__gen4_write(8)
-__gen4_write(16)
+__vgpu_write(16)
-__gen4_write(32)
+__vgpu_write(32)
-__gen4_write(64)
+__vgpu_write(64)
 #undef __gen9_write
 #undef __chv_write
 #undef __gen8_write
 #undef __hsw_write
-#undef __gen6_write
-#undef __gen5_write
+#undef __gen6_write
-#undef __gen4_write
+#undef __vgpu_write
-#undef REG_WRITE_FOOTER
+#undef GEN6_WRITE_FOOTER
-#undef REG_WRITE_HEADER
+#undef GEN6_WRITE_HEADER
 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
 do { \
 	dev_priv->uncore.funcs.mmio_readw = x##_read16; \
 	dev_priv->uncore.funcs.mmio_readl = x##_read32; \
 	dev_priv->uncore.funcs.mmio_readq = x##_read64; \
 } while (0)
+static void fw_domain_init(struct drm_i915_private *dev_priv,
+			   enum forcewake_domain_id domain_id,
-void intel_uncore_init(struct drm_device *dev)
+			   u32 reg_set, u32 reg_ack)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_uncore_forcewake_domain *d;
+	if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
+		return;
+	d = &dev_priv->uncore.fw_domain[domain_id];
+	WARN_ON(d->wake_count);
+	d->wake_count = 0;
+	d->reg_set = reg_set;
+	d->reg_ack = reg_ack;
+	if (IS_GEN6(dev_priv)) {
+		d->val_reset = 0;
+		d->val_set = FORCEWAKE_KERNEL;
+		d->val_clear = 0;
+	} else {
+		/* WaRsClearFWBitsAtReset:bdw,skl */
+		d->val_reset = _MASKED_BIT_DISABLE(0xffff);
+		d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
+		d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
+	}
+	if (IS_VALLEYVIEW(dev_priv))
+		d->reg_post = FORCEWAKE_ACK_VLV;
+	else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
+		d->reg_post = ECOBUS;
+	else
+		d->reg_post = 0;
+	d->i915 = dev_priv;
+	d->id = domain_id;
-	setup_timer(&dev_priv->uncore.force_wake_timer,
+	setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
+	dev_priv->uncore.fw_domains |= (1 << domain_id);
+	fw_domain_reset(d);
+}
+static void intel_uncore_fw_domains_init(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
 		    gen6_force_wake_timer, (unsigned long)dev_priv);
+	if (INTEL_INFO(dev_priv->dev)->gen <= 5)
-	__intel_uncore_early_sanitize(dev, false);
+		return;
+	if (IS_GEN9(dev)) {
+		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
+		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
+		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+			       FORCEWAKE_RENDER_GEN9,
+			       FORCEWAKE_ACK_RENDER_GEN9);
+		fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
 			       FORCEWAKE_BLITTER_GEN9,
-	if (IS_GEN9(dev)) {
+			       FORCEWAKE_ACK_BLITTER_GEN9);
+		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
+			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
+	} else if (IS_VALLEYVIEW(dev)) {
+		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
-		dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get;
+		if (!IS_CHERRYVIEW(dev))
+			dev_priv->uncore.funcs.force_wake_put =
+				fw_domains_put_with_fifo;
+		else
+			dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
-		dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put;
+		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
-	} else if (IS_VALLEYVIEW(dev)) {
+			       FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
+		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
-		dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
+			       FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
+	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+		dev_priv->uncore.funcs.force_wake_get =
-		dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
+			fw_domains_get_with_thread_status;
-	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
-		dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
+		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
 		 * force_wake_mt_get will not wake the device and the
 		 * ECOBUS read will return zero. Which will be
 		 * (correctly) interpreted by the test below as MT
 		 * forcewake being disabled.
 		 */
+		dev_priv->uncore.funcs.force_wake_get =
+			fw_domains_get_with_thread_status;
+		dev_priv->uncore.funcs.force_wake_put =
+			fw_domains_put_with_fifo;
+		/* We need to init first for ECOBUS access and then
+		 * determine later if we want to reinit, in case of MT access is
+		 * not working. In this stage we don't know which flavour this
+		 * ivb is, so it is better to reset also the gen6 fw registers
+		 * before the ecobus check.
+		 */
+		__raw_i915_write32(dev_priv, FORCEWAKE, 0);
+		__raw_posting_read(dev_priv, ECOBUS);
+		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+			       FORCEWAKE_MT, FORCEWAKE_MT_ACK);
 		mutex_lock(&dev->struct_mutex);
-		__gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
+		fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
 		ecobus = __raw_i915_read32(dev_priv, ECOBUS);
-		__gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
+		fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
 		mutex_unlock(&dev->struct_mutex);
-		if (ecobus & FORCEWAKE_MT_ENABLE) {
-			dev_priv->uncore.funcs.force_wake_get =
-				__gen7_gt_force_wake_mt_get;
-			dev_priv->uncore.funcs.force_wake_put =
-				__gen7_gt_force_wake_mt_put;
-		} else {
+		if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
 			DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
 			DRM_INFO("when using vblank-synced partial screen updates.\n");
-			dev_priv->uncore.funcs.force_wake_get =
+			fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
-				__gen6_gt_force_wake_get;
-			dev_priv->uncore.funcs.force_wake_put =
-				__gen6_gt_force_wake_put;
+				       FORCEWAKE, FORCEWAKE_ACK);
+		}
 	} else if (IS_GEN6(dev)) {
 		dev_priv->uncore.funcs.force_wake_get =
-			__gen6_gt_force_wake_get;
+			fw_domains_get_with_thread_status;
 		dev_priv->uncore.funcs.force_wake_put =
+			fw_domains_put_with_fifo;
+		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+			       FORCEWAKE, FORCEWAKE_ACK);
+	}
+	/* All future platforms are expected to require complex power gating */
-			__gen6_gt_force_wake_put;
+	WARN_ON(dev_priv->uncore.fw_domains == 0);
+}
+void intel_uncore_init(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	i915_check_vgpu(dev);
+	intel_uncore_ellc_detect(dev);
+	intel_uncore_fw_domains_init(dev);
 	__intel_uncore_early_sanitize(dev, false);
-	switch (INTEL_INFO(dev)->gen) {
-	default:
-		WARN_ON(1);
+	switch (INTEL_INFO(dev)->gen) {
-		return;
+	default:
 	case 9:
 		ASSIGN_WRITE_MMIO_VFUNCS(gen9);
 		ASSIGN_READ_MMIO_VFUNCS(gen9);
 		ASSIGN_READ_MMIO_VFUNCS(gen5);
 		break;
 	case 4:
 	case 3:
 	case 2:
-		ASSIGN_WRITE_MMIO_VFUNCS(gen4);
+		ASSIGN_WRITE_MMIO_VFUNCS(gen2);
-		ASSIGN_READ_MMIO_VFUNCS(gen4);
+		ASSIGN_READ_MMIO_VFUNCS(gen2);
 		break;
+	}
+	if (intel_vgpu_active(dev)) {
+		ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
+		ASSIGN_READ_MMIO_VFUNCS(vgpu);
+	}
 	i915_check_and_clear_faults(dev);
+}
 #undef ASSIGN_WRITE_MMIO_VFUNCS
 			void *data, struct drm_file *file)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_reg_read *reg = data;
 	struct register_whitelist const *entry = whitelist;
+	unsigned size;
+	u64 offset;
 	int i, ret = 0;
 	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
-		if (entry->offset == reg->offset &&
+		if (entry->offset == (reg->offset & -entry->size) &&
 		    (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
 			break;
+	}
+	if (i == ARRAY_SIZE(whitelist))
+		return -EINVAL;
+	/* We use the low bits to encode extra flags as the register should
+	 * be naturally aligned (and those that are not so aligned merely
+	 * limit the available flags for that register).
+	 */
+	offset = entry->offset;
+	size = entry->size;
+	size |= reg->offset ^ offset;
-	if (i == ARRAY_SIZE(whitelist))
+	intel_runtime_pm_get(dev_priv);
+	switch (size) {
-		return -EINVAL;
+	case 8 | 1:
+		reg->val = I915_READ64_2x32(offset, offset+4);
-	switch (entry->size) {
+		break;
 	case 8:
-		reg->val = I915_READ64(reg->offset);
+		reg->val = I915_READ64(offset);
 		break;
 	case 4:
-		reg->val = I915_READ(reg->offset);
+		reg->val = I915_READ(offset);
 		break;
 	case 2:
-		reg->val = I915_READ16(reg->offset);
+		reg->val = I915_READ16(offset);
 		break;
 	case 1:
-		reg->val = I915_READ8(reg->offset);
-		break;
+		reg->val = I915_READ8(offset);
-	default:
+		break;
-		WARN_ON(1);
+	default:
 		ret = -EINVAL;
+		goto out;
 		goto out;
 out:
-out:
+	intel_runtime_pm_put(dev_priv);
 static int ironlake_do_reset(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
-	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
+	I915_WRITE(ILK_GDSR,
 		   ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
-	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
+	ret = wait_for((I915_READ(ILK_GDSR) &
 			ILK_GRDOM_RESET_ENABLE) == 0, 500);
 	if (ret)
 		return ret;
-	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
+	I915_WRITE(ILK_GDSR,
 		   ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
-	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
+	ret = wait_for((I915_READ(ILK_GDSR) &
 			ILK_GRDOM_RESET_ENABLE) == 0, 500);
 	if (ret)
 		return ret;
-	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
+	I915_WRITE(ILK_GDSR, 0);
 	intel_uncore_forcewake_reset(dev, true);
 	return ret;
 }
+static int wait_for_register(struct drm_i915_private *dev_priv,
+			     const u32 reg,
+			     const u32 mask,
 			     const u32 value,
+			     const unsigned long timeout_ms)
+{
+	return wait_for((I915_READ(reg) & mask) == value, timeout_ms);
+}
+static int gen8_do_reset(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_engine_cs *engine;
+	int i;
+	for_each_ring(engine, dev_priv, i) {
+		I915_WRITE(RING_RESET_CTL(engine->mmio_base),
-int intel_gpu_reset(struct drm_device *dev)
+			   _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
+		if (wait_for_register(dev_priv,
+				      RING_RESET_CTL(engine->mmio_base),
+				      RESET_CTL_READY_TO_RESET,
+				      RESET_CTL_READY_TO_RESET,
+)) {
+			DRM_ERROR("%s: reset request timeout\n", engine->name);
+			goto not_ready;
+		}
+	}
+	return gen6_do_reset(dev);
+not_ready:
+	for_each_ring(engine, dev_priv, i)
+		I915_WRITE(RING_RESET_CTL(engine->mmio_base),
+			   _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
+	return -EIO;
+}
+static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *)
+{
+	if (!i915.reset)
+		return NULL;
+	if (INTEL_INFO(dev)->gen >= 8)
+		return gen8_do_reset;
-	if (INTEL_INFO(dev)->gen >= 6)
+	else if (INTEL_INFO(dev)->gen >= 6)
-		return gen6_do_reset(dev);
+		return gen6_do_reset;
 	else if (IS_GEN5(dev))
-		return ironlake_do_reset(dev);
+		return ironlake_do_reset;
 	else if (IS_G4X(dev))
-			return g4x_do_reset(dev);
+		return g4x_do_reset;
 	else if (IS_G33(dev))
-		return g33_do_reset(dev);
+		return g33_do_reset;
 	else if (INTEL_INFO(dev)->gen >= 3)
+		return i915_do_reset;
+	else
+		return NULL;
+}
+int intel_gpu_reset(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int (*reset)(struct drm_device *);
+	int ret;
-		return i915_do_reset(dev);
+	reset = intel_get_gpu_reset(dev);
+	if (reset == NULL)
+		return -ENODEV;
+	/* If the power well sleeps during the reset, the reset
+	 * request may be dropped and never completes (causing -EIO).
+	 */
+	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+	ret = reset(dev);
+	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+	return ret;
+}
+bool intel_has_gpu_reset(struct drm_device *dev)
 		else
-		return -ENODEV;
+	return intel_get_gpu_reset(dev) != NULL;
+}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_uncore.c – Rev 5354 → 6084