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| Rev 5060 | Rev 5354 | ||
|---|---|---|---|
| Line 41... | Line 41... | ||
| 41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) |
41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) |
| Line 42... | Line 42... | ||
| 42 | 42 | ||
| 43 | static void |
43 | static void |
| 44 | assert_device_not_suspended(struct drm_i915_private *dev_priv) |
44 | assert_device_not_suspended(struct drm_i915_private *dev_priv) |
| 45 | { |
45 | { |
| 46 | WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, |
46 | WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, |
| 47 | "Device suspended\n"); |
47 | "Device suspended\n"); |
| Line 48... | Line 48... | ||
| 48 | } |
48 | } |
| 49 | 49 | ||
| 50 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
- | |
| 51 | { |
- | |
| 52 | u32 gt_thread_status_mask; |
- | |
| 53 | - | ||
| 54 | if (IS_HASWELL(dev_priv->dev)) |
- | |
| 55 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
- | |
| 56 | else |
- | |
| 57 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
50 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
| 58 | 51 | { |
|
| 59 | /* w/a for a sporadic read returning 0 by waiting for the GT |
52 | /* w/a for a sporadic read returning 0 by waiting for the GT |
| 60 | * thread to wake up. |
53 | * thread to wake up. |
| - | 54 | */ |
|
| 61 | */ |
55 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & |
| 62 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
56 | GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) |
| Line 63... | Line 57... | ||
| 63 | DRM_ERROR("GT thread status wait timed out\n"); |
57 | DRM_ERROR("GT thread status wait timed out\n"); |
| 64 | } |
58 | } |
| Line 99... | Line 93... | ||
| 99 | static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
93 | static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
| 100 | int fw_engine) |
94 | int fw_engine) |
| 101 | { |
95 | { |
| 102 | u32 forcewake_ack; |
96 | u32 forcewake_ack; |
| Line 103... | Line 97... | ||
| 103 | 97 | ||
| 104 | if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) |
98 | if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev)) |
| 105 | forcewake_ack = FORCEWAKE_ACK_HSW; |
99 | forcewake_ack = FORCEWAKE_ACK_HSW; |
| 106 | else |
100 | else |
| Line 107... | Line 101... | ||
| 107 | forcewake_ack = FORCEWAKE_MT_ACK; |
101 | forcewake_ack = FORCEWAKE_MT_ACK; |
| Line 118... | Line 112... | ||
| 118 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
112 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
| 119 | FORCEWAKE_ACK_TIMEOUT_MS)) |
113 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 120 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
114 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| Line 121... | Line 115... | ||
| 121 | 115 | ||
| 122 | /* WaRsForcewakeWaitTC0:ivb,hsw */ |
- | |
| 123 | if (INTEL_INFO(dev_priv->dev)->gen < 8) |
116 | /* WaRsForcewakeWaitTC0:ivb,hsw */ |
| 124 | __gen6_gt_wait_for_thread_c0(dev_priv); |
117 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| Line 125... | Line 118... | ||
| 125 | } |
118 | } |
| 126 | 119 | ||
| Line 227... | Line 220... | ||
| 227 | FORCEWAKE_ACK_MEDIA_VLV) & |
220 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 228 | FORCEWAKE_KERNEL), |
221 | FORCEWAKE_KERNEL), |
| 229 | FORCEWAKE_ACK_TIMEOUT_MS)) |
222 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 230 | DRM_ERROR("Timed out: waiting for media to ack.\n"); |
223 | DRM_ERROR("Timed out: waiting for media to ack.\n"); |
| 231 | } |
224 | } |
| 232 | - | ||
| 233 | /* WaRsForcewakeWaitTC0:vlv */ |
- | |
| 234 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
- | |
| 235 | __gen6_gt_wait_for_thread_c0(dev_priv); |
- | |
| 236 | } |
225 | } |
| Line 237... | Line 226... | ||
| 237 | 226 | ||
| 238 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
227 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
| 239 | int fw_engine) |
228 | int fw_engine) |
| Line 297... | Line 286... | ||
| 297 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); |
286 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); |
| Line 298... | Line 287... | ||
| 298 | 287 | ||
| 299 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
288 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| Line -... | Line 289... | ||
| - | 289 | } |
|
| - | 290 | ||
| - | 291 | static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
|
| - | 292 | { |
|
| - | 293 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, |
|
| - | 294 | _MASKED_BIT_DISABLE(0xffff)); |
|
| - | 295 | ||
| - | 296 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, |
|
| - | 297 | _MASKED_BIT_DISABLE(0xffff)); |
|
| - | 298 | ||
| - | 299 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, |
|
| - | 300 | _MASKED_BIT_DISABLE(0xffff)); |
|
| - | 301 | } |
|
| - | 302 | ||
| - | 303 | static void |
|
| - | 304 | __gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
|
| - | 305 | { |
|
| - | 306 | /* Check for Render Engine */ |
|
| - | 307 | if (FORCEWAKE_RENDER & fw_engine) { |
|
| - | 308 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
|
| - | 309 | FORCEWAKE_ACK_RENDER_GEN9) & |
|
| - | 310 | FORCEWAKE_KERNEL) == 0, |
|
| - | 311 | FORCEWAKE_ACK_TIMEOUT_MS)) |
|
| - | 312 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); |
|
| - | 313 | ||
| - | 314 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, |
|
| - | 315 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
|
| - | 316 | ||
| - | 317 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
|
| - | 318 | FORCEWAKE_ACK_RENDER_GEN9) & |
|
| - | 319 | FORCEWAKE_KERNEL), |
|
| - | 320 | FORCEWAKE_ACK_TIMEOUT_MS)) |
|
| - | 321 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); |
|
| - | 322 | } |
|
| - | 323 | ||
| - | 324 | /* Check for Media Engine */ |
|
| - | 325 | if (FORCEWAKE_MEDIA & fw_engine) { |
|
| - | 326 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
|
| - | 327 | FORCEWAKE_ACK_MEDIA_GEN9) & |
|
| - | 328 | FORCEWAKE_KERNEL) == 0, |
|
| - | 329 | FORCEWAKE_ACK_TIMEOUT_MS)) |
|
| - | 330 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); |
|
| - | 331 | ||
| - | 332 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, |
|
| - | 333 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
|
| - | 334 | ||
| - | 335 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
|
| - | 336 | FORCEWAKE_ACK_MEDIA_GEN9) & |
|
| - | 337 | FORCEWAKE_KERNEL), |
|
| - | 338 | FORCEWAKE_ACK_TIMEOUT_MS)) |
|
| - | 339 | DRM_ERROR("Timed out: waiting for Media to ack.\n"); |
|
| - | 340 | } |
|
| - | 341 | ||
| - | 342 | /* Check for Blitter Engine */ |
|
| - | 343 | if (FORCEWAKE_BLITTER & fw_engine) { |
|
| - | 344 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
|
| - | 345 | FORCEWAKE_ACK_BLITTER_GEN9) & |
|
| - | 346 | FORCEWAKE_KERNEL) == 0, |
|
| - | 347 | FORCEWAKE_ACK_TIMEOUT_MS)) |
|
| - | 348 | DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n"); |
|
| - | 349 | ||
| - | 350 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, |
|
| - | 351 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
|
| - | 352 | ||
| - | 353 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
|
| - | 354 | FORCEWAKE_ACK_BLITTER_GEN9) & |
|
| - | 355 | FORCEWAKE_KERNEL), |
|
| - | 356 | FORCEWAKE_ACK_TIMEOUT_MS)) |
|
| - | 357 | DRM_ERROR("Timed out: waiting for Blitter to ack.\n"); |
|
| - | 358 | } |
|
| - | 359 | } |
|
| - | 360 | ||
| - | 361 | static void |
|
| - | 362 | __gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
|
| - | 363 | { |
|
| - | 364 | /* Check for Render Engine */ |
|
| - | 365 | if (FORCEWAKE_RENDER & fw_engine) |
|
| - | 366 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, |
|
| - | 367 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
|
| - | 368 | ||
| - | 369 | /* Check for Media Engine */ |
|
| - | 370 | if (FORCEWAKE_MEDIA & fw_engine) |
|
| - | 371 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, |
|
| - | 372 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
|
| - | 373 | ||
| - | 374 | /* Check for Blitter Engine */ |
|
| - | 375 | if (FORCEWAKE_BLITTER & fw_engine) |
|
| - | 376 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, |
|
| - | 377 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
|
| - | 378 | } |
|
| - | 379 | ||
| - | 380 | static void |
|
| - | 381 | gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
|
| - | 382 | { |
|
| - | 383 | unsigned long irqflags; |
|
| - | 384 | ||
| - | 385 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
|
| - | 386 | ||
| - | 387 | if (FORCEWAKE_RENDER & fw_engine) { |
|
| - | 388 | if (dev_priv->uncore.fw_rendercount++ == 0) |
|
| - | 389 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
|
| - | 390 | FORCEWAKE_RENDER); |
|
| - | 391 | } |
|
| - | 392 | ||
| - | 393 | if (FORCEWAKE_MEDIA & fw_engine) { |
|
| - | 394 | if (dev_priv->uncore.fw_mediacount++ == 0) |
|
| - | 395 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
|
| - | 396 | FORCEWAKE_MEDIA); |
|
| - | 397 | } |
|
| - | 398 | ||
| - | 399 | if (FORCEWAKE_BLITTER & fw_engine) { |
|
| - | 400 | if (dev_priv->uncore.fw_blittercount++ == 0) |
|
| - | 401 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
|
| - | 402 | FORCEWAKE_BLITTER); |
|
| - | 403 | } |
|
| - | 404 | ||
| - | 405 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
|
| - | 406 | } |
|
| - | 407 | ||
| - | 408 | static void |
|
| - | 409 | gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
|
| - | 410 | { |
|
| - | 411 | unsigned long irqflags; |
|
| - | 412 | ||
| - | 413 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
|
| - | 414 | ||
| - | 415 | if (FORCEWAKE_RENDER & fw_engine) { |
|
| - | 416 | WARN_ON(dev_priv->uncore.fw_rendercount == 0); |
|
| - | 417 | if (--dev_priv->uncore.fw_rendercount == 0) |
|
| - | 418 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
|
| - | 419 | FORCEWAKE_RENDER); |
|
| - | 420 | } |
|
| - | 421 | ||
| - | 422 | if (FORCEWAKE_MEDIA & fw_engine) { |
|
| - | 423 | WARN_ON(dev_priv->uncore.fw_mediacount == 0); |
|
| - | 424 | if (--dev_priv->uncore.fw_mediacount == 0) |
|
| - | 425 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
|
| - | 426 | FORCEWAKE_MEDIA); |
|
| - | 427 | } |
|
| - | 428 | ||
| - | 429 | if (FORCEWAKE_BLITTER & fw_engine) { |
|
| - | 430 | WARN_ON(dev_priv->uncore.fw_blittercount == 0); |
|
| - | 431 | if (--dev_priv->uncore.fw_blittercount == 0) |
|
| - | 432 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
|
| - | 433 | FORCEWAKE_BLITTER); |
|
| - | 434 | } |
|
| - | 435 | ||
| - | 436 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
|
| 300 | } |
437 | } |
| 301 | 438 | ||
| 302 | static void gen6_force_wake_timer(unsigned long arg) |
439 | static void gen6_force_wake_timer(unsigned long arg) |
| 303 | { |
440 | { |
| Line 332... | Line 469... | ||
| 332 | if (IS_VALLEYVIEW(dev)) |
469 | if (IS_VALLEYVIEW(dev)) |
| 333 | vlv_force_wake_reset(dev_priv); |
470 | vlv_force_wake_reset(dev_priv); |
| 334 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
471 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 335 | __gen6_gt_force_wake_reset(dev_priv); |
472 | __gen6_gt_force_wake_reset(dev_priv); |
| Line 336... | Line 473... | ||
| 336 | 473 | ||
| 337 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev)) |
474 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| Line -... | Line 475... | ||
| - | 475 | __gen7_gt_force_wake_mt_reset(dev_priv); |
|
| - | 476 | ||
| - | 477 | if (IS_GEN9(dev)) |
|
| 338 | __gen7_gt_force_wake_mt_reset(dev_priv); |
478 | __gen9_gt_force_wake_mt_reset(dev_priv); |
| 339 | 479 | ||
| Line 340... | Line 480... | ||
| 340 | if (restore) { /* If reset with a user forcewake, try to restore */ |
480 | if (restore) { /* If reset with a user forcewake, try to restore */ |
| 341 | unsigned fw = 0; |
481 | unsigned fw = 0; |
| 342 | 482 | ||
| Line 343... | Line 483... | ||
| 343 | if (IS_VALLEYVIEW(dev)) { |
483 | if (IS_VALLEYVIEW(dev)) { |
| 344 | if (dev_priv->uncore.fw_rendercount) |
484 | if (dev_priv->uncore.fw_rendercount) |
| - | 485 | fw |= FORCEWAKE_RENDER; |
|
| - | 486 | ||
| - | 487 | if (dev_priv->uncore.fw_mediacount) |
|
| - | 488 | fw |= FORCEWAKE_MEDIA; |
|
| - | 489 | } else if (IS_GEN9(dev)) { |
|
| - | 490 | if (dev_priv->uncore.fw_rendercount) |
|
| - | 491 | fw |= FORCEWAKE_RENDER; |
|
| - | 492 | ||
| - | 493 | if (dev_priv->uncore.fw_mediacount) |
|
| 345 | fw |= FORCEWAKE_RENDER; |
494 | fw |= FORCEWAKE_MEDIA; |
| 346 | 495 | ||
| 347 | if (dev_priv->uncore.fw_mediacount) |
496 | if (dev_priv->uncore.fw_blittercount) |
| 348 | fw |= FORCEWAKE_MEDIA; |
497 | fw |= FORCEWAKE_BLITTER; |
| Line 361... | Line 510... | ||
| 361 | } |
510 | } |
| Line 362... | Line 511... | ||
| 362 | 511 | ||
| 363 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
512 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| Line 364... | Line 513... | ||
| 364 | } |
513 | } |
| - | 514 | ||
| 365 | 515 | static void __intel_uncore_early_sanitize(struct drm_device *dev, |
|
| 366 | void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) |
516 | bool restore_forcewake) |
| Line 367... | Line 517... | ||
| 367 | { |
517 | { |
| 368 | struct drm_i915_private *dev_priv = dev->dev_private; |
518 | struct drm_i915_private *dev_priv = dev->dev_private; |
| Line 387... | Line 537... | ||
| 387 | __raw_i915_read32(dev_priv, GTFIFODBG)); |
537 | __raw_i915_read32(dev_priv, GTFIFODBG)); |
| Line 388... | Line 538... | ||
| 388 | 538 | ||
| 389 | intel_uncore_forcewake_reset(dev, restore_forcewake); |
539 | intel_uncore_forcewake_reset(dev, restore_forcewake); |
| Line -... | Line 540... | ||
| - | 540 | } |
|
| - | 541 | ||
| - | 542 | void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) |
|
| - | 543 | { |
|
| - | 544 | __intel_uncore_early_sanitize(dev, restore_forcewake); |
|
| - | 545 | i915_check_and_clear_faults(dev); |
|
| 390 | } |
546 | } |
| 391 | 547 | ||
| 392 | void intel_uncore_sanitize(struct drm_device *dev) |
548 | void intel_uncore_sanitize(struct drm_device *dev) |
| 393 | { |
549 | { |
| 394 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
550 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
| Line 408... | Line 564... | ||
| 408 | if (!dev_priv->uncore.funcs.force_wake_get) |
564 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 409 | return; |
565 | return; |
| Line 410... | Line 566... | ||
| 410 | 566 | ||
| Line -... | Line 567... | ||
| - | 567 | intel_runtime_pm_get(dev_priv); |
|
| - | 568 | ||
| - | 569 | /* Redirect to Gen9 specific routine */ |
|
| - | 570 | if (IS_GEN9(dev_priv->dev)) |
|
| 411 | intel_runtime_pm_get(dev_priv); |
571 | return gen9_force_wake_get(dev_priv, fw_engine); |
| 412 | 572 | ||
| 413 | /* Redirect to VLV specific routine */ |
573 | /* Redirect to VLV specific routine */ |
| Line 414... | Line 574... | ||
| 414 | if (IS_VALLEYVIEW(dev_priv->dev)) |
574 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| Line 429... | Line 589... | ||
| 429 | bool delayed = false; |
589 | bool delayed = false; |
| Line 430... | Line 590... | ||
| 430 | 590 | ||
| 431 | if (!dev_priv->uncore.funcs.force_wake_put) |
591 | if (!dev_priv->uncore.funcs.force_wake_put) |
| Line -... | Line 592... | ||
| - | 592 | return; |
|
| - | 593 | ||
| - | 594 | /* Redirect to Gen9 specific routine */ |
|
| - | 595 | if (IS_GEN9(dev_priv->dev)) { |
|
| - | 596 | gen9_force_wake_put(dev_priv, fw_engine); |
|
| - | 597 | goto out; |
|
| 432 | return; |
598 | } |
| 433 | 599 | ||
| 434 | /* Redirect to VLV specific routine */ |
600 | /* Redirect to VLV specific routine */ |
| 435 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
601 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 436 | vlv_force_wake_put(dev_priv, fw_engine); |
602 | vlv_force_wake_put(dev_priv, fw_engine); |
| Line 502... | Line 668... | ||
| 502 | REG_RANGE((reg), 0xC000, 0xC800) || \ |
668 | REG_RANGE((reg), 0xC000, 0xC800) || \ |
| 503 | REG_RANGE((reg), 0xF000, 0x10000) || \ |
669 | REG_RANGE((reg), 0xF000, 0x10000) || \ |
| 504 | REG_RANGE((reg), 0x14000, 0x14400) || \ |
670 | REG_RANGE((reg), 0x14000, 0x14400) || \ |
| 505 | REG_RANGE((reg), 0x22000, 0x24000)) |
671 | REG_RANGE((reg), 0x22000, 0x24000)) |
| Line -... | Line 672... | ||
| - | 672 | ||
| - | 673 | #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ |
|
| - | 674 | REG_RANGE((reg), 0xB00, 0x2000) |
|
| - | 675 | ||
| - | 676 | #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ |
|
| - | 677 | (REG_RANGE((reg), 0x2000, 0x2700) || \ |
|
| - | 678 | REG_RANGE((reg), 0x3000, 0x4000) || \ |
|
| - | 679 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
|
| - | 680 | REG_RANGE((reg), 0x8140, 0x8160) || \ |
|
| - | 681 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
|
| - | 682 | REG_RANGE((reg), 0x8C00, 0x8D00) || \ |
|
| - | 683 | REG_RANGE((reg), 0xB000, 0xB480) || \ |
|
| - | 684 | REG_RANGE((reg), 0xE000, 0xE900) || \ |
|
| - | 685 | REG_RANGE((reg), 0x24400, 0x24800)) |
|
| - | 686 | ||
| - | 687 | #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ |
|
| - | 688 | (REG_RANGE((reg), 0x8130, 0x8140) || \ |
|
| - | 689 | REG_RANGE((reg), 0x8800, 0x8A00) || \ |
|
| - | 690 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
|
| - | 691 | REG_RANGE((reg), 0x12000, 0x14000) || \ |
|
| - | 692 | REG_RANGE((reg), 0x1A000, 0x1EA00) || \ |
|
| - | 693 | REG_RANGE((reg), 0x30000, 0x40000)) |
|
| - | 694 | ||
| - | 695 | #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \ |
|
| - | 696 | REG_RANGE((reg), 0x9400, 0x9800) |
|
| - | 697 | ||
| - | 698 | #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \ |
|
| - | 699 | ((reg) < 0x40000 &&\ |
|
| - | 700 | !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \ |
|
| - | 701 | !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \ |
|
| - | 702 | !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \ |
|
| - | 703 | !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) |
|
| 506 | 704 | ||
| 507 | static void |
705 | static void |
| 508 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
706 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
| 509 | { |
707 | { |
| 510 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
708 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
| Line 632... | Line 830... | ||
| 632 | if (fwengine) \ |
830 | if (fwengine) \ |
| 633 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
831 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 634 | REG_READ_FOOTER; \ |
832 | REG_READ_FOOTER; \ |
| 635 | } |
833 | } |
| Line -... | Line 834... | ||
| - | 834 | ||
| - | 835 | #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \ |
|
| - | 836 | ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg)) |
|
| - | 837 | ||
| - | 838 | #define __gen9_read(x) \ |
|
| - | 839 | static u##x \ |
|
| - | 840 | gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
|
| - | 841 | REG_READ_HEADER(x); \ |
|
| - | 842 | if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
|
| - | 843 | val = __raw_i915_read##x(dev_priv, reg); \ |
|
| - | 844 | } else { \ |
|
| - | 845 | unsigned fwengine = 0; \ |
|
| - | 846 | if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \ |
|
| - | 847 | if (dev_priv->uncore.fw_rendercount == 0) \ |
|
| - | 848 | fwengine = FORCEWAKE_RENDER; \ |
|
| - | 849 | } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \ |
|
| - | 850 | if (dev_priv->uncore.fw_mediacount == 0) \ |
|
| - | 851 | fwengine = FORCEWAKE_MEDIA; \ |
|
| - | 852 | } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \ |
|
| - | 853 | if (dev_priv->uncore.fw_rendercount == 0) \ |
|
| - | 854 | fwengine |= FORCEWAKE_RENDER; \ |
|
| - | 855 | if (dev_priv->uncore.fw_mediacount == 0) \ |
|
| - | 856 | fwengine |= FORCEWAKE_MEDIA; \ |
|
| - | 857 | } else { \ |
|
| - | 858 | if (dev_priv->uncore.fw_blittercount == 0) \ |
|
| - | 859 | fwengine = FORCEWAKE_BLITTER; \ |
|
| - | 860 | } \ |
|
| - | 861 | if (fwengine) \ |
|
| - | 862 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
|
| - | 863 | val = __raw_i915_read##x(dev_priv, reg); \ |
|
| - | 864 | if (fwengine) \ |
|
| - | 865 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
|
| - | 866 | } \ |
|
| - | 867 | REG_READ_FOOTER; \ |
|
| - | 868 | } |
|
| - | 869 | ||
| - | 870 | __gen9_read(8) |
|
| - | 871 | __gen9_read(16) |
|
| - | 872 | __gen9_read(32) |
|
| 636 | 873 | __gen9_read(64) |
|
| 637 | __chv_read(8) |
874 | __chv_read(8) |
| 638 | __chv_read(16) |
875 | __chv_read(16) |
| 639 | __chv_read(32) |
876 | __chv_read(32) |
| 640 | __chv_read(64) |
877 | __chv_read(64) |
| Line 653... | Line 890... | ||
| 653 | __gen4_read(8) |
890 | __gen4_read(8) |
| 654 | __gen4_read(16) |
891 | __gen4_read(16) |
| 655 | __gen4_read(32) |
892 | __gen4_read(32) |
| 656 | __gen4_read(64) |
893 | __gen4_read(64) |
| Line -... | Line 894... | ||
| - | 894 | ||
| 657 | 895 | #undef __gen9_read |
|
| 658 | #undef __chv_read |
896 | #undef __chv_read |
| 659 | #undef __vlv_read |
897 | #undef __vlv_read |
| 660 | #undef __gen6_read |
898 | #undef __gen6_read |
| 661 | #undef __gen5_read |
899 | #undef __gen5_read |
| Line 790... | Line 1028... | ||
| 790 | if (fwengine) \ |
1028 | if (fwengine) \ |
| 791 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
1029 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 792 | REG_WRITE_FOOTER; \ |
1030 | REG_WRITE_FOOTER; \ |
| 793 | } |
1031 | } |
| Line -... | Line 1032... | ||
| - | 1032 | ||
| - | 1033 | static const u32 gen9_shadowed_regs[] = { |
|
| - | 1034 | RING_TAIL(RENDER_RING_BASE), |
|
| - | 1035 | RING_TAIL(GEN6_BSD_RING_BASE), |
|
| - | 1036 | RING_TAIL(VEBOX_RING_BASE), |
|
| - | 1037 | RING_TAIL(BLT_RING_BASE), |
|
| - | 1038 | FORCEWAKE_BLITTER_GEN9, |
|
| - | 1039 | FORCEWAKE_RENDER_GEN9, |
|
| - | 1040 | FORCEWAKE_MEDIA_GEN9, |
|
| - | 1041 | GEN6_RPNSWREQ, |
|
| - | 1042 | GEN6_RC_VIDEO_FREQ, |
|
| - | 1043 | /* TODO: Other registers are not yet used */ |
|
| - | 1044 | }; |
|
| - | 1045 | ||
| - | 1046 | static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg) |
|
| - | 1047 | { |
|
| - | 1048 | int i; |
|
| - | 1049 | for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++) |
|
| - | 1050 | if (reg == gen9_shadowed_regs[i]) |
|
| - | 1051 | return true; |
|
| - | 1052 | ||
| - | 1053 | return false; |
|
| - | 1054 | } |
|
| - | 1055 | ||
| - | 1056 | #define __gen9_write(x) \ |
|
| - | 1057 | static void \ |
|
| - | 1058 | gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \ |
|
| - | 1059 | bool trace) { \ |
|
| - | 1060 | REG_WRITE_HEADER; \ |
|
| - | 1061 | if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \ |
|
| - | 1062 | is_gen9_shadowed(dev_priv, reg)) { \ |
|
| - | 1063 | __raw_i915_write##x(dev_priv, reg, val); \ |
|
| - | 1064 | } else { \ |
|
| - | 1065 | unsigned fwengine = 0; \ |
|
| - | 1066 | if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \ |
|
| - | 1067 | if (dev_priv->uncore.fw_rendercount == 0) \ |
|
| - | 1068 | fwengine = FORCEWAKE_RENDER; \ |
|
| - | 1069 | } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \ |
|
| - | 1070 | if (dev_priv->uncore.fw_mediacount == 0) \ |
|
| - | 1071 | fwengine = FORCEWAKE_MEDIA; \ |
|
| - | 1072 | } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \ |
|
| - | 1073 | if (dev_priv->uncore.fw_rendercount == 0) \ |
|
| - | 1074 | fwengine |= FORCEWAKE_RENDER; \ |
|
| - | 1075 | if (dev_priv->uncore.fw_mediacount == 0) \ |
|
| - | 1076 | fwengine |= FORCEWAKE_MEDIA; \ |
|
| - | 1077 | } else { \ |
|
| - | 1078 | if (dev_priv->uncore.fw_blittercount == 0) \ |
|
| - | 1079 | fwengine = FORCEWAKE_BLITTER; \ |
|
| - | 1080 | } \ |
|
| - | 1081 | if (fwengine) \ |
|
| - | 1082 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
|
| - | 1083 | fwengine); \ |
|
| - | 1084 | __raw_i915_write##x(dev_priv, reg, val); \ |
|
| - | 1085 | if (fwengine) \ |
|
| - | 1086 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
|
| - | 1087 | fwengine); \ |
|
| - | 1088 | } \ |
|
| - | 1089 | REG_WRITE_FOOTER; \ |
|
| - | 1090 | } |
|
| - | 1091 | ||
| - | 1092 | __gen9_write(8) |
|
| - | 1093 | __gen9_write(16) |
|
| - | 1094 | __gen9_write(32) |
|
| 794 | 1095 | __gen9_write(64) |
|
| 795 | __chv_write(8) |
1096 | __chv_write(8) |
| 796 | __chv_write(16) |
1097 | __chv_write(16) |
| 797 | __chv_write(32) |
1098 | __chv_write(32) |
| 798 | __chv_write(64) |
1099 | __chv_write(64) |
| Line 815... | Line 1116... | ||
| 815 | __gen4_write(8) |
1116 | __gen4_write(8) |
| 816 | __gen4_write(16) |
1117 | __gen4_write(16) |
| 817 | __gen4_write(32) |
1118 | __gen4_write(32) |
| 818 | __gen4_write(64) |
1119 | __gen4_write(64) |
| Line -... | Line 1120... | ||
| - | 1120 | ||
| 819 | 1121 | #undef __gen9_write |
|
| 820 | #undef __chv_write |
1122 | #undef __chv_write |
| 821 | #undef __gen8_write |
1123 | #undef __gen8_write |
| 822 | #undef __hsw_write |
1124 | #undef __hsw_write |
| 823 | #undef __gen6_write |
1125 | #undef __gen6_write |
| 824 | #undef __gen5_write |
1126 | #undef __gen5_write |
| 825 | #undef __gen4_write |
1127 | #undef __gen4_write |
| 826 | #undef REG_WRITE_FOOTER |
1128 | #undef REG_WRITE_FOOTER |
| Line -... | Line 1129... | ||
| - | 1129 | #undef REG_WRITE_HEADER |
|
| - | 1130 | ||
| - | 1131 | #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ |
|
| - | 1132 | do { \ |
|
| - | 1133 | dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ |
|
| - | 1134 | dev_priv->uncore.funcs.mmio_writew = x##_write16; \ |
|
| - | 1135 | dev_priv->uncore.funcs.mmio_writel = x##_write32; \ |
|
| - | 1136 | dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ |
|
| - | 1137 | } while (0) |
|
| - | 1138 | ||
| - | 1139 | #define ASSIGN_READ_MMIO_VFUNCS(x) \ |
|
| - | 1140 | do { \ |
|
| - | 1141 | dev_priv->uncore.funcs.mmio_readb = x##_read8; \ |
|
| - | 1142 | dev_priv->uncore.funcs.mmio_readw = x##_read16; \ |
|
| - | 1143 | dev_priv->uncore.funcs.mmio_readl = x##_read32; \ |
|
| - | 1144 | dev_priv->uncore.funcs.mmio_readq = x##_read64; \ |
|
| 827 | #undef REG_WRITE_HEADER |
1145 | } while (0) |
| 828 | 1146 | ||
| 829 | void intel_uncore_init(struct drm_device *dev) |
1147 | void intel_uncore_init(struct drm_device *dev) |
| Line 830... | Line 1148... | ||
| 830 | { |
1148 | { |
| 831 | struct drm_i915_private *dev_priv = dev->dev_private; |
1149 | struct drm_i915_private *dev_priv = dev->dev_private; |
| Line 832... | Line 1150... | ||
| 832 | 1150 | ||
| Line -... | Line 1151... | ||
| - | 1151 | setup_timer(&dev_priv->uncore.force_wake_timer, |
|
| - | 1152 | gen6_force_wake_timer, (unsigned long)dev_priv); |
|
| - | 1153 | ||
| 833 | setup_timer(&dev_priv->uncore.force_wake_timer, |
1154 | __intel_uncore_early_sanitize(dev, false); |
| 834 | gen6_force_wake_timer, (unsigned long)dev_priv); |
1155 | |
| 835 | 1156 | if (IS_GEN9(dev)) { |
|
| 836 | intel_uncore_early_sanitize(dev, false); |
1157 | dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get; |
| 837 | 1158 | dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put; |
|
| 838 | if (IS_VALLEYVIEW(dev)) { |
1159 | } else if (IS_VALLEYVIEW(dev)) { |
| 839 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
1160 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
| 840 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; |
1161 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; |
| Line 879... | Line 1200... | ||
| 879 | __gen6_gt_force_wake_put; |
1200 | __gen6_gt_force_wake_put; |
| 880 | } |
1201 | } |
| Line 881... | Line 1202... | ||
| 881 | 1202 | ||
| 882 | switch (INTEL_INFO(dev)->gen) { |
1203 | switch (INTEL_INFO(dev)->gen) { |
| - | 1204 | default: |
|
| - | 1205 | WARN_ON(1); |
|
| - | 1206 | return; |
|
| - | 1207 | case 9: |
|
| - | 1208 | ASSIGN_WRITE_MMIO_VFUNCS(gen9); |
|
| - | 1209 | ASSIGN_READ_MMIO_VFUNCS(gen9); |
|
| - | 1210 | break; |
|
| 883 | default: |
1211 | case 8: |
| 884 | if (IS_CHERRYVIEW(dev)) { |
- | |
| 885 | dev_priv->uncore.funcs.mmio_writeb = chv_write8; |
- | |
| 886 | dev_priv->uncore.funcs.mmio_writew = chv_write16; |
- | |
| 887 | dev_priv->uncore.funcs.mmio_writel = chv_write32; |
- | |
| 888 | dev_priv->uncore.funcs.mmio_writeq = chv_write64; |
1212 | if (IS_CHERRYVIEW(dev)) { |
| 889 | dev_priv->uncore.funcs.mmio_readb = chv_read8; |
1213 | ASSIGN_WRITE_MMIO_VFUNCS(chv); |
| 890 | dev_priv->uncore.funcs.mmio_readw = chv_read16; |
- | |
| 891 | dev_priv->uncore.funcs.mmio_readl = chv_read32; |
- | |
| Line 892... | Line 1214... | ||
| 892 | dev_priv->uncore.funcs.mmio_readq = chv_read64; |
1214 | ASSIGN_READ_MMIO_VFUNCS(chv); |
| 893 | 1215 | ||
| 894 | } else { |
- | |
| 895 | dev_priv->uncore.funcs.mmio_writeb = gen8_write8; |
- | |
| 896 | dev_priv->uncore.funcs.mmio_writew = gen8_write16; |
- | |
| 897 | dev_priv->uncore.funcs.mmio_writel = gen8_write32; |
1216 | } else { |
| 898 | dev_priv->uncore.funcs.mmio_writeq = gen8_write64; |
- | |
| 899 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
- | |
| 900 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; |
- | |
| 901 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; |
1217 | ASSIGN_WRITE_MMIO_VFUNCS(gen8); |
| 902 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; |
1218 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
| 903 | } |
1219 | } |
| 904 | break; |
1220 | break; |
| 905 | case 7: |
1221 | case 7: |
| 906 | case 6: |
1222 | case 6: |
| 907 | if (IS_HASWELL(dev)) { |
- | |
| 908 | dev_priv->uncore.funcs.mmio_writeb = hsw_write8; |
- | |
| 909 | dev_priv->uncore.funcs.mmio_writew = hsw_write16; |
- | |
| 910 | dev_priv->uncore.funcs.mmio_writel = hsw_write32; |
1223 | if (IS_HASWELL(dev)) { |
| 911 | dev_priv->uncore.funcs.mmio_writeq = hsw_write64; |
1224 | ASSIGN_WRITE_MMIO_VFUNCS(hsw); |
| 912 | } else { |
- | |
| 913 | dev_priv->uncore.funcs.mmio_writeb = gen6_write8; |
- | |
| 914 | dev_priv->uncore.funcs.mmio_writew = gen6_write16; |
- | |
| 915 | dev_priv->uncore.funcs.mmio_writel = gen6_write32; |
1225 | } else { |
| Line 916... | Line 1226... | ||
| 916 | dev_priv->uncore.funcs.mmio_writeq = gen6_write64; |
1226 | ASSIGN_WRITE_MMIO_VFUNCS(gen6); |
| 917 | } |
1227 | } |
| 918 | - | ||
| 919 | if (IS_VALLEYVIEW(dev)) { |
- | |
| 920 | dev_priv->uncore.funcs.mmio_readb = vlv_read8; |
- | |
| 921 | dev_priv->uncore.funcs.mmio_readw = vlv_read16; |
1228 | |
| 922 | dev_priv->uncore.funcs.mmio_readl = vlv_read32; |
1229 | if (IS_VALLEYVIEW(dev)) { |
| 923 | dev_priv->uncore.funcs.mmio_readq = vlv_read64; |
- | |
| 924 | } else { |
- | |
| 925 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
- | |
| 926 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; |
1230 | ASSIGN_READ_MMIO_VFUNCS(vlv); |
| 927 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; |
1231 | } else { |
| 928 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; |
1232 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
| 929 | } |
- | |
| 930 | break; |
- | |
| 931 | case 5: |
- | |
| 932 | dev_priv->uncore.funcs.mmio_writeb = gen5_write8; |
- | |
| 933 | dev_priv->uncore.funcs.mmio_writew = gen5_write16; |
1233 | } |
| 934 | dev_priv->uncore.funcs.mmio_writel = gen5_write32; |
1234 | break; |
| 935 | dev_priv->uncore.funcs.mmio_writeq = gen5_write64; |
- | |
| 936 | dev_priv->uncore.funcs.mmio_readb = gen5_read8; |
- | |
| 937 | dev_priv->uncore.funcs.mmio_readw = gen5_read16; |
1235 | case 5: |
| 938 | dev_priv->uncore.funcs.mmio_readl = gen5_read32; |
1236 | ASSIGN_WRITE_MMIO_VFUNCS(gen5); |
| 939 | dev_priv->uncore.funcs.mmio_readq = gen5_read64; |
1237 | ASSIGN_READ_MMIO_VFUNCS(gen5); |
| 940 | break; |
1238 | break; |
| 941 | case 4: |
- | |
| 942 | case 3: |
- | |
| 943 | case 2: |
- | |
| 944 | dev_priv->uncore.funcs.mmio_writeb = gen4_write8; |
- | |
| 945 | dev_priv->uncore.funcs.mmio_writew = gen4_write16; |
1239 | case 4: |
| 946 | dev_priv->uncore.funcs.mmio_writel = gen4_write32; |
1240 | case 3: |
| 947 | dev_priv->uncore.funcs.mmio_writeq = gen4_write64; |
- | |
| 948 | dev_priv->uncore.funcs.mmio_readb = gen4_read8; |
- | |
| 949 | dev_priv->uncore.funcs.mmio_readw = gen4_read16; |
1241 | case 2: |
| 950 | dev_priv->uncore.funcs.mmio_readl = gen4_read32; |
1242 | ASSIGN_WRITE_MMIO_VFUNCS(gen4); |
| - | 1243 | ASSIGN_READ_MMIO_VFUNCS(gen4); |
|
| - | 1244 | break; |
|
| 951 | dev_priv->uncore.funcs.mmio_readq = gen4_read64; |
1245 | } |
| - | 1246 | ||
| - | 1247 | i915_check_and_clear_faults(dev); |
|
| Line 952... | Line 1248... | ||
| 952 | break; |
1248 | } |
| 953 | } |
1249 | #undef ASSIGN_WRITE_MMIO_VFUNCS |
| 954 | } |
1250 | #undef ASSIGN_READ_MMIO_VFUNCS |
| 955 | 1251 | ||
| Line 966... | Line 1262... | ||
| 966 | uint64_t offset; |
1262 | uint64_t offset; |
| 967 | uint32_t size; |
1263 | uint32_t size; |
| 968 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
1264 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
| 969 | uint32_t gen_bitmask; |
1265 | uint32_t gen_bitmask; |
| 970 | } whitelist[] = { |
1266 | } whitelist[] = { |
| 971 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) }, |
1267 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) }, |
| 972 | }; |
1268 | }; |
| Line 973... | Line 1269... | ||
| 973 | 1269 | ||
| 974 | int i915_reg_read_ioctl(struct drm_device *dev, |
1270 | int i915_reg_read_ioctl(struct drm_device *dev, |
| 975 | void *data, struct drm_file *file) |
1271 | void *data, struct drm_file *file) |
| Line 1042... | Line 1338... | ||
| 1042 | mutex_unlock(&dev->struct_mutex); |
1338 | mutex_unlock(&dev->struct_mutex); |
| Line 1043... | Line 1339... | ||
| 1043 | 1339 | ||
| 1044 | return 0; |
1340 | return 0; |
| Line 1045... | Line 1341... | ||
| 1045 | } |
1341 | } |
| 1046 | 1342 | ||
| 1047 | static int i965_reset_complete(struct drm_device *dev) |
1343 | static int i915_reset_complete(struct drm_device *dev) |
| 1048 | { |
1344 | { |
| 1049 | u8 gdrst; |
1345 | u8 gdrst; |
| 1050 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
1346 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
| Line 1051... | Line 1347... | ||
| 1051 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
1347 | return (gdrst & GRDOM_RESET_STATUS) == 0; |
| 1052 | } |
1348 | } |
| 1053 | 1349 | ||
| 1054 | static int i965_do_reset(struct drm_device *dev) |
- | |
| 1055 | { |
1350 | static int i915_do_reset(struct drm_device *dev) |
| 1056 | int ret; |
1351 | { |
| - | 1352 | /* assert reset for at least 20 usec */ |
|
| Line 1057... | Line -... | ||
| 1057 | - | ||
| 1058 | /* FIXME: i965g/gm need a display save/restore for gpu reset. */ |
- | |
| 1059 | return -ENODEV; |
- | |
| 1060 | - | ||
| 1061 | /* |
- | |
| 1062 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
- | |
| 1063 | * well as the reset bit (GR/bit 0). Setting the GR bit |
- | |
| 1064 | * triggers the reset; when done, the hardware will clear it. |
1353 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
| 1065 | */ |
- | |
| 1066 | pci_write_config_byte(dev->pdev, I965_GDRST, |
- | |
| 1067 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
- | |
| 1068 | ret = wait_for(i965_reset_complete(dev), 500); |
- | |
| 1069 | if (ret) |
- | |
| 1070 | return ret; |
1354 | udelay(20); |
| 1071 | - | ||
| 1072 | pci_write_config_byte(dev->pdev, I965_GDRST, |
- | |
| 1073 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
- | |
| Line -... | Line 1355... | ||
| - | 1355 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
|
| - | 1356 | ||
| - | 1357 | return wait_for(i915_reset_complete(dev), 500); |
|
| 1074 | 1358 | } |
|
| - | 1359 | ||
| - | 1360 | static int g4x_reset_complete(struct drm_device *dev) |
|
| Line -... | Line 1361... | ||
| - | 1361 | { |
|
| - | 1362 | u8 gdrst; |
|
| - | 1363 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
|
| 1075 | ret = wait_for(i965_reset_complete(dev), 500); |
1364 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
| 1076 | if (ret) |
1365 | } |
| Line 1077... | Line 1366... | ||
| 1077 | return ret; |
1366 | |
| 1078 | 1367 | static int g33_do_reset(struct drm_device *dev) |
|
| 1079 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
1368 | { |
| 1080 | 1369 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
|
| Line 1081... | Line 1370... | ||
| 1081 | return 0; |
1370 | return wait_for(g4x_reset_complete(dev), 500); |
| 1082 | } |
1371 | } |
| 1083 | 1372 | ||
| 1084 | static int g4x_do_reset(struct drm_device *dev) |
1373 | static int g4x_do_reset(struct drm_device *dev) |
| 1085 | { |
1374 | { |
| Line 1086... | Line 1375... | ||
| 1086 | struct drm_i915_private *dev_priv = dev->dev_private; |
1375 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1087 | int ret; |
1376 | int ret; |
| 1088 | 1377 | ||
| Line 1089... | Line 1378... | ||
| 1089 | pci_write_config_byte(dev->pdev, I965_GDRST, |
1378 | pci_write_config_byte(dev->pdev, I915_GDRST, |
| 1090 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
1379 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 1091 | ret = wait_for(i965_reset_complete(dev), 500); |
1380 | ret = wait_for(g4x_reset_complete(dev), 500); |
| 1092 | if (ret) |
1381 | if (ret) |
| 1093 | return ret; |
1382 | return ret; |
| Line 1094... | Line 1383... | ||
| 1094 | 1383 | ||
| 1095 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ |
1384 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ |
| 1096 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); |
1385 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); |
| Line 1097... | Line 1386... | ||
| 1097 | POSTING_READ(VDECCLK_GATE_D); |
1386 | POSTING_READ(VDECCLK_GATE_D); |
| Line 1098... | Line 1387... | ||
| 1098 | 1387 | ||
| 1099 | pci_write_config_byte(dev->pdev, I965_GDRST, |
1388 | pci_write_config_byte(dev->pdev, I915_GDRST, |
| Line 1100... | Line 1389... | ||
| 1100 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
1389 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| Line 1162... | Line 1451... | ||
| 1162 | return gen6_do_reset(dev); |
1451 | return gen6_do_reset(dev); |
| 1163 | else if (IS_GEN5(dev)) |
1452 | else if (IS_GEN5(dev)) |
| 1164 | return ironlake_do_reset(dev); |
1453 | return ironlake_do_reset(dev); |
| 1165 | else if (IS_G4X(dev)) |
1454 | else if (IS_G4X(dev)) |
| 1166 | return g4x_do_reset(dev); |
1455 | return g4x_do_reset(dev); |
| 1167 | else if (IS_GEN4(dev)) |
1456 | else if (IS_G33(dev)) |
| - | 1457 | return g33_do_reset(dev); |
|
| - | 1458 | else if (INTEL_INFO(dev)->gen >= 3) |
|
| 1168 | return i965_do_reset(dev); |
1459 | return i915_do_reset(dev); |
| 1169 | else |
1460 | else |
| 1170 | return -ENODEV; |
1461 | return -ENODEV; |
| 1171 | } |
1462 | } |
| Line 1172... | Line 1463... | ||
| 1172 | 1463 | ||