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1 | /* |
1 | /* |
2 | * Copyright © 2011 Intel Corporation |
2 | * Copyright © 2011 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
21 | * SOFTWARE. |
21 | * SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Jesse Barnes |
24 | * Jesse Barnes |
25 | * |
25 | * |
26 | * New plane/sprite handling. |
26 | * New plane/sprite handling. |
27 | * |
27 | * |
28 | * The older chips had a separate interface for programming plane related |
28 | * The older chips had a separate interface for programming plane related |
29 | * registers; newer ones are much simpler and we can use the new DRM plane |
29 | * registers; newer ones are much simpler and we can use the new DRM plane |
30 | * support. |
30 | * support. |
31 | */ |
31 | */ |
32 | #include |
32 | #include |
33 | #include |
33 | #include |
34 | #include |
34 | #include |
- | 35 | #include |
|
35 | #include "intel_drv.h" |
36 | #include "intel_drv.h" |
36 | #include |
37 | #include |
37 | #include "i915_drv.h" |
38 | #include "i915_drv.h" |
38 | 39 | ||
39 | static void |
40 | static void |
40 | vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb, |
41 | vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
- | 42 | struct drm_framebuffer *fb, |
|
41 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
43 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
42 | unsigned int crtc_w, unsigned int crtc_h, |
44 | unsigned int crtc_w, unsigned int crtc_h, |
43 | uint32_t x, uint32_t y, |
45 | uint32_t x, uint32_t y, |
44 | uint32_t src_w, uint32_t src_h) |
46 | uint32_t src_w, uint32_t src_h) |
45 | { |
47 | { |
46 | struct drm_device *dev = dplane->dev; |
48 | struct drm_device *dev = dplane->dev; |
47 | struct drm_i915_private *dev_priv = dev->dev_private; |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
48 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
50 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
49 | int pipe = intel_plane->pipe; |
51 | int pipe = intel_plane->pipe; |
50 | int plane = intel_plane->plane; |
52 | int plane = intel_plane->plane; |
51 | u32 sprctl; |
53 | u32 sprctl; |
52 | unsigned long sprsurf_offset, linear_offset; |
54 | unsigned long sprsurf_offset, linear_offset; |
53 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
55 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
54 | 56 | ||
55 | sprctl = I915_READ(SPCNTR(pipe, plane)); |
57 | sprctl = I915_READ(SPCNTR(pipe, plane)); |
56 | 58 | ||
57 | /* Mask out pixel format bits in case we change it */ |
59 | /* Mask out pixel format bits in case we change it */ |
58 | sprctl &= ~SP_PIXFORMAT_MASK; |
60 | sprctl &= ~SP_PIXFORMAT_MASK; |
59 | sprctl &= ~SP_YUV_BYTE_ORDER_MASK; |
61 | sprctl &= ~SP_YUV_BYTE_ORDER_MASK; |
60 | sprctl &= ~SP_TILED; |
62 | sprctl &= ~SP_TILED; |
61 | 63 | ||
62 | switch (fb->pixel_format) { |
64 | switch (fb->pixel_format) { |
63 | case DRM_FORMAT_YUYV: |
65 | case DRM_FORMAT_YUYV: |
64 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; |
66 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; |
65 | break; |
67 | break; |
66 | case DRM_FORMAT_YVYU: |
68 | case DRM_FORMAT_YVYU: |
67 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; |
69 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; |
68 | break; |
70 | break; |
69 | case DRM_FORMAT_UYVY: |
71 | case DRM_FORMAT_UYVY: |
70 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; |
72 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; |
71 | break; |
73 | break; |
72 | case DRM_FORMAT_VYUY: |
74 | case DRM_FORMAT_VYUY: |
73 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; |
75 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; |
74 | break; |
76 | break; |
75 | case DRM_FORMAT_RGB565: |
77 | case DRM_FORMAT_RGB565: |
76 | sprctl |= SP_FORMAT_BGR565; |
78 | sprctl |= SP_FORMAT_BGR565; |
77 | break; |
79 | break; |
78 | case DRM_FORMAT_XRGB8888: |
80 | case DRM_FORMAT_XRGB8888: |
79 | sprctl |= SP_FORMAT_BGRX8888; |
81 | sprctl |= SP_FORMAT_BGRX8888; |
80 | break; |
82 | break; |
81 | case DRM_FORMAT_ARGB8888: |
83 | case DRM_FORMAT_ARGB8888: |
82 | sprctl |= SP_FORMAT_BGRA8888; |
84 | sprctl |= SP_FORMAT_BGRA8888; |
83 | break; |
85 | break; |
84 | case DRM_FORMAT_XBGR2101010: |
86 | case DRM_FORMAT_XBGR2101010: |
85 | sprctl |= SP_FORMAT_RGBX1010102; |
87 | sprctl |= SP_FORMAT_RGBX1010102; |
86 | break; |
88 | break; |
87 | case DRM_FORMAT_ABGR2101010: |
89 | case DRM_FORMAT_ABGR2101010: |
88 | sprctl |= SP_FORMAT_RGBA1010102; |
90 | sprctl |= SP_FORMAT_RGBA1010102; |
89 | break; |
91 | break; |
90 | case DRM_FORMAT_XBGR8888: |
92 | case DRM_FORMAT_XBGR8888: |
91 | sprctl |= SP_FORMAT_RGBX8888; |
93 | sprctl |= SP_FORMAT_RGBX8888; |
92 | break; |
94 | break; |
93 | case DRM_FORMAT_ABGR8888: |
95 | case DRM_FORMAT_ABGR8888: |
94 | sprctl |= SP_FORMAT_RGBA8888; |
96 | sprctl |= SP_FORMAT_RGBA8888; |
95 | break; |
97 | break; |
96 | default: |
98 | default: |
97 | /* |
99 | /* |
98 | * If we get here one of the upper layers failed to filter |
100 | * If we get here one of the upper layers failed to filter |
99 | * out the unsupported plane formats |
101 | * out the unsupported plane formats |
100 | */ |
102 | */ |
101 | BUG(); |
103 | BUG(); |
102 | break; |
104 | break; |
103 | } |
105 | } |
104 | 106 | ||
105 | if (obj->tiling_mode != I915_TILING_NONE) |
107 | if (obj->tiling_mode != I915_TILING_NONE) |
106 | sprctl |= SP_TILED; |
108 | sprctl |= SP_TILED; |
107 | 109 | ||
108 | sprctl |= SP_ENABLE; |
110 | sprctl |= SP_ENABLE; |
- | 111 | ||
- | 112 | intel_update_sprite_watermarks(dplane, crtc, src_w, pixel_size, true, |
|
- | 113 | src_w != crtc_w || src_h != crtc_h); |
|
109 | 114 | ||
110 | /* Sizes are 0 based */ |
115 | /* Sizes are 0 based */ |
111 | src_w--; |
116 | src_w--; |
112 | src_h--; |
117 | src_h--; |
113 | crtc_w--; |
118 | crtc_w--; |
114 | crtc_h--; |
119 | crtc_h--; |
115 | - | ||
116 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); |
- | |
117 | 120 | ||
118 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
121 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
119 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); |
122 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); |
120 | 123 | ||
121 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
124 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
122 | sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, |
125 | sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, |
123 | obj->tiling_mode, |
126 | obj->tiling_mode, |
124 | pixel_size, |
127 | pixel_size, |
125 | fb->pitches[0]); |
128 | fb->pitches[0]); |
126 | linear_offset -= sprsurf_offset; |
129 | linear_offset -= sprsurf_offset; |
127 | 130 | ||
128 | if (obj->tiling_mode != I915_TILING_NONE) |
131 | if (obj->tiling_mode != I915_TILING_NONE) |
129 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); |
132 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); |
130 | else |
133 | else |
131 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); |
134 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); |
132 | 135 | ||
133 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
136 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
134 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
137 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
135 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset + |
138 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
136 | sprsurf_offset); |
139 | sprsurf_offset); |
137 | POSTING_READ(SPSURF(pipe, plane)); |
140 | POSTING_READ(SPSURF(pipe, plane)); |
138 | } |
141 | } |
139 | 142 | ||
140 | static void |
143 | static void |
141 | vlv_disable_plane(struct drm_plane *dplane) |
144 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
142 | { |
145 | { |
143 | struct drm_device *dev = dplane->dev; |
146 | struct drm_device *dev = dplane->dev; |
144 | struct drm_i915_private *dev_priv = dev->dev_private; |
147 | struct drm_i915_private *dev_priv = dev->dev_private; |
145 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
148 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
146 | int pipe = intel_plane->pipe; |
149 | int pipe = intel_plane->pipe; |
147 | int plane = intel_plane->plane; |
150 | int plane = intel_plane->plane; |
148 | 151 | ||
149 | I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) & |
152 | I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) & |
150 | ~SP_ENABLE); |
153 | ~SP_ENABLE); |
151 | /* Activate double buffered register update */ |
154 | /* Activate double buffered register update */ |
152 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0); |
155 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0); |
153 | POSTING_READ(SPSURF(pipe, plane)); |
156 | POSTING_READ(SPSURF(pipe, plane)); |
- | 157 | ||
- | 158 | intel_update_sprite_watermarks(dplane, crtc, 0, 0, false, false); |
|
154 | } |
159 | } |
155 | 160 | ||
156 | static int |
161 | static int |
157 | vlv_update_colorkey(struct drm_plane *dplane, |
162 | vlv_update_colorkey(struct drm_plane *dplane, |
158 | struct drm_intel_sprite_colorkey *key) |
163 | struct drm_intel_sprite_colorkey *key) |
159 | { |
164 | { |
160 | struct drm_device *dev = dplane->dev; |
165 | struct drm_device *dev = dplane->dev; |
161 | struct drm_i915_private *dev_priv = dev->dev_private; |
166 | struct drm_i915_private *dev_priv = dev->dev_private; |
162 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
167 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
163 | int pipe = intel_plane->pipe; |
168 | int pipe = intel_plane->pipe; |
164 | int plane = intel_plane->plane; |
169 | int plane = intel_plane->plane; |
165 | u32 sprctl; |
170 | u32 sprctl; |
166 | 171 | ||
167 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
172 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
168 | return -EINVAL; |
173 | return -EINVAL; |
169 | 174 | ||
170 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); |
175 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); |
171 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); |
176 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); |
172 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); |
177 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); |
173 | 178 | ||
174 | sprctl = I915_READ(SPCNTR(pipe, plane)); |
179 | sprctl = I915_READ(SPCNTR(pipe, plane)); |
175 | sprctl &= ~SP_SOURCE_KEY; |
180 | sprctl &= ~SP_SOURCE_KEY; |
176 | if (key->flags & I915_SET_COLORKEY_SOURCE) |
181 | if (key->flags & I915_SET_COLORKEY_SOURCE) |
177 | sprctl |= SP_SOURCE_KEY; |
182 | sprctl |= SP_SOURCE_KEY; |
178 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
183 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
179 | 184 | ||
180 | POSTING_READ(SPKEYMSK(pipe, plane)); |
185 | POSTING_READ(SPKEYMSK(pipe, plane)); |
181 | 186 | ||
182 | return 0; |
187 | return 0; |
183 | } |
188 | } |
184 | 189 | ||
185 | static void |
190 | static void |
186 | vlv_get_colorkey(struct drm_plane *dplane, |
191 | vlv_get_colorkey(struct drm_plane *dplane, |
187 | struct drm_intel_sprite_colorkey *key) |
192 | struct drm_intel_sprite_colorkey *key) |
188 | { |
193 | { |
189 | struct drm_device *dev = dplane->dev; |
194 | struct drm_device *dev = dplane->dev; |
190 | struct drm_i915_private *dev_priv = dev->dev_private; |
195 | struct drm_i915_private *dev_priv = dev->dev_private; |
191 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
196 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
192 | int pipe = intel_plane->pipe; |
197 | int pipe = intel_plane->pipe; |
193 | int plane = intel_plane->plane; |
198 | int plane = intel_plane->plane; |
194 | u32 sprctl; |
199 | u32 sprctl; |
195 | 200 | ||
196 | key->min_value = I915_READ(SPKEYMINVAL(pipe, plane)); |
201 | key->min_value = I915_READ(SPKEYMINVAL(pipe, plane)); |
197 | key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane)); |
202 | key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane)); |
198 | key->channel_mask = I915_READ(SPKEYMSK(pipe, plane)); |
203 | key->channel_mask = I915_READ(SPKEYMSK(pipe, plane)); |
199 | 204 | ||
200 | sprctl = I915_READ(SPCNTR(pipe, plane)); |
205 | sprctl = I915_READ(SPCNTR(pipe, plane)); |
201 | if (sprctl & SP_SOURCE_KEY) |
206 | if (sprctl & SP_SOURCE_KEY) |
202 | key->flags = I915_SET_COLORKEY_SOURCE; |
207 | key->flags = I915_SET_COLORKEY_SOURCE; |
203 | else |
208 | else |
204 | key->flags = I915_SET_COLORKEY_NONE; |
209 | key->flags = I915_SET_COLORKEY_NONE; |
205 | } |
210 | } |
206 | 211 | ||
207 | static void |
212 | static void |
208 | ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, |
213 | ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
- | 214 | struct drm_framebuffer *fb, |
|
209 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
215 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
210 | unsigned int crtc_w, unsigned int crtc_h, |
216 | unsigned int crtc_w, unsigned int crtc_h, |
211 | uint32_t x, uint32_t y, |
217 | uint32_t x, uint32_t y, |
212 | uint32_t src_w, uint32_t src_h) |
218 | uint32_t src_w, uint32_t src_h) |
213 | { |
219 | { |
214 | struct drm_device *dev = plane->dev; |
220 | struct drm_device *dev = plane->dev; |
215 | struct drm_i915_private *dev_priv = dev->dev_private; |
221 | struct drm_i915_private *dev_priv = dev->dev_private; |
216 | struct intel_plane *intel_plane = to_intel_plane(plane); |
222 | struct intel_plane *intel_plane = to_intel_plane(plane); |
217 | int pipe = intel_plane->pipe; |
223 | int pipe = intel_plane->pipe; |
218 | u32 sprctl, sprscale = 0; |
224 | u32 sprctl, sprscale = 0; |
219 | unsigned long sprsurf_offset, linear_offset; |
225 | unsigned long sprsurf_offset, linear_offset; |
220 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
226 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
221 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
227 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
222 | 228 | ||
223 | sprctl = I915_READ(SPRCTL(pipe)); |
229 | sprctl = I915_READ(SPRCTL(pipe)); |
224 | 230 | ||
225 | /* Mask out pixel format bits in case we change it */ |
231 | /* Mask out pixel format bits in case we change it */ |
226 | sprctl &= ~SPRITE_PIXFORMAT_MASK; |
232 | sprctl &= ~SPRITE_PIXFORMAT_MASK; |
227 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; |
233 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; |
228 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; |
234 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; |
229 | sprctl &= ~SPRITE_TILED; |
235 | sprctl &= ~SPRITE_TILED; |
230 | 236 | ||
231 | switch (fb->pixel_format) { |
237 | switch (fb->pixel_format) { |
232 | case DRM_FORMAT_XBGR8888: |
238 | case DRM_FORMAT_XBGR8888: |
233 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
239 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
234 | break; |
240 | break; |
235 | case DRM_FORMAT_XRGB8888: |
241 | case DRM_FORMAT_XRGB8888: |
236 | sprctl |= SPRITE_FORMAT_RGBX888; |
242 | sprctl |= SPRITE_FORMAT_RGBX888; |
237 | break; |
243 | break; |
238 | case DRM_FORMAT_YUYV: |
244 | case DRM_FORMAT_YUYV: |
239 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
245 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
240 | break; |
246 | break; |
241 | case DRM_FORMAT_YVYU: |
247 | case DRM_FORMAT_YVYU: |
242 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
248 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
243 | break; |
249 | break; |
244 | case DRM_FORMAT_UYVY: |
250 | case DRM_FORMAT_UYVY: |
245 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
251 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
246 | break; |
252 | break; |
247 | case DRM_FORMAT_VYUY: |
253 | case DRM_FORMAT_VYUY: |
248 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
254 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
249 | break; |
255 | break; |
250 | default: |
256 | default: |
251 | BUG(); |
257 | BUG(); |
252 | } |
258 | } |
253 | 259 | ||
254 | if (obj->tiling_mode != I915_TILING_NONE) |
260 | if (obj->tiling_mode != I915_TILING_NONE) |
255 | sprctl |= SPRITE_TILED; |
261 | sprctl |= SPRITE_TILED; |
256 | 262 | ||
- | 263 | if (IS_HASWELL(dev)) |
|
- | 264 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
|
257 | /* must disable */ |
265 | else |
- | 266 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
|
258 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
267 | |
259 | sprctl |= SPRITE_ENABLE; |
268 | sprctl |= SPRITE_ENABLE; |
260 | 269 | ||
261 | if (IS_HASWELL(dev)) |
270 | if (IS_HASWELL(dev)) |
262 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
271 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
- | 272 | ||
- | 273 | intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true, |
|
- | 274 | src_w != crtc_w || src_h != crtc_h); |
|
263 | 275 | ||
264 | /* Sizes are 0 based */ |
276 | /* Sizes are 0 based */ |
265 | src_w--; |
277 | src_w--; |
266 | src_h--; |
278 | src_h--; |
267 | crtc_w--; |
279 | crtc_w--; |
268 | crtc_h--; |
280 | crtc_h--; |
269 | - | ||
270 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); |
- | |
271 | 281 | ||
272 | /* |
282 | /* |
273 | * IVB workaround: must disable low power watermarks for at least |
283 | * IVB workaround: must disable low power watermarks for at least |
274 | * one frame before enabling scaling. LP watermarks can be re-enabled |
284 | * one frame before enabling scaling. LP watermarks can be re-enabled |
275 | * when scaling is disabled. |
285 | * when scaling is disabled. |
276 | */ |
286 | */ |
277 | if (crtc_w != src_w || crtc_h != src_h) { |
287 | if (crtc_w != src_w || crtc_h != src_h) { |
278 | dev_priv->sprite_scaling_enabled |= 1 << pipe; |
288 | dev_priv->sprite_scaling_enabled |= 1 << pipe; |
279 | 289 | ||
280 | if (!scaling_was_enabled) { |
290 | if (!scaling_was_enabled) { |
281 | intel_update_watermarks(dev); |
291 | intel_update_watermarks(dev); |
282 | intel_wait_for_vblank(dev, pipe); |
292 | intel_wait_for_vblank(dev, pipe); |
283 | } |
293 | } |
284 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
294 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
285 | } else |
295 | } else |
286 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
296 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
287 | 297 | ||
288 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
298 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
289 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
299 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
290 | 300 | ||
291 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
301 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
292 | sprsurf_offset = |
302 | sprsurf_offset = |
293 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
303 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
294 | pixel_size, fb->pitches[0]); |
304 | pixel_size, fb->pitches[0]); |
295 | linear_offset -= sprsurf_offset; |
305 | linear_offset -= sprsurf_offset; |
296 | 306 | ||
297 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
307 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
298 | * register */ |
308 | * register */ |
299 | if (IS_HASWELL(dev)) |
309 | if (IS_HASWELL(dev)) |
300 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
310 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
301 | else if (obj->tiling_mode != I915_TILING_NONE) |
311 | else if (obj->tiling_mode != I915_TILING_NONE) |
302 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
312 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
303 | else |
313 | else |
304 | I915_WRITE(SPRLINOFF(pipe), linear_offset); |
314 | I915_WRITE(SPRLINOFF(pipe), linear_offset); |
305 | 315 | ||
306 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
316 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
307 | if (intel_plane->can_scale) |
317 | if (intel_plane->can_scale) |
308 | I915_WRITE(SPRSCALE(pipe), sprscale); |
318 | I915_WRITE(SPRSCALE(pipe), sprscale); |
309 | I915_WRITE(SPRCTL(pipe), sprctl); |
319 | I915_WRITE(SPRCTL(pipe), sprctl); |
- | 320 | I915_MODIFY_DISPBASE(SPRSURF(pipe), |
|
310 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); |
321 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); |
311 | POSTING_READ(SPRSURF(pipe)); |
322 | POSTING_READ(SPRSURF(pipe)); |
312 | 323 | ||
313 | /* potentially re-enable LP watermarks */ |
324 | /* potentially re-enable LP watermarks */ |
314 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) |
325 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) |
315 | intel_update_watermarks(dev); |
326 | intel_update_watermarks(dev); |
316 | } |
327 | } |
317 | 328 | ||
318 | static void |
329 | static void |
319 | ivb_disable_plane(struct drm_plane *plane) |
330 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
320 | { |
331 | { |
321 | struct drm_device *dev = plane->dev; |
332 | struct drm_device *dev = plane->dev; |
322 | struct drm_i915_private *dev_priv = dev->dev_private; |
333 | struct drm_i915_private *dev_priv = dev->dev_private; |
323 | struct intel_plane *intel_plane = to_intel_plane(plane); |
334 | struct intel_plane *intel_plane = to_intel_plane(plane); |
324 | int pipe = intel_plane->pipe; |
335 | int pipe = intel_plane->pipe; |
325 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
336 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
326 | 337 | ||
327 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
338 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
328 | /* Can't leave the scaler enabled... */ |
339 | /* Can't leave the scaler enabled... */ |
329 | if (intel_plane->can_scale) |
340 | if (intel_plane->can_scale) |
330 | I915_WRITE(SPRSCALE(pipe), 0); |
341 | I915_WRITE(SPRSCALE(pipe), 0); |
331 | /* Activate double buffered register update */ |
342 | /* Activate double buffered register update */ |
332 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
343 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
333 | POSTING_READ(SPRSURF(pipe)); |
344 | POSTING_READ(SPRSURF(pipe)); |
334 | 345 | ||
335 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
346 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
- | 347 | ||
- | 348 | intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false); |
|
336 | 349 | ||
337 | /* potentially re-enable LP watermarks */ |
350 | /* potentially re-enable LP watermarks */ |
338 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) |
351 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) |
339 | intel_update_watermarks(dev); |
352 | intel_update_watermarks(dev); |
340 | } |
353 | } |
341 | 354 | ||
342 | static int |
355 | static int |
343 | ivb_update_colorkey(struct drm_plane *plane, |
356 | ivb_update_colorkey(struct drm_plane *plane, |
344 | struct drm_intel_sprite_colorkey *key) |
357 | struct drm_intel_sprite_colorkey *key) |
345 | { |
358 | { |
346 | struct drm_device *dev = plane->dev; |
359 | struct drm_device *dev = plane->dev; |
347 | struct drm_i915_private *dev_priv = dev->dev_private; |
360 | struct drm_i915_private *dev_priv = dev->dev_private; |
348 | struct intel_plane *intel_plane; |
361 | struct intel_plane *intel_plane; |
349 | u32 sprctl; |
362 | u32 sprctl; |
350 | int ret = 0; |
363 | int ret = 0; |
351 | 364 | ||
352 | intel_plane = to_intel_plane(plane); |
365 | intel_plane = to_intel_plane(plane); |
353 | 366 | ||
354 | I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); |
367 | I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); |
355 | I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value); |
368 | I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value); |
356 | I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask); |
369 | I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask); |
357 | 370 | ||
358 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); |
371 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); |
359 | sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY); |
372 | sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY); |
360 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
373 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
361 | sprctl |= SPRITE_DEST_KEY; |
374 | sprctl |= SPRITE_DEST_KEY; |
362 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
375 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
363 | sprctl |= SPRITE_SOURCE_KEY; |
376 | sprctl |= SPRITE_SOURCE_KEY; |
364 | I915_WRITE(SPRCTL(intel_plane->pipe), sprctl); |
377 | I915_WRITE(SPRCTL(intel_plane->pipe), sprctl); |
365 | 378 | ||
366 | POSTING_READ(SPRKEYMSK(intel_plane->pipe)); |
379 | POSTING_READ(SPRKEYMSK(intel_plane->pipe)); |
367 | 380 | ||
368 | return ret; |
381 | return ret; |
369 | } |
382 | } |
370 | 383 | ||
371 | static void |
384 | static void |
372 | ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
385 | ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
373 | { |
386 | { |
374 | struct drm_device *dev = plane->dev; |
387 | struct drm_device *dev = plane->dev; |
375 | struct drm_i915_private *dev_priv = dev->dev_private; |
388 | struct drm_i915_private *dev_priv = dev->dev_private; |
376 | struct intel_plane *intel_plane; |
389 | struct intel_plane *intel_plane; |
377 | u32 sprctl; |
390 | u32 sprctl; |
378 | 391 | ||
379 | intel_plane = to_intel_plane(plane); |
392 | intel_plane = to_intel_plane(plane); |
380 | 393 | ||
381 | key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe)); |
394 | key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe)); |
382 | key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe)); |
395 | key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe)); |
383 | key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe)); |
396 | key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe)); |
384 | key->flags = 0; |
397 | key->flags = 0; |
385 | 398 | ||
386 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); |
399 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); |
387 | 400 | ||
388 | if (sprctl & SPRITE_DEST_KEY) |
401 | if (sprctl & SPRITE_DEST_KEY) |
389 | key->flags = I915_SET_COLORKEY_DESTINATION; |
402 | key->flags = I915_SET_COLORKEY_DESTINATION; |
390 | else if (sprctl & SPRITE_SOURCE_KEY) |
403 | else if (sprctl & SPRITE_SOURCE_KEY) |
391 | key->flags = I915_SET_COLORKEY_SOURCE; |
404 | key->flags = I915_SET_COLORKEY_SOURCE; |
392 | else |
405 | else |
393 | key->flags = I915_SET_COLORKEY_NONE; |
406 | key->flags = I915_SET_COLORKEY_NONE; |
394 | } |
407 | } |
395 | 408 | ||
396 | static void |
409 | static void |
397 | ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, |
410 | ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
- | 411 | struct drm_framebuffer *fb, |
|
398 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
412 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
399 | unsigned int crtc_w, unsigned int crtc_h, |
413 | unsigned int crtc_w, unsigned int crtc_h, |
400 | uint32_t x, uint32_t y, |
414 | uint32_t x, uint32_t y, |
401 | uint32_t src_w, uint32_t src_h) |
415 | uint32_t src_w, uint32_t src_h) |
402 | { |
416 | { |
403 | struct drm_device *dev = plane->dev; |
417 | struct drm_device *dev = plane->dev; |
404 | struct drm_i915_private *dev_priv = dev->dev_private; |
418 | struct drm_i915_private *dev_priv = dev->dev_private; |
405 | struct intel_plane *intel_plane = to_intel_plane(plane); |
419 | struct intel_plane *intel_plane = to_intel_plane(plane); |
406 | int pipe = intel_plane->pipe; |
420 | int pipe = intel_plane->pipe; |
407 | unsigned long dvssurf_offset, linear_offset; |
421 | unsigned long dvssurf_offset, linear_offset; |
408 | u32 dvscntr, dvsscale; |
422 | u32 dvscntr, dvsscale; |
409 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
423 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
410 | 424 | ||
411 | dvscntr = I915_READ(DVSCNTR(pipe)); |
425 | dvscntr = I915_READ(DVSCNTR(pipe)); |
412 | 426 | ||
413 | /* Mask out pixel format bits in case we change it */ |
427 | /* Mask out pixel format bits in case we change it */ |
414 | dvscntr &= ~DVS_PIXFORMAT_MASK; |
428 | dvscntr &= ~DVS_PIXFORMAT_MASK; |
415 | dvscntr &= ~DVS_RGB_ORDER_XBGR; |
429 | dvscntr &= ~DVS_RGB_ORDER_XBGR; |
416 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; |
430 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; |
417 | dvscntr &= ~DVS_TILED; |
431 | dvscntr &= ~DVS_TILED; |
418 | 432 | ||
419 | switch (fb->pixel_format) { |
433 | switch (fb->pixel_format) { |
420 | case DRM_FORMAT_XBGR8888: |
434 | case DRM_FORMAT_XBGR8888: |
421 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
435 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
422 | break; |
436 | break; |
423 | case DRM_FORMAT_XRGB8888: |
437 | case DRM_FORMAT_XRGB8888: |
424 | dvscntr |= DVS_FORMAT_RGBX888; |
438 | dvscntr |= DVS_FORMAT_RGBX888; |
425 | break; |
439 | break; |
426 | case DRM_FORMAT_YUYV: |
440 | case DRM_FORMAT_YUYV: |
427 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
441 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
428 | break; |
442 | break; |
429 | case DRM_FORMAT_YVYU: |
443 | case DRM_FORMAT_YVYU: |
430 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
444 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
431 | break; |
445 | break; |
432 | case DRM_FORMAT_UYVY: |
446 | case DRM_FORMAT_UYVY: |
433 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
447 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
434 | break; |
448 | break; |
435 | case DRM_FORMAT_VYUY: |
449 | case DRM_FORMAT_VYUY: |
436 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
450 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
437 | break; |
451 | break; |
438 | default: |
452 | default: |
439 | BUG(); |
453 | BUG(); |
440 | } |
454 | } |
441 | 455 | ||
442 | if (obj->tiling_mode != I915_TILING_NONE) |
456 | if (obj->tiling_mode != I915_TILING_NONE) |
443 | dvscntr |= DVS_TILED; |
457 | dvscntr |= DVS_TILED; |
444 | 458 | ||
445 | if (IS_GEN6(dev)) |
459 | if (IS_GEN6(dev)) |
446 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
460 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
447 | dvscntr |= DVS_ENABLE; |
461 | dvscntr |= DVS_ENABLE; |
- | 462 | ||
- | 463 | intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true, |
|
- | 464 | src_w != crtc_w || src_h != crtc_h); |
|
448 | 465 | ||
449 | /* Sizes are 0 based */ |
466 | /* Sizes are 0 based */ |
450 | src_w--; |
467 | src_w--; |
451 | src_h--; |
468 | src_h--; |
452 | crtc_w--; |
469 | crtc_w--; |
453 | crtc_h--; |
470 | crtc_h--; |
454 | - | ||
455 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); |
- | |
456 | 471 | ||
457 | dvsscale = 0; |
472 | dvsscale = 0; |
458 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) |
473 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) |
459 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
474 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
460 | 475 | ||
461 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
476 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
462 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
477 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
463 | 478 | ||
464 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
479 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
465 | dvssurf_offset = |
480 | dvssurf_offset = |
466 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
481 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
467 | pixel_size, fb->pitches[0]); |
482 | pixel_size, fb->pitches[0]); |
468 | linear_offset -= dvssurf_offset; |
483 | linear_offset -= dvssurf_offset; |
469 | 484 | ||
470 | if (obj->tiling_mode != I915_TILING_NONE) |
485 | if (obj->tiling_mode != I915_TILING_NONE) |
471 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
486 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
472 | else |
487 | else |
473 | I915_WRITE(DVSLINOFF(pipe), linear_offset); |
488 | I915_WRITE(DVSLINOFF(pipe), linear_offset); |
474 | 489 | ||
475 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
490 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
476 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
491 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
477 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
492 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
- | 493 | I915_MODIFY_DISPBASE(DVSSURF(pipe), |
|
478 | I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset); |
494 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); |
479 | POSTING_READ(DVSSURF(pipe)); |
495 | POSTING_READ(DVSSURF(pipe)); |
480 | } |
496 | } |
481 | 497 | ||
482 | static void |
498 | static void |
483 | ilk_disable_plane(struct drm_plane *plane) |
499 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
484 | { |
500 | { |
485 | struct drm_device *dev = plane->dev; |
501 | struct drm_device *dev = plane->dev; |
486 | struct drm_i915_private *dev_priv = dev->dev_private; |
502 | struct drm_i915_private *dev_priv = dev->dev_private; |
487 | struct intel_plane *intel_plane = to_intel_plane(plane); |
503 | struct intel_plane *intel_plane = to_intel_plane(plane); |
488 | int pipe = intel_plane->pipe; |
504 | int pipe = intel_plane->pipe; |
489 | 505 | ||
490 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); |
506 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); |
491 | /* Disable the scaler */ |
507 | /* Disable the scaler */ |
492 | I915_WRITE(DVSSCALE(pipe), 0); |
508 | I915_WRITE(DVSSCALE(pipe), 0); |
493 | /* Flush double buffered register updates */ |
509 | /* Flush double buffered register updates */ |
494 | I915_MODIFY_DISPBASE(DVSSURF(pipe), 0); |
510 | I915_MODIFY_DISPBASE(DVSSURF(pipe), 0); |
495 | POSTING_READ(DVSSURF(pipe)); |
511 | POSTING_READ(DVSSURF(pipe)); |
- | 512 | ||
- | 513 | intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false); |
|
496 | } |
514 | } |
497 | 515 | ||
498 | static void |
516 | static void |
499 | intel_enable_primary(struct drm_crtc *crtc) |
517 | intel_enable_primary(struct drm_crtc *crtc) |
500 | { |
518 | { |
501 | struct drm_device *dev = crtc->dev; |
519 | struct drm_device *dev = crtc->dev; |
502 | struct drm_i915_private *dev_priv = dev->dev_private; |
520 | struct drm_i915_private *dev_priv = dev->dev_private; |
503 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
504 | int reg = DSPCNTR(intel_crtc->plane); |
522 | int reg = DSPCNTR(intel_crtc->plane); |
505 | 523 | ||
506 | if (!intel_crtc->primary_disabled) |
524 | if (!intel_crtc->primary_disabled) |
507 | return; |
525 | return; |
508 | 526 | ||
509 | intel_crtc->primary_disabled = false; |
527 | intel_crtc->primary_disabled = false; |
510 | intel_update_fbc(dev); |
528 | intel_update_fbc(dev); |
511 | 529 | ||
512 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
530 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
513 | } |
531 | } |
514 | 532 | ||
515 | static void |
533 | static void |
516 | intel_disable_primary(struct drm_crtc *crtc) |
534 | intel_disable_primary(struct drm_crtc *crtc) |
517 | { |
535 | { |
518 | struct drm_device *dev = crtc->dev; |
536 | struct drm_device *dev = crtc->dev; |
519 | struct drm_i915_private *dev_priv = dev->dev_private; |
537 | struct drm_i915_private *dev_priv = dev->dev_private; |
520 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
521 | int reg = DSPCNTR(intel_crtc->plane); |
539 | int reg = DSPCNTR(intel_crtc->plane); |
522 | 540 | ||
523 | if (intel_crtc->primary_disabled) |
541 | if (intel_crtc->primary_disabled) |
524 | return; |
542 | return; |
525 | 543 | ||
526 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
544 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
527 | 545 | ||
528 | intel_crtc->primary_disabled = true; |
546 | intel_crtc->primary_disabled = true; |
529 | intel_update_fbc(dev); |
547 | intel_update_fbc(dev); |
530 | } |
548 | } |
531 | 549 | ||
532 | static int |
550 | static int |
533 | ilk_update_colorkey(struct drm_plane *plane, |
551 | ilk_update_colorkey(struct drm_plane *plane, |
534 | struct drm_intel_sprite_colorkey *key) |
552 | struct drm_intel_sprite_colorkey *key) |
535 | { |
553 | { |
536 | struct drm_device *dev = plane->dev; |
554 | struct drm_device *dev = plane->dev; |
537 | struct drm_i915_private *dev_priv = dev->dev_private; |
555 | struct drm_i915_private *dev_priv = dev->dev_private; |
538 | struct intel_plane *intel_plane; |
556 | struct intel_plane *intel_plane; |
539 | u32 dvscntr; |
557 | u32 dvscntr; |
540 | int ret = 0; |
558 | int ret = 0; |
541 | 559 | ||
542 | intel_plane = to_intel_plane(plane); |
560 | intel_plane = to_intel_plane(plane); |
543 | 561 | ||
544 | I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value); |
562 | I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value); |
545 | I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value); |
563 | I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value); |
546 | I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask); |
564 | I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask); |
547 | 565 | ||
548 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); |
566 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); |
549 | dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY); |
567 | dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY); |
550 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
568 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
551 | dvscntr |= DVS_DEST_KEY; |
569 | dvscntr |= DVS_DEST_KEY; |
552 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
570 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
553 | dvscntr |= DVS_SOURCE_KEY; |
571 | dvscntr |= DVS_SOURCE_KEY; |
554 | I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr); |
572 | I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr); |
555 | 573 | ||
556 | POSTING_READ(DVSKEYMSK(intel_plane->pipe)); |
574 | POSTING_READ(DVSKEYMSK(intel_plane->pipe)); |
557 | 575 | ||
558 | return ret; |
576 | return ret; |
559 | } |
577 | } |
560 | 578 | ||
561 | static void |
579 | static void |
562 | ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
580 | ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
563 | { |
581 | { |
564 | struct drm_device *dev = plane->dev; |
582 | struct drm_device *dev = plane->dev; |
565 | struct drm_i915_private *dev_priv = dev->dev_private; |
583 | struct drm_i915_private *dev_priv = dev->dev_private; |
566 | struct intel_plane *intel_plane; |
584 | struct intel_plane *intel_plane; |
567 | u32 dvscntr; |
585 | u32 dvscntr; |
568 | 586 | ||
569 | intel_plane = to_intel_plane(plane); |
587 | intel_plane = to_intel_plane(plane); |
570 | 588 | ||
571 | key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe)); |
589 | key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe)); |
572 | key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe)); |
590 | key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe)); |
573 | key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe)); |
591 | key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe)); |
574 | key->flags = 0; |
592 | key->flags = 0; |
575 | 593 | ||
576 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); |
594 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); |
577 | 595 | ||
578 | if (dvscntr & DVS_DEST_KEY) |
596 | if (dvscntr & DVS_DEST_KEY) |
579 | key->flags = I915_SET_COLORKEY_DESTINATION; |
597 | key->flags = I915_SET_COLORKEY_DESTINATION; |
580 | else if (dvscntr & DVS_SOURCE_KEY) |
598 | else if (dvscntr & DVS_SOURCE_KEY) |
581 | key->flags = I915_SET_COLORKEY_SOURCE; |
599 | key->flags = I915_SET_COLORKEY_SOURCE; |
582 | else |
600 | else |
583 | key->flags = I915_SET_COLORKEY_NONE; |
601 | key->flags = I915_SET_COLORKEY_NONE; |
584 | } |
602 | } |
- | 603 | ||
- | 604 | static bool |
|
- | 605 | format_is_yuv(uint32_t format) |
|
- | 606 | { |
|
- | 607 | switch (format) { |
|
- | 608 | case DRM_FORMAT_YUYV: |
|
- | 609 | case DRM_FORMAT_UYVY: |
|
- | 610 | case DRM_FORMAT_VYUY: |
|
- | 611 | case DRM_FORMAT_YVYU: |
|
- | 612 | return true; |
|
- | 613 | default: |
|
- | 614 | return false; |
|
- | 615 | } |
|
- | 616 | } |
|
585 | 617 | ||
586 | static int |
618 | static int |
587 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
619 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
588 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
620 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
589 | unsigned int crtc_w, unsigned int crtc_h, |
621 | unsigned int crtc_w, unsigned int crtc_h, |
590 | uint32_t src_x, uint32_t src_y, |
622 | uint32_t src_x, uint32_t src_y, |
591 | uint32_t src_w, uint32_t src_h) |
623 | uint32_t src_w, uint32_t src_h) |
592 | { |
624 | { |
593 | struct drm_device *dev = plane->dev; |
625 | struct drm_device *dev = plane->dev; |
594 | struct drm_i915_private *dev_priv = dev->dev_private; |
626 | struct drm_i915_private *dev_priv = dev->dev_private; |
595 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
627 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
596 | struct intel_plane *intel_plane = to_intel_plane(plane); |
628 | struct intel_plane *intel_plane = to_intel_plane(plane); |
597 | struct intel_framebuffer *intel_fb; |
629 | struct intel_framebuffer *intel_fb; |
598 | struct drm_i915_gem_object *obj, *old_obj; |
630 | struct drm_i915_gem_object *obj, *old_obj; |
599 | int pipe = intel_plane->pipe; |
631 | int pipe = intel_plane->pipe; |
600 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
632 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
601 | pipe); |
633 | pipe); |
602 | int ret = 0; |
634 | int ret = 0; |
603 | int x = src_x >> 16, y = src_y >> 16; |
- | |
604 | int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay; |
- | |
605 | bool disable_primary = false; |
635 | bool disable_primary = false; |
- | 636 | bool visible; |
|
- | 637 | int hscale, vscale; |
|
- | 638 | int max_scale, min_scale; |
|
- | 639 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
|
- | 640 | struct drm_rect src = { |
|
- | 641 | /* sample coordinates in 16.16 fixed point */ |
|
- | 642 | .x1 = src_x, |
|
- | 643 | .x2 = src_x + src_w, |
|
- | 644 | .y1 = src_y, |
|
- | 645 | .y2 = src_y + src_h, |
|
- | 646 | }; |
|
- | 647 | struct drm_rect dst = { |
|
- | 648 | /* integer pixels */ |
|
- | 649 | .x1 = crtc_x, |
|
- | 650 | .x2 = crtc_x + crtc_w, |
|
- | 651 | .y1 = crtc_y, |
|
- | 652 | .y2 = crtc_y + crtc_h, |
|
- | 653 | }; |
|
- | 654 | const struct drm_rect clip = { |
|
- | 655 | .x2 = crtc->mode.hdisplay, |
|
- | 656 | .y2 = crtc->mode.vdisplay, |
|
- | 657 | }; |
|
606 | 658 | ||
607 | intel_fb = to_intel_framebuffer(fb); |
659 | intel_fb = to_intel_framebuffer(fb); |
608 | obj = intel_fb->obj; |
660 | obj = intel_fb->obj; |
609 | 661 | ||
610 | old_obj = intel_plane->obj; |
662 | old_obj = intel_plane->obj; |
611 | 663 | ||
612 | intel_plane->crtc_x = crtc_x; |
664 | intel_plane->crtc_x = crtc_x; |
613 | intel_plane->crtc_y = crtc_y; |
665 | intel_plane->crtc_y = crtc_y; |
614 | intel_plane->crtc_w = crtc_w; |
666 | intel_plane->crtc_w = crtc_w; |
615 | intel_plane->crtc_h = crtc_h; |
667 | intel_plane->crtc_h = crtc_h; |
616 | intel_plane->src_x = src_x; |
668 | intel_plane->src_x = src_x; |
617 | intel_plane->src_y = src_y; |
669 | intel_plane->src_y = src_y; |
618 | intel_plane->src_w = src_w; |
670 | intel_plane->src_w = src_w; |
619 | intel_plane->src_h = src_h; |
671 | intel_plane->src_h = src_h; |
620 | - | ||
621 | src_w = src_w >> 16; |
- | |
622 | src_h = src_h >> 16; |
- | |
623 | 672 | ||
624 | /* Pipe must be running... */ |
673 | /* Pipe must be running... */ |
- | 674 | if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) { |
|
625 | if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) |
675 | DRM_DEBUG_KMS("Pipe disabled\n"); |
- | 676 | return -EINVAL; |
|
- | 677 | } |
|
626 | return -EINVAL; |
678 | |
- | 679 | /* Don't modify another pipe's plane */ |
|
627 | 680 | if (intel_plane->pipe != intel_crtc->pipe) { |
|
- | 681 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); |
|
628 | if (crtc_x >= primary_w || crtc_y >= primary_h) |
682 | return -EINVAL; |
629 | return -EINVAL; |
683 | } |
- | 684 | ||
630 | 685 | /* FIXME check all gen limits */ |
|
- | 686 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { |
|
631 | /* Don't modify another pipe's plane */ |
687 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); |
632 | if (intel_plane->pipe != intel_crtc->pipe) |
688 | return -EINVAL; |
633 | return -EINVAL; |
689 | } |
634 | 690 | ||
635 | /* Sprite planes can be linear or x-tiled surfaces */ |
691 | /* Sprite planes can be linear or x-tiled surfaces */ |
636 | switch (obj->tiling_mode) { |
692 | switch (obj->tiling_mode) { |
637 | case I915_TILING_NONE: |
693 | case I915_TILING_NONE: |
638 | case I915_TILING_X: |
694 | case I915_TILING_X: |
639 | break; |
695 | break; |
640 | default: |
696 | default: |
- | 697 | DRM_DEBUG_KMS("Unsupported tiling mode\n"); |
|
641 | return -EINVAL; |
698 | return -EINVAL; |
642 | } |
699 | } |
643 | 700 | ||
644 | /* |
701 | /* |
645 | * Clamp the width & height into the visible area. Note we don't |
702 | * FIXME the following code does a bunch of fuzzy adjustments to the |
646 | * try to scale the source if part of the visible region is offscreen. |
703 | * coordinates and sizes. We probably need some way to decide whether |
647 | * The caller must handle that by adjusting source offset and size. |
704 | * more strict checking should be done instead. |
648 | */ |
705 | */ |
649 | if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) { |
706 | max_scale = intel_plane->max_downscale << 16; |
- | 707 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); |
|
- | 708 | ||
- | 709 | hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale); |
|
- | 710 | BUG_ON(hscale < 0); |
|
- | 711 | ||
- | 712 | vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale); |
|
- | 713 | BUG_ON(vscale < 0); |
|
- | 714 | ||
- | 715 | visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale); |
|
- | 716 | ||
650 | crtc_w += crtc_x; |
717 | crtc_x = dst.x1; |
651 | crtc_x = 0; |
718 | crtc_y = dst.y1; |
- | 719 | crtc_w = drm_rect_width(&dst); |
|
- | 720 | crtc_h = drm_rect_height(&dst); |
|
- | 721 | ||
- | 722 | if (visible) { |
|
- | 723 | /* check again in case clipping clamped the results */ |
|
- | 724 | hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale); |
|
- | 725 | if (hscale < 0) { |
|
- | 726 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); |
|
- | 727 | drm_rect_debug_print(&src, true); |
|
- | 728 | drm_rect_debug_print(&dst, false); |
|
- | 729 | ||
- | 730 | return hscale; |
|
652 | } |
731 | } |
653 | if ((crtc_x + crtc_w) <= 0) /* Nothing to display */ |
- | |
654 | goto out; |
- | |
655 | if ((crtc_x + crtc_w) > primary_w) |
- | |
656 | crtc_w = primary_w - crtc_x; |
- | |
657 | 732 | ||
658 | if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) { |
733 | vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale); |
- | 734 | if (vscale < 0) { |
|
- | 735 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); |
|
- | 736 | drm_rect_debug_print(&src, true); |
|
- | 737 | drm_rect_debug_print(&dst, false); |
|
659 | crtc_h += crtc_y; |
738 | |
660 | crtc_y = 0; |
739 | return vscale; |
661 | } |
- | |
662 | if ((crtc_y + crtc_h) <= 0) /* Nothing to display */ |
- | |
663 | goto out; |
- | |
664 | if (crtc_y + crtc_h > primary_h) |
- | |
- | 740 | } |
|
- | 741 | ||
- | 742 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
|
- | 743 | drm_rect_adjust_size(&src, |
|
- | 744 | drm_rect_width(&dst) * hscale - drm_rect_width(&src), |
|
665 | crtc_h = primary_h - crtc_y; |
745 | drm_rect_height(&dst) * vscale - drm_rect_height(&src)); |
- | 746 | ||
666 | 747 | /* sanity check to make sure the src viewport wasn't enlarged */ |
|
- | 748 | WARN_ON(src.x1 < (int) src_x || |
|
- | 749 | src.y1 < (int) src_y || |
|
667 | if (!crtc_w || !crtc_h) /* Again, nothing to display */ |
750 | src.x2 > (int) (src_x + src_w) || |
- | 751 | src.y2 > (int) (src_y + src_h)); |
|
- | 752 | ||
668 | goto out; |
753 | /* |
- | 754 | * Hardware doesn't handle subpixel coordinates. |
|
669 | 755 | * Adjust to (macro)pixel boundary, but be careful not to |
|
- | 756 | * increase the source viewport size, because that could |
|
670 | /* |
757 | * push the downscaling factor out of bounds. |
- | 758 | */ |
|
- | 759 | src_x = src.x1 >> 16; |
|
- | 760 | src_w = drm_rect_width(&src) >> 16; |
|
- | 761 | src_y = src.y1 >> 16; |
|
- | 762 | src_h = drm_rect_height(&src) >> 16; |
|
671 | * We may not have a scaler, eg. HSW does not have it any more |
763 | |
672 | */ |
764 | if (format_is_yuv(fb->pixel_format)) { |
673 | if (!intel_plane->can_scale && (crtc_w != src_w || crtc_h != src_h)) |
765 | src_x &= ~1; |
674 | return -EINVAL; |
766 | src_w &= ~1; |
675 | 767 | ||
- | 768 | /* |
|
- | 769 | * Must keep src and dst the |
|
- | 770 | * same if we can't scale. |
|
- | 771 | */ |
|
- | 772 | if (!intel_plane->can_scale) |
|
- | 773 | crtc_w &= ~1; |
|
- | 774 | ||
- | 775 | if (crtc_w == 0) |
|
- | 776 | visible = false; |
|
676 | /* |
777 | } |
- | 778 | } |
|
- | 779 | ||
- | 780 | /* Check size restrictions when scaling */ |
|
- | 781 | if (visible && (src_w != crtc_w || src_h != crtc_h)) { |
|
- | 782 | unsigned int width_bytes; |
|
- | 783 | ||
- | 784 | WARN_ON(!intel_plane->can_scale); |
|
- | 785 | ||
- | 786 | /* FIXME interlacing min height is 6 */ |
|
- | 787 | ||
- | 788 | if (crtc_w < 3 || crtc_h < 3) |
|
- | 789 | visible = false; |
|
- | 790 | ||
- | 791 | if (src_w < 3 || src_h < 3) |
|
- | 792 | visible = false; |
|
- | 793 | ||
- | 794 | width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size; |
|
677 | * We can take a larger source and scale it down, but |
795 | |
- | 796 | if (src_w > 2048 || src_h > 2048 || |
|
- | 797 | width_bytes > 4096 || fb->pitches[0] > 4096) { |
|
- | 798 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); |
|
- | 799 | return -EINVAL; |
|
- | 800 | } |
|
- | 801 | } |
|
- | 802 | ||
678 | * only so much... 16x is the max on SNB. |
803 | dst.x1 = crtc_x; |
679 | */ |
804 | dst.x2 = crtc_x + crtc_w; |
680 | if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale) |
805 | dst.y1 = crtc_y; |
681 | return -EINVAL; |
806 | dst.y2 = crtc_y + crtc_h; |
682 | 807 | ||
683 | /* |
808 | /* |
684 | * If the sprite is completely covering the primary plane, |
809 | * If the sprite is completely covering the primary plane, |
685 | * we can disable the primary and save power. |
810 | * we can disable the primary and save power. |
686 | */ |
811 | */ |
687 | if ((crtc_x == 0) && (crtc_y == 0) && |
- | |
688 | (crtc_w == primary_w) && (crtc_h == primary_h)) |
812 | disable_primary = drm_rect_equals(&dst, &clip); |
689 | disable_primary = true; |
813 | WARN_ON(disable_primary && !visible); |
690 | 814 | ||
691 | mutex_lock(&dev->struct_mutex); |
815 | mutex_lock(&dev->struct_mutex); |
692 | 816 | ||
693 | /* Note that this will apply the VT-d workaround for scanouts, |
817 | /* Note that this will apply the VT-d workaround for scanouts, |
694 | * which is more restrictive than required for sprites. (The |
818 | * which is more restrictive than required for sprites. (The |
695 | * primary plane requires 256KiB alignment with 64 PTE padding, |
819 | * primary plane requires 256KiB alignment with 64 PTE padding, |
696 | * the sprite planes only require 128KiB alignment and 32 PTE padding. |
820 | * the sprite planes only require 128KiB alignment and 32 PTE padding. |
697 | */ |
821 | */ |
698 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
822 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
699 | if (ret) |
823 | if (ret) |
700 | goto out_unlock; |
824 | goto out_unlock; |
701 | 825 | ||
702 | intel_plane->obj = obj; |
826 | intel_plane->obj = obj; |
703 | 827 | ||
704 | /* |
828 | /* |
705 | * Be sure to re-enable the primary before the sprite is no longer |
829 | * Be sure to re-enable the primary before the sprite is no longer |
706 | * covering it fully. |
830 | * covering it fully. |
707 | */ |
831 | */ |
708 | if (!disable_primary) |
832 | if (!disable_primary) |
709 | intel_enable_primary(crtc); |
833 | intel_enable_primary(crtc); |
- | 834 | ||
710 | 835 | if (visible) |
|
- | 836 | intel_plane->update_plane(plane, crtc, fb, obj, |
|
711 | intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y, |
837 | crtc_x, crtc_y, crtc_w, crtc_h, |
- | 838 | src_x, src_y, src_w, src_h); |
|
- | 839 | else |
|
712 | crtc_w, crtc_h, x, y, src_w, src_h); |
840 | intel_plane->disable_plane(plane, crtc); |
713 | 841 | ||
714 | if (disable_primary) |
842 | if (disable_primary) |
715 | intel_disable_primary(crtc); |
843 | intel_disable_primary(crtc); |
716 | 844 | ||
717 | /* Unpin old obj after new one is active to avoid ugliness */ |
845 | /* Unpin old obj after new one is active to avoid ugliness */ |
718 | if (old_obj) { |
846 | if (old_obj) { |
719 | /* |
847 | /* |
720 | * It's fairly common to simply update the position of |
848 | * It's fairly common to simply update the position of |
721 | * an existing object. In that case, we don't need to |
849 | * an existing object. In that case, we don't need to |
722 | * wait for vblank to avoid ugliness, we only need to |
850 | * wait for vblank to avoid ugliness, we only need to |
723 | * do the pin & ref bookkeeping. |
851 | * do the pin & ref bookkeeping. |
724 | */ |
852 | */ |
725 | if (old_obj != obj) { |
853 | if (old_obj != obj) { |
726 | mutex_unlock(&dev->struct_mutex); |
854 | mutex_unlock(&dev->struct_mutex); |
727 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); |
855 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); |
728 | mutex_lock(&dev->struct_mutex); |
856 | mutex_lock(&dev->struct_mutex); |
729 | } |
857 | } |
730 | intel_unpin_fb_obj(old_obj); |
858 | intel_unpin_fb_obj(old_obj); |
731 | } |
859 | } |
732 | 860 | ||
733 | out_unlock: |
861 | out_unlock: |
734 | mutex_unlock(&dev->struct_mutex); |
862 | mutex_unlock(&dev->struct_mutex); |
735 | out: |
- | |
736 | return ret; |
863 | return ret; |
737 | } |
864 | } |
738 | 865 | ||
739 | static int |
866 | static int |
740 | intel_disable_plane(struct drm_plane *plane) |
867 | intel_disable_plane(struct drm_plane *plane) |
741 | { |
868 | { |
742 | struct drm_device *dev = plane->dev; |
869 | struct drm_device *dev = plane->dev; |
743 | struct intel_plane *intel_plane = to_intel_plane(plane); |
870 | struct intel_plane *intel_plane = to_intel_plane(plane); |
744 | int ret = 0; |
871 | int ret = 0; |
745 | 872 | ||
- | 873 | if (!plane->fb) |
|
- | 874 | return 0; |
|
- | 875 | ||
- | 876 | if (WARN_ON(!plane->crtc)) |
|
- | 877 | return -EINVAL; |
|
746 | if (plane->crtc) |
878 | |
747 | intel_enable_primary(plane->crtc); |
879 | intel_enable_primary(plane->crtc); |
748 | intel_plane->disable_plane(plane); |
880 | intel_plane->disable_plane(plane, plane->crtc); |
749 | 881 | ||
750 | if (!intel_plane->obj) |
882 | if (!intel_plane->obj) |
751 | goto out; |
883 | goto out; |
752 | 884 | ||
753 | intel_wait_for_vblank(dev, intel_plane->pipe); |
885 | intel_wait_for_vblank(dev, intel_plane->pipe); |
754 | 886 | ||
755 | mutex_lock(&dev->struct_mutex); |
887 | mutex_lock(&dev->struct_mutex); |
756 | intel_unpin_fb_obj(intel_plane->obj); |
888 | intel_unpin_fb_obj(intel_plane->obj); |
757 | intel_plane->obj = NULL; |
889 | intel_plane->obj = NULL; |
758 | mutex_unlock(&dev->struct_mutex); |
890 | mutex_unlock(&dev->struct_mutex); |
759 | out: |
891 | out: |
760 | 892 | ||
761 | return ret; |
893 | return ret; |
762 | } |
894 | } |
763 | 895 | ||
764 | static void intel_destroy_plane(struct drm_plane *plane) |
896 | static void intel_destroy_plane(struct drm_plane *plane) |
765 | { |
897 | { |
766 | struct intel_plane *intel_plane = to_intel_plane(plane); |
898 | struct intel_plane *intel_plane = to_intel_plane(plane); |
767 | intel_disable_plane(plane); |
899 | intel_disable_plane(plane); |
768 | drm_plane_cleanup(plane); |
900 | drm_plane_cleanup(plane); |
769 | kfree(intel_plane); |
901 | kfree(intel_plane); |
770 | } |
902 | } |
771 | 903 | ||
772 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
904 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
773 | struct drm_file *file_priv) |
905 | struct drm_file *file_priv) |
774 | { |
906 | { |
775 | struct drm_intel_sprite_colorkey *set = data; |
907 | struct drm_intel_sprite_colorkey *set = data; |
776 | struct drm_mode_object *obj; |
908 | struct drm_mode_object *obj; |
777 | struct drm_plane *plane; |
909 | struct drm_plane *plane; |
778 | struct intel_plane *intel_plane; |
910 | struct intel_plane *intel_plane; |
779 | int ret = 0; |
911 | int ret = 0; |
780 | 912 | ||
781 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
913 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
782 | return -ENODEV; |
914 | return -ENODEV; |
783 | 915 | ||
784 | /* Make sure we don't try to enable both src & dest simultaneously */ |
916 | /* Make sure we don't try to enable both src & dest simultaneously */ |
785 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
917 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
786 | return -EINVAL; |
918 | return -EINVAL; |
787 | 919 | ||
788 | drm_modeset_lock_all(dev); |
920 | drm_modeset_lock_all(dev); |
789 | 921 | ||
790 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); |
922 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); |
791 | if (!obj) { |
923 | if (!obj) { |
792 | ret = -EINVAL; |
924 | ret = -EINVAL; |
793 | goto out_unlock; |
925 | goto out_unlock; |
794 | } |
926 | } |
795 | 927 | ||
796 | plane = obj_to_plane(obj); |
928 | plane = obj_to_plane(obj); |
797 | intel_plane = to_intel_plane(plane); |
929 | intel_plane = to_intel_plane(plane); |
798 | ret = intel_plane->update_colorkey(plane, set); |
930 | ret = intel_plane->update_colorkey(plane, set); |
799 | 931 | ||
800 | out_unlock: |
932 | out_unlock: |
801 | drm_modeset_unlock_all(dev); |
933 | drm_modeset_unlock_all(dev); |
802 | return ret; |
934 | return ret; |
803 | } |
935 | } |
804 | 936 | ||
805 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
937 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
806 | struct drm_file *file_priv) |
938 | struct drm_file *file_priv) |
807 | { |
939 | { |
808 | struct drm_intel_sprite_colorkey *get = data; |
940 | struct drm_intel_sprite_colorkey *get = data; |
809 | struct drm_mode_object *obj; |
941 | struct drm_mode_object *obj; |
810 | struct drm_plane *plane; |
942 | struct drm_plane *plane; |
811 | struct intel_plane *intel_plane; |
943 | struct intel_plane *intel_plane; |
812 | int ret = 0; |
944 | int ret = 0; |
813 | 945 | ||
814 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
946 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
815 | return -ENODEV; |
947 | return -ENODEV; |
816 | 948 | ||
817 | drm_modeset_lock_all(dev); |
949 | drm_modeset_lock_all(dev); |
818 | 950 | ||
819 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); |
951 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); |
820 | if (!obj) { |
952 | if (!obj) { |
821 | ret = -EINVAL; |
953 | ret = -EINVAL; |
822 | goto out_unlock; |
954 | goto out_unlock; |
823 | } |
955 | } |
824 | 956 | ||
825 | plane = obj_to_plane(obj); |
957 | plane = obj_to_plane(obj); |
826 | intel_plane = to_intel_plane(plane); |
958 | intel_plane = to_intel_plane(plane); |
827 | intel_plane->get_colorkey(plane, get); |
959 | intel_plane->get_colorkey(plane, get); |
828 | 960 | ||
829 | out_unlock: |
961 | out_unlock: |
830 | drm_modeset_unlock_all(dev); |
962 | drm_modeset_unlock_all(dev); |
831 | return ret; |
963 | return ret; |
832 | } |
964 | } |
833 | 965 | ||
834 | void intel_plane_restore(struct drm_plane *plane) |
966 | void intel_plane_restore(struct drm_plane *plane) |
835 | { |
967 | { |
836 | struct intel_plane *intel_plane = to_intel_plane(plane); |
968 | struct intel_plane *intel_plane = to_intel_plane(plane); |
837 | 969 | ||
838 | if (!plane->crtc || !plane->fb) |
970 | if (!plane->crtc || !plane->fb) |
839 | return; |
971 | return; |
840 | 972 | ||
841 | intel_update_plane(plane, plane->crtc, plane->fb, |
973 | intel_update_plane(plane, plane->crtc, plane->fb, |
842 | intel_plane->crtc_x, intel_plane->crtc_y, |
974 | intel_plane->crtc_x, intel_plane->crtc_y, |
843 | intel_plane->crtc_w, intel_plane->crtc_h, |
975 | intel_plane->crtc_w, intel_plane->crtc_h, |
844 | intel_plane->src_x, intel_plane->src_y, |
976 | intel_plane->src_x, intel_plane->src_y, |
845 | intel_plane->src_w, intel_plane->src_h); |
977 | intel_plane->src_w, intel_plane->src_h); |
846 | } |
978 | } |
- | 979 | ||
- | 980 | void intel_plane_disable(struct drm_plane *plane) |
|
- | 981 | { |
|
- | 982 | if (!plane->crtc || !plane->fb) |
|
- | 983 | return; |
|
- | 984 | ||
- | 985 | intel_disable_plane(plane); |
|
- | 986 | } |
|
847 | 987 | ||
848 | static const struct drm_plane_funcs intel_plane_funcs = { |
988 | static const struct drm_plane_funcs intel_plane_funcs = { |
849 | .update_plane = intel_update_plane, |
989 | .update_plane = intel_update_plane, |
850 | .disable_plane = intel_disable_plane, |
990 | .disable_plane = intel_disable_plane, |
851 | .destroy = intel_destroy_plane, |
991 | .destroy = intel_destroy_plane, |
852 | }; |
992 | }; |
853 | 993 | ||
854 | static uint32_t ilk_plane_formats[] = { |
994 | static uint32_t ilk_plane_formats[] = { |
855 | DRM_FORMAT_XRGB8888, |
995 | DRM_FORMAT_XRGB8888, |
856 | DRM_FORMAT_YUYV, |
996 | DRM_FORMAT_YUYV, |
857 | DRM_FORMAT_YVYU, |
997 | DRM_FORMAT_YVYU, |
858 | DRM_FORMAT_UYVY, |
998 | DRM_FORMAT_UYVY, |
859 | DRM_FORMAT_VYUY, |
999 | DRM_FORMAT_VYUY, |
860 | }; |
1000 | }; |
861 | 1001 | ||
862 | static uint32_t snb_plane_formats[] = { |
1002 | static uint32_t snb_plane_formats[] = { |
863 | DRM_FORMAT_XBGR8888, |
1003 | DRM_FORMAT_XBGR8888, |
864 | DRM_FORMAT_XRGB8888, |
1004 | DRM_FORMAT_XRGB8888, |
865 | DRM_FORMAT_YUYV, |
1005 | DRM_FORMAT_YUYV, |
866 | DRM_FORMAT_YVYU, |
1006 | DRM_FORMAT_YVYU, |
867 | DRM_FORMAT_UYVY, |
1007 | DRM_FORMAT_UYVY, |
868 | DRM_FORMAT_VYUY, |
1008 | DRM_FORMAT_VYUY, |
869 | }; |
1009 | }; |
870 | 1010 | ||
871 | static uint32_t vlv_plane_formats[] = { |
1011 | static uint32_t vlv_plane_formats[] = { |
872 | DRM_FORMAT_RGB565, |
1012 | DRM_FORMAT_RGB565, |
873 | DRM_FORMAT_ABGR8888, |
1013 | DRM_FORMAT_ABGR8888, |
874 | DRM_FORMAT_ARGB8888, |
1014 | DRM_FORMAT_ARGB8888, |
875 | DRM_FORMAT_XBGR8888, |
1015 | DRM_FORMAT_XBGR8888, |
876 | DRM_FORMAT_XRGB8888, |
1016 | DRM_FORMAT_XRGB8888, |
877 | DRM_FORMAT_XBGR2101010, |
1017 | DRM_FORMAT_XBGR2101010, |
878 | DRM_FORMAT_ABGR2101010, |
1018 | DRM_FORMAT_ABGR2101010, |
879 | DRM_FORMAT_YUYV, |
1019 | DRM_FORMAT_YUYV, |
880 | DRM_FORMAT_YVYU, |
1020 | DRM_FORMAT_YVYU, |
881 | DRM_FORMAT_UYVY, |
1021 | DRM_FORMAT_UYVY, |
882 | DRM_FORMAT_VYUY, |
1022 | DRM_FORMAT_VYUY, |
883 | }; |
1023 | }; |
884 | 1024 | ||
885 | int |
1025 | int |
886 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
1026 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
887 | { |
1027 | { |
888 | struct intel_plane *intel_plane; |
1028 | struct intel_plane *intel_plane; |
889 | unsigned long possible_crtcs; |
1029 | unsigned long possible_crtcs; |
890 | const uint32_t *plane_formats; |
1030 | const uint32_t *plane_formats; |
891 | int num_plane_formats; |
1031 | int num_plane_formats; |
892 | int ret; |
1032 | int ret; |
893 | 1033 | ||
894 | if (INTEL_INFO(dev)->gen < 5) |
1034 | if (INTEL_INFO(dev)->gen < 5) |
895 | return -ENODEV; |
1035 | return -ENODEV; |
896 | 1036 | ||
897 | intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); |
1037 | intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); |
898 | if (!intel_plane) |
1038 | if (!intel_plane) |
899 | return -ENOMEM; |
1039 | return -ENOMEM; |
900 | 1040 | ||
901 | switch (INTEL_INFO(dev)->gen) { |
1041 | switch (INTEL_INFO(dev)->gen) { |
902 | case 5: |
1042 | case 5: |
903 | case 6: |
1043 | case 6: |
904 | intel_plane->can_scale = true; |
1044 | intel_plane->can_scale = true; |
905 | intel_plane->max_downscale = 16; |
1045 | intel_plane->max_downscale = 16; |
906 | intel_plane->update_plane = ilk_update_plane; |
1046 | intel_plane->update_plane = ilk_update_plane; |
907 | intel_plane->disable_plane = ilk_disable_plane; |
1047 | intel_plane->disable_plane = ilk_disable_plane; |
908 | intel_plane->update_colorkey = ilk_update_colorkey; |
1048 | intel_plane->update_colorkey = ilk_update_colorkey; |
909 | intel_plane->get_colorkey = ilk_get_colorkey; |
1049 | intel_plane->get_colorkey = ilk_get_colorkey; |
910 | 1050 | ||
911 | if (IS_GEN6(dev)) { |
1051 | if (IS_GEN6(dev)) { |
912 | plane_formats = snb_plane_formats; |
1052 | plane_formats = snb_plane_formats; |
913 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
1053 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
914 | } else { |
1054 | } else { |
915 | plane_formats = ilk_plane_formats; |
1055 | plane_formats = ilk_plane_formats; |
916 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
1056 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
917 | } |
1057 | } |
918 | break; |
1058 | break; |
919 | 1059 | ||
920 | case 7: |
1060 | case 7: |
921 | if (IS_HASWELL(dev) || IS_VALLEYVIEW(dev)) |
1061 | if (IS_IVYBRIDGE(dev)) { |
922 | intel_plane->can_scale = false; |
- | |
923 | else |
- | |
924 | intel_plane->can_scale = true; |
1062 | intel_plane->can_scale = true; |
- | 1063 | intel_plane->max_downscale = 2; |
|
- | 1064 | } else { |
|
- | 1065 | intel_plane->can_scale = false; |
|
- | 1066 | intel_plane->max_downscale = 1; |
|
- | 1067 | } |
|
925 | 1068 | ||
926 | if (IS_VALLEYVIEW(dev)) { |
- | |
927 | intel_plane->max_downscale = 1; |
1069 | if (IS_VALLEYVIEW(dev)) { |
928 | intel_plane->update_plane = vlv_update_plane; |
1070 | intel_plane->update_plane = vlv_update_plane; |
929 | intel_plane->disable_plane = vlv_disable_plane; |
1071 | intel_plane->disable_plane = vlv_disable_plane; |
930 | intel_plane->update_colorkey = vlv_update_colorkey; |
1072 | intel_plane->update_colorkey = vlv_update_colorkey; |
931 | intel_plane->get_colorkey = vlv_get_colorkey; |
1073 | intel_plane->get_colorkey = vlv_get_colorkey; |
932 | 1074 | ||
933 | plane_formats = vlv_plane_formats; |
1075 | plane_formats = vlv_plane_formats; |
934 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); |
1076 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); |
935 | } else { |
1077 | } else { |
936 | intel_plane->max_downscale = 2; |
- | |
937 | intel_plane->update_plane = ivb_update_plane; |
1078 | intel_plane->update_plane = ivb_update_plane; |
938 | intel_plane->disable_plane = ivb_disable_plane; |
1079 | intel_plane->disable_plane = ivb_disable_plane; |
939 | intel_plane->update_colorkey = ivb_update_colorkey; |
1080 | intel_plane->update_colorkey = ivb_update_colorkey; |
940 | intel_plane->get_colorkey = ivb_get_colorkey; |
1081 | intel_plane->get_colorkey = ivb_get_colorkey; |
941 | 1082 | ||
942 | plane_formats = snb_plane_formats; |
1083 | plane_formats = snb_plane_formats; |
943 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
1084 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
944 | } |
1085 | } |
945 | break; |
1086 | break; |
946 | 1087 | ||
947 | default: |
1088 | default: |
948 | kfree(intel_plane); |
1089 | kfree(intel_plane); |
949 | return -ENODEV; |
1090 | return -ENODEV; |
950 | } |
1091 | } |
951 | 1092 | ||
952 | intel_plane->pipe = pipe; |
1093 | intel_plane->pipe = pipe; |
953 | intel_plane->plane = plane; |
1094 | intel_plane->plane = plane; |
954 | possible_crtcs = (1 << pipe); |
1095 | possible_crtcs = (1 << pipe); |
955 | ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, |
1096 | ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, |
956 | &intel_plane_funcs, |
1097 | &intel_plane_funcs, |
957 | plane_formats, num_plane_formats, |
1098 | plane_formats, num_plane_formats, |
958 | false); |
1099 | false); |
959 | if (ret) |
1100 | if (ret) |
960 | kfree(intel_plane); |
1101 | kfree(intel_plane); |
961 | 1102 | ||
962 | return ret; |
1103 | return ret; |
963 | }><>>=>>=>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
1104 | }><>>>>>>>>>>>>><>><>>>->><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |